1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 * Based on r8a779a0-cpg-mssr.c 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/kernel.h> 16 #include <linux/soc/renesas/rcar-rst.h> 17 18 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 19 20 #include "renesas-cpg-mssr.h" 21 #include "rcar-gen4-cpg.h" 22 23 enum clk_ids { 24 /* Core Clock Outputs exported to DT */ 25 LAST_DT_CORE_CLK = R8A779F0_CLK_R, 26 27 /* External Input Clocks */ 28 CLK_EXTAL, 29 CLK_EXTALR, 30 31 /* Internal Core Clocks */ 32 CLK_MAIN, 33 CLK_PLL1, 34 CLK_PLL2, 35 CLK_PLL3, 36 CLK_PLL5, 37 CLK_PLL6, 38 CLK_PLL1_DIV2, 39 CLK_PLL2_DIV2, 40 CLK_PLL3_DIV2, 41 CLK_PLL5_DIV2, 42 CLK_PLL5_DIV4, 43 CLK_PLL6_DIV2, 44 CLK_S0, 45 CLK_SDSRC, 46 CLK_RPCSRC, 47 CLK_OCO, 48 49 /* Module Clocks */ 50 MOD_CLK_BASE 51 }; 52 53 static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 54 /* External Clock Inputs */ 55 DEF_INPUT("extal", CLK_EXTAL), 56 DEF_INPUT("extalr", CLK_EXTALR), 57 58 /* Internal Core Clocks */ 59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), 60 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), 61 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), 62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), 63 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), 64 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), 65 66 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 67 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), 68 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), 69 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 70 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 71 DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), 72 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 73 74 DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), 75 DEF_RATE(".oco", CLK_OCO, 32768), 76 77 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), 78 79 /* Core Clock Outputs */ 80 DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), 81 DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), 82 DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), 83 DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1), 84 DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1), 85 DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1), 86 DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1), 87 DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1), 88 DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1), 89 DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1), 90 DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1), 91 DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1), 92 DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1), 93 DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1), 94 DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1), 95 DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1), 96 DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1), 97 DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1), 98 DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1), 99 DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1), 100 DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1), 101 DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1), 102 DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1), 103 DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1), 104 DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1), 105 DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5_DIV2, 5, 1), 106 DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1), 107 DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), 108 109 DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870), 110 111 DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), 112 DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), 113 114 DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 115 116 DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), 117 DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 118 }; 119 120 static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 121 DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER), 122 DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER), 123 DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER), 124 DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER), 125 DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER), 126 DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER), 127 DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), 128 DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), 129 DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), 130 DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), 131 DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0), 132 DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), 133 DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), 134 DEF_MOD("wdt", 907, R8A779F0_CLK_R), 135 DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), 136 DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M), 137 DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC), 138 }; 139 140 static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { 141 MOD_CLK_ID(907), /* WDT */ 142 }; 143 144 /* 145 * CPG Clock Data 146 */ 147 /* 148 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC 149 * 14 13 (MHz) 150 * ------------------------------------------------------------------------ 151 * 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15 152 * 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19 153 * 1 0 Prohibited setting 154 * 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38 155 */ 156 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 157 (((md) & BIT(13)) >> 13)) 158 159 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { 160 /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ 161 { 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, }, 162 { 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, }, 163 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 164 { 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, }, 165 }; 166 167 static int __init r8a779f0_cpg_mssr_init(struct device *dev) 168 { 169 const struct rcar_gen4_cpg_pll_config *cpg_pll_config; 170 u32 cpg_mode; 171 int error; 172 173 error = rcar_rst_read_mode_pins(&cpg_mode); 174 if (error) 175 return error; 176 177 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 178 if (!cpg_pll_config->extal_div) { 179 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); 180 return -EINVAL; 181 } 182 183 return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); 184 } 185 186 const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { 187 /* Core Clocks */ 188 .core_clks = r8a779f0_core_clks, 189 .num_core_clks = ARRAY_SIZE(r8a779f0_core_clks), 190 .last_dt_core_clk = LAST_DT_CORE_CLK, 191 .num_total_core_clks = MOD_CLK_BASE, 192 193 /* Module Clocks */ 194 .mod_clks = r8a779f0_mod_clks, 195 .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks), 196 .num_hw_mod_clks = 28 * 32, 197 198 /* Critical Module Clocks */ 199 .crit_mod_clks = r8a779f0_crit_mod_clks, 200 .num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks), 201 202 /* Callbacks */ 203 .init = r8a779f0_cpg_mssr_init, 204 .cpg_clk_register = rcar_gen4_cpg_clk_register, 205 206 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, 207 }; 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