#
b8c1ddad |
| 23-Apr-2018 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson: meson8b: add support for the NAND clocks
This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the Meson8b clock driver. There are three NAND clocks: a gate which enables or
clk: meson: meson8b: add support for the NAND clocks
This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the Meson8b clock driver. There are three NAND clocks: a gate which enables or disables the NAND clock, a mux and a divider (which divides the mux output). Unfortunately the public S805 datasheet does not document the mux parents. However, the vendor kernel has a few hints for us which allows us to make an educated guess about the clock parents. To do this we need to have a look at set_nand_core_clk() from the vendor's NAND driver (see [0]): - XTAL = (4<<9) | (1<<8) | 0 - 160MHz = (0<<9) | (1<<8) | 3) - 182MHz = (3<<9) | (1<<8) | 1) - 212MHz = (1<<9) | (1<<8) | 3) - 255MHz = (2<<9) | (1<<8) | 1)
While there is a comment for the XTAL parent (which indicates that it should only be used for debugging) we have to do a bit of math for the other parents: target_freq * divider = rate of parent clock Bit 8 above is the enable bit, so we can ignore it here. Bits 11:9 are the mux index and bits 6:0 are the 0-based divider (so we need to add 1). This gives us: - mux 0 (160MHz * 4) = fclk_div4 (actual rate = 637.5MHz, off by 2.5MHz) - mux 1 (212MHz * 4) = fclk_div3 (actual rate = 850MHz, off by 2MHz) - mux 2 (255MHz * 2) = fclk_div5 (matches exactly 510MHz) - mux 3 (182MHz * 2) = fclk_div7 (actual rate = 346.3MHz, off by 0.3MHz)
[0] https://github.com/khadas/linux/blob/9587681285cb/drivers/amlogic/amlnf/dev/amlnf_ctrl.c#L314
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Revision tags: v4.16 |
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#
05f81440 |
| 19-Feb-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate independently. We never had an issue so far because these clocks were provided 'enabled' by the bootloa
clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate independently. We never had an issue so far because these clocks were provided 'enabled' by the bootloader.
Add these gates to enable/disable the clocks when required.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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#
513b67ac |
| 19-Feb-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
clk: meson: add mpll pre-divider
mpll clocks parent can actually be divided by 1 or 2. So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, mode
clk: meson: add mpll pre-divider
mpll clocks parent can actually be divided by 1 or 2. So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, model the tree correctly. If we ever get a platform where the divider is different, we won't get into trouble
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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#
251b6fd3 |
| 12-Feb-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
clk: meson: rework meson8b cpu clock
Instead of migrating meson cpu_clk to clk_regmap, like the other meson clock drivers, we take advantage of the massive rework to get rid of it completely, and so
clk: meson: rework meson8b cpu clock
Instead of migrating meson cpu_clk to clk_regmap, like the other meson clock drivers, we take advantage of the massive rework to get rid of it completely, and solve (the first part) of the related FIXME notice.
As pointed out in the code comments, the cpu_clk should be modeled with dividers and muxes it is made of, instead of one big composite clock.
The cpu_clk was not working correctly to enable dvfs on meson8b. It hangs quite often when changing the cpu clock rate. This new implementation, based on simple elements improves the situation but the platform will still hang from time to time. This is not acceptable so, until we can make the mechanism around the cpu clock stable, the cpu clock subtree has been put in read-only mode, preventing any change of the cpu clock
The notifier and read-write operation will be added back when we have a solution to the problem.
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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#
d610b54f |
| 12-Feb-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate. When the RW operation have been added, enable/disable ops have been mistakenly inserted
clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate. When the RW operation have been added, enable/disable ops have been mistakenly inserted in this driver. These ops are essentially a poor copy/paste of the generic gate ops.
This change removes the gate ops from the mpll driver and inserts a generic gate clock on each mpll divider, simplifying the mpll driver and reducing code duplication.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Revision tags: v4.15, v4.13.16, v4.14, v4.13.5, v4.13 |
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#
18962172 |
| 28-Jul-2017 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson: meson8b: register the built-in reset controller
The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The re
clk: meson: meson8b: register the built-in reset controller
The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The reset controller itself is registered early (through CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot process (to start the secondary CPU cores).
According to the public S805 datasheet there are two more reset bits in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by this patch (as these seem to be unused in Amlogic's vendor Linux kernel sources and their u-boot tree): - bit 15: GEN_DIV_SOFT_RESET - bit 14: SOFT_RESET
All information was taken from the public S805 Datasheet and Amlogic's vendor GPL kernel sources. This patch is based on an earlier version submitted by Carlo Caione.
Suggested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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#
31128822 |
| 31-Jul-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
clk: meson8b: expose every clock in the bindings
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed (none on this particular controller at the
clk: meson8b: expose every clock in the bindings
Expose all clocks which maybe used as DT bindings Only clock ids internal the controller remain un-exposed (none on this particular controller at the moment)
Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Revision tags: v4.12 |
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#
c22f06d3 |
| 11-Jun-2017 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson8b: export the ethernet gate clock
Export the ethernet gate clock to the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <nar
clk: meson8b: export the ethernet gate clock
Export the ethernet gate clock to the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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#
677f6af5 |
| 11-Jun-2017 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson8b: export the USB clocks
Export the USB related clocks (for the USB controller and the USB2 PHYs) so they can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blume
clk: meson8b: export the USB clocks
Export the USB related clocks (for the USB controller and the USB2 PHYs) so they can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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#
06eff6a7 |
| 11-Jun-2017 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson8b: export the gate clock for the HW random number generator
This exports the clock so it can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemai
clk: meson8b: export the gate clock for the HW random number generator
This exports the clock so it can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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#
e2e5f321 |
| 11-Jun-2017 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson8b: export the SDIO clock
Export the SDIO clock so it can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <nar
clk: meson8b: export the SDIO clock
Export the SDIO clock so it can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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#
70ad0d03 |
| 11-Jun-2017 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson8b: export the SAR ADC clocks
Export the clocks for the SAR ADC so they can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: N
clk: meson8b: export the SAR ADC clocks
Export the clocks for the SAR ADC so they can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Revision tags: v4.10.17, v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7, v4.10.6, v4.10.5, v4.10.4, v4.10.3, v4.10.2 |
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#
b778f745 |
| 09-Mar-2017 |
Jerome Brunet <jbrunet@baylibre.com> |
clk: meson8b: add the mplls clocks 0, 1 and 2
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28
clk: meson8b: add the mplls clocks 0, 1 and 2
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-8-jbrunet@baylibre.com
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Revision tags: v4.10.1, v4.10, v4.9, openbmc-4.4-20161121-1, v4.4.33, v4.4.32, v4.4.31, v4.4.30, v4.4.29, v4.4.28, v4.4.27, v4.7.10, openbmc-4.4-20161021-1, v4.7.9, v4.4.26, v4.7.8, v4.4.25, v4.4.24, v4.7.7, v4.8, v4.4.23, v4.7.6, v4.7.5, v4.4.22, v4.4.21, v4.7.4, v4.7.3, v4.4.20 |
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#
e31a1900 |
| 27-Aug-2016 |
Alexander Müller <serveralex@gmail.com> |
meson: clk: Add support for clock gates
This patch adds support for the meson8b clock gates. Most of them are disabled by Amlogic U-Boot, but need to be enabled for ethernet, USB and many other comp
meson: clk: Add support for clock gates
This patch adds support for the meson8b clock gates. Most of them are disabled by Amlogic U-Boot, but need to be enabled for ethernet, USB and many other components.
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-7-git-send-email-serveralex@gmail.com
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#
0f32e64b |
| 27-Aug-2016 |
Alexander Müller <serveralex@gmail.com> |
clk: meson: Copy meson8b CLKID defines to private header file
Only expose future CLKID constants if necessary. This patch removes CLK_NR_CLKS from the DT bindings but leaves all previously defined C
clk: meson: Copy meson8b CLKID defines to private header file
Only expose future CLKID constants if necessary. This patch removes CLK_NR_CLKS from the DT bindings but leaves all previously defined CLKIDs there to keep backward compatibility.
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-5-git-send-email-serveralex@gmail.com
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#
e0818a39 |
| 27-Aug-2016 |
Alexander Müller <serveralex@gmail.com> |
meson: clk: Rename register names according to Amlogic datasheet
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.o
meson: clk: Rename register names according to Amlogic datasheet
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-4-git-send-email-serveralex@gmail.com
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#
d0c175da |
| 27-Aug-2016 |
Alexander Müller <serveralex@gmail.com> |
meson: clk: Move register definitions to meson8b.h
Move the register definitions into a separate header file to reflect the gxbb implementation.
Signed-off-by: Alexander Müller <serveralex@gmail.co
meson: clk: Move register definitions to meson8b.h
Move the register definitions into a separate header file to reflect the gxbb implementation.
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-3-git-send-email-serveralex@gmail.com
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#
b396b3d2 |
| 21-Jul-2020 |
Stephen Boyd <sboyd@kernel.org> |
Merge branch 'clk-amlogic' into clk-next * clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b
Merge branch 'clk-amlogic' into clk-next * clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
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Revision tags: v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51 |
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#
5f1d8970 |
| 03-Jul-2020 |
Alexander A. Klimov <grandmaster@al2klimov.de> |
Replace HTTP links with HTTPS ones: Common CLK framework Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate.
Replace HTTP links with HTTPS ones: Common CLK framework Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Link: https://lore.kernel.org/r/20200703175114.15027-1-grandmaster@al2klimov.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v5.4.50, v5.7.7 |
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#
2568528f |
| 29-Jun-2020 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson: meson8b: add the vclk2_en gate clock HHI_VIID_CLK_CNTL[19] is not part of the public S805 datasheet. However, the GXBB driver defines this bit as a gate called "vclk2" and in
clk: meson: meson8b: add the vclk2_en gate clock HHI_VIID_CLK_CNTL[19] is not part of the public S805 datasheet. However, the GXBB driver defines this bit as a gate called "vclk2" and in the 3.10 kernel GPL code dump the following line can found: WRITE_LCD_CBUS_REG_BITS(HHI_VIID_CLK_CNTL, 0, 19, 1); //disable vclk2_en Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller to complete the VCLK2 clock tree. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200629203904.2989007-3-martin.blumenstingl@googlemail.com
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#
e653b411 |
| 29-Jun-2020 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson: meson8b: add the vclk_en gate clock HHI_VID_CLK_CNTL[19] is documented as CLK_EN0. This description is the same in the public S912 datasheet and the GXBB driver calls this ga
clk: meson: meson8b: add the vclk_en gate clock HHI_VID_CLK_CNTL[19] is documented as CLK_EN0. This description is the same in the public S912 datasheet and the GXBB driver calls this gate "vclk". Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller because it's needed to make the video output work. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200629203904.2989007-2-martin.blumenstingl@googlemail.com
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Revision tags: v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37 |
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#
a29ae860 |
| 01-May-2020 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers. In that case all HHI_GPLL_PLL_CNTL[1-5] regi
clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers. In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when booting Linux the PLL fails to lock. The initialization sequence from u-boot is: - put the PLL into reset - write 0x59C88000 to HHI_GP_PLL_CNTL2 - write 0xCA463823 to HHI_GP_PLL_CNTL3 - write 0x0286A027 to HHI_GP_PLL_CNTL4 - write 0x00003000 to HHI_GP_PLL_CNTL5 - set M, N, OD and the enable bit - take the PLL out of reset - check if it has locked - disable the PLL In Linux we already initialize M, N, OD, the enable and the reset bits. Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the exact meaning is unknown) so the PLL can lock when the vendor u-boot did not initialize these registers yet. Fixes: b882964b376f21 ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200501215717.735393-1-martin.blumenstingl@googlemail.com
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Revision tags: v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29 |
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#
778fb6b7 |
| 30-Mar-2020 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson8b: export the HDMI system clock Export the HDMI system clock (used by the HDMI transmitter) so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <
clk: meson8b: export the HDMI system clock Export the HDMI system clock (used by the HDMI transmitter) so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200330234535.3327513-2-martin.blumenstingl@googlemail.com
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Revision tags: v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4 |
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#
174806aa |
| 20-May-2019 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson: meson8b: add the cts_i958 clock Add the cts_i958 clock to control the clock source of the spdif output block. It is used to select whether the clock source of the spdif outpu
clk: meson: meson8b: add the cts_i958 clock Add the cts_i958 clock to control the clock source of the spdif output block. It is used to select whether the clock source of the spdif output is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer). The setup for this clock is identical to GXBB, so this ports commit 7eaa44f6207fb6 ("clk: meson: gxbb: add cts_i958 clock") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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c39c24c1 |
| 20-May-2019 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
clk: meson: meson8b: add the cts_mclk_i958 clocks Add the SPDIF master clock also referred as cts_mclk_i958. The setup for this clock is identical to GXBB, so this ports commit 3c277c247
clk: meson: meson8b: add the cts_mclk_i958 clocks Add the SPDIF master clock also referred as cts_mclk_i958. The setup for this clock is identical to GXBB, so this ports commit 3c277c247eabeb ("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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