1 /* 2 * Copyright (c) 2015 Endless Mobile, Inc. 3 * Author: Carlo Caione <carlo@endlessm.com> 4 * 5 * Copyright (c) 2016 BayLibre, Inc. 6 * Michael Turquette <mturquette@baylibre.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef __MESON8B_H 22 #define __MESON8B_H 23 24 /* 25 * Clock controller register offsets 26 * 27 * Register offsets from the HardKernel[0] data sheet are listed in comment 28 * blocks below. Those offsets must be multiplied by 4 before adding them to 29 * the base address to get the right value 30 * 31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 32 */ 33 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 34 #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 35 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 36 #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 37 #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 38 #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 39 #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 40 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 41 #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 42 #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 43 44 /* 45 * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 46 * confirm these are the same for the S805. 47 */ 48 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 49 #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 50 #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 51 #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 52 #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 53 #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 54 #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ 55 #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ 56 #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ 57 #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 58 59 /* 60 * CLKID index values 61 * 62 * These indices are entirely contrived and do not map onto the hardware. 63 * Migrate them out of this header and into the DT header file when they need 64 * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h 65 */ 66 67 /* CLKID_UNUSED */ 68 /* CLKID_XTAL */ 69 /* CLKID_PLL_FIXED */ 70 /* CLKID_PLL_VID */ 71 /* CLKID_PLL_SYS */ 72 /* CLKID_FCLK_DIV2 */ 73 /* CLKID_FCLK_DIV3 */ 74 /* CLKID_FCLK_DIV4 */ 75 /* CLKID_FCLK_DIV5 */ 76 /* CLKID_FCLK_DIV7 */ 77 /* CLKID_CLK81 */ 78 /* CLKID_MALI */ 79 /* CLKID_CPUCLK */ 80 /* CLKID_ZERO */ 81 /* CLKID_MPEG_SEL */ 82 /* CLKID_MPEG_DIV */ 83 #define CLKID_DDR 16 84 #define CLKID_DOS 17 85 #define CLKID_ISA 18 86 #define CLKID_PL301 19 87 #define CLKID_PERIPHS 20 88 #define CLKID_SPICC 21 89 #define CLKID_I2C 22 90 /* #define CLKID_SAR_ADC */ 91 #define CLKID_SMART_CARD 24 92 #define CLKID_RNG0 25 93 #define CLKID_UART0 26 94 #define CLKID_SDHC 27 95 #define CLKID_STREAM 28 96 #define CLKID_ASYNC_FIFO 29 97 /* #define CLKID_SDIO */ 98 #define CLKID_ABUF 31 99 #define CLKID_HIU_IFACE 32 100 #define CLKID_ASSIST_MISC 33 101 #define CLKID_SPI 34 102 #define CLKID_I2S_SPDIF 35 103 #define CLKID_ETH 36 104 #define CLKID_DEMUX 37 105 #define CLKID_AIU_GLUE 38 106 #define CLKID_IEC958 39 107 #define CLKID_I2S_OUT 40 108 #define CLKID_AMCLK 41 109 #define CLKID_AIFIFO2 42 110 #define CLKID_MIXER 43 111 #define CLKID_MIXER_IFACE 44 112 #define CLKID_ADC 45 113 #define CLKID_BLKMV 46 114 #define CLKID_AIU 47 115 #define CLKID_UART1 48 116 #define CLKID_G2D 49 117 #define CLKID_USB0 50 118 #define CLKID_USB1 51 119 #define CLKID_RESET 52 120 #define CLKID_NAND 53 121 #define CLKID_DOS_PARSER 54 122 #define CLKID_USB 55 123 #define CLKID_VDIN1 56 124 #define CLKID_AHB_ARB0 57 125 #define CLKID_EFUSE 58 126 #define CLKID_BOOT_ROM 59 127 #define CLKID_AHB_DATA_BUS 60 128 #define CLKID_AHB_CTRL_BUS 61 129 #define CLKID_HDMI_INTR_SYNC 62 130 #define CLKID_HDMI_PCLK 63 131 #define CLKID_USB1_DDR_BRIDGE 64 132 #define CLKID_USB0_DDR_BRIDGE 65 133 #define CLKID_MMC_PCLK 66 134 #define CLKID_DVIN 67 135 #define CLKID_UART2 68 136 /* #define CLKID_SANA */ 137 #define CLKID_VPU_INTR 70 138 #define CLKID_SEC_AHB_AHB3_BRIDGE 71 139 #define CLKID_CLK81_A9 72 140 #define CLKID_VCLK2_VENCI0 73 141 #define CLKID_VCLK2_VENCI1 74 142 #define CLKID_VCLK2_VENCP0 75 143 #define CLKID_VCLK2_VENCP1 76 144 #define CLKID_GCLK_VENCI_INT 77 145 #define CLKID_GCLK_VENCP_INT 78 146 #define CLKID_DAC_CLK 79 147 #define CLKID_AOCLK_GATE 80 148 #define CLKID_IEC958_GATE 81 149 #define CLKID_ENC480P 82 150 #define CLKID_RNG1 83 151 #define CLKID_GCLK_VENCL_INT 84 152 #define CLKID_VCLK2_VENCLMCC 85 153 #define CLKID_VCLK2_VENCL 86 154 #define CLKID_VCLK2_OTHER 87 155 #define CLKID_EDP 88 156 #define CLKID_AO_MEDIA_CPU 89 157 #define CLKID_AO_AHB_SRAM 90 158 #define CLKID_AO_AHB_BUS 91 159 #define CLKID_AO_IFACE 92 160 #define CLKID_MPLL0 93 161 #define CLKID_MPLL1 94 162 #define CLKID_MPLL2 95 163 164 #define CLK_NR_CLKS 96 165 166 /* include the CLKIDs that have been made part of the stable DT binding */ 167 #include <dt-bindings/clock/meson8b-clkc.h> 168 169 #endif /* __MESON8B_H */ 170