1 /* 2 * Copyright (c) 2015 Endless Mobile, Inc. 3 * Author: Carlo Caione <carlo@endlessm.com> 4 * 5 * Copyright (c) 2016 BayLibre, Inc. 6 * Michael Turquette <mturquette@baylibre.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef __MESON8B_H 22 #define __MESON8B_H 23 24 /* 25 * Clock controller register offsets 26 * 27 * Register offsets from the HardKernel[0] data sheet are listed in comment 28 * blocks below. Those offsets must be multiplied by 4 before adding them to 29 * the base address to get the right value 30 * 31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 32 */ 33 #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 34 #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 35 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 36 #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 37 #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 38 39 /* 40 * CLKID index values 41 * 42 * These indices are entirely contrived and do not map onto the hardware. 43 * Migrate them out of this header and into the DT header file when they need 44 * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h 45 */ 46 47 /* CLKID_UNUSED */ 48 /* CLKID_XTAL */ 49 /* CLKID_PLL_FIXED */ 50 /* CLKID_PLL_VID */ 51 /* CLKID_PLL_SYS */ 52 /* CLKID_FCLK_DIV2 */ 53 /* CLKID_FCLK_DIV3 */ 54 /* CLKID_FCLK_DIV4 */ 55 /* CLKID_FCLK_DIV5 */ 56 /* CLKID_FCLK_DIV7 */ 57 /* CLKID_CLK81 */ 58 /* CLKID_MALI */ 59 /* CLKID_CPUCLK */ 60 /* CLKID_ZERO */ 61 /* CLKID_MPEG_SEL */ 62 /* CLKID_MPEG_DIV */ 63 #define CLKID_DDR 16 64 #define CLKID_DOS 17 65 #define CLKID_ISA 18 66 #define CLKID_PL301 19 67 #define CLKID_PERIPHS 20 68 #define CLKID_SPICC 21 69 #define CLKID_I2C 22 70 #define CLKID_SAR_ADC 23 71 #define CLKID_SMART_CARD 24 72 #define CLKID_RNG0 25 73 #define CLKID_UART0 26 74 #define CLKID_SDHC 27 75 #define CLKID_STREAM 28 76 #define CLKID_ASYNC_FIFO 29 77 #define CLKID_SDIO 30 78 #define CLKID_ABUF 31 79 #define CLKID_HIU_IFACE 32 80 #define CLKID_ASSIST_MISC 33 81 #define CLKID_SPI 34 82 #define CLKID_I2S_SPDIF 35 83 #define CLKID_ETH 36 84 #define CLKID_DEMUX 37 85 #define CLKID_AIU_GLUE 38 86 #define CLKID_IEC958 39 87 #define CLKID_I2S_OUT 40 88 #define CLKID_AMCLK 41 89 #define CLKID_AIFIFO2 42 90 #define CLKID_MIXER 43 91 #define CLKID_MIXER_IFACE 44 92 #define CLKID_ADC 45 93 #define CLKID_BLKMV 46 94 #define CLKID_AIU 47 95 #define CLKID_UART1 48 96 #define CLKID_G2D 49 97 #define CLKID_USB0 50 98 #define CLKID_USB1 51 99 #define CLKID_RESET 52 100 #define CLKID_NAND 53 101 #define CLKID_DOS_PARSER 54 102 #define CLKID_USB 55 103 #define CLKID_VDIN1 56 104 #define CLKID_AHB_ARB0 57 105 #define CLKID_EFUSE 58 106 #define CLKID_BOOT_ROM 59 107 #define CLKID_AHB_DATA_BUS 60 108 #define CLKID_AHB_CTRL_BUS 61 109 #define CLKID_HDMI_INTR_SYNC 62 110 #define CLKID_HDMI_PCLK 63 111 #define CLKID_USB1_DDR_BRIDGE 64 112 #define CLKID_USB0_DDR_BRIDGE 65 113 #define CLKID_MMC_PCLK 66 114 #define CLKID_DVIN 67 115 #define CLKID_UART2 68 116 #define CLKID_SANA 69 117 #define CLKID_VPU_INTR 70 118 #define CLKID_SEC_AHB_AHB3_BRIDGE 71 119 #define CLKID_CLK81_A9 72 120 #define CLKID_VCLK2_VENCI0 73 121 #define CLKID_VCLK2_VENCI1 74 122 #define CLKID_VCLK2_VENCP0 75 123 #define CLKID_VCLK2_VENCP1 76 124 #define CLKID_GCLK_VENCI_INT 77 125 #define CLKID_GCLK_VENCP_INT 78 126 #define CLKID_DAC_CLK 79 127 #define CLKID_AOCLK_GATE 80 128 #define CLKID_IEC958_GATE 81 129 #define CLKID_ENC480P 82 130 #define CLKID_RNG1 83 131 #define CLKID_GCLK_VENCL_INT 84 132 #define CLKID_VCLK2_VENCLMCC 85 133 #define CLKID_VCLK2_VENCL 86 134 #define CLKID_VCLK2_OTHER 87 135 #define CLKID_EDP 88 136 #define CLKID_AO_MEDIA_CPU 89 137 #define CLKID_AO_AHB_SRAM 90 138 #define CLKID_AO_AHB_BUS 91 139 #define CLKID_AO_IFACE 92 140 141 #define CLK_NR_CLKS 93 142 143 /* include the CLKIDs that have been made part of the stable DT binding */ 144 #include <dt-bindings/clock/meson8b-clkc.h> 145 146 #endif /* __MESON8B_H */ 147