1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 22 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 23 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 24 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 #interrupt-cells = <3>; 29 interrupt-controller; 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x00 0x00 0x00100000 0x20000>; 51 52 phy_gmii_sel: phy@4044 { 53 compatible = "ti,am654-phy-gmii-sel"; 54 reg = <0x4044 0x8>; 55 #phy-cells = <1>; 56 }; 57 58 epwm_tbclk: clock-controller@4130 { 59 compatible = "ti,am62-epwm-tbclk", "syscon"; 60 reg = <0x4130 0x4>; 61 #clock-cells = <1>; 62 }; 63 }; 64 65 dmss: bus@48000000 { 66 compatible = "simple-bus"; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 dma-ranges; 70 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 71 72 ti,sci-dev-id = <25>; 73 74 secure_proxy_main: mailbox@4d000000 { 75 compatible = "ti,am654-secure-proxy"; 76 reg = <0x00 0x4d000000 0x00 0x80000>, 77 <0x00 0x4a600000 0x00 0x80000>, 78 <0x00 0x4a400000 0x00 0x80000>; 79 reg-names = "target_data", "rt", "scfg"; 80 #mbox-cells = <1>; 81 interrupt-names = "rx_012"; 82 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 83 }; 84 85 inta_main_dmss: interrupt-controller@48000000 { 86 compatible = "ti,sci-inta"; 87 reg = <0x00 0x48000000 0x00 0x100000>; 88 #interrupt-cells = <0>; 89 interrupt-controller; 90 interrupt-parent = <&gic500>; 91 msi-controller; 92 ti,sci = <&dmsc>; 93 ti,sci-dev-id = <28>; 94 ti,interrupt-ranges = <6 70 34>; 95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 96 }; 97 98 main_bcdma: dma-controller@485c0100 { 99 compatible = "ti,am64-dmss-bcdma"; 100 reg = <0x00 0x485c0100 0x00 0x100>, 101 <0x00 0x4c000000 0x00 0x20000>, 102 <0x00 0x4a820000 0x00 0x20000>, 103 <0x00 0x4aa40000 0x00 0x20000>, 104 <0x00 0x4bc00000 0x00 0x100000>; 105 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 106 msi-parent = <&inta_main_dmss>; 107 #dma-cells = <3>; 108 ti,sci = <&dmsc>; 109 ti,sci-dev-id = <26>; 110 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 111 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 112 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 113 }; 114 115 main_pktdma: dma-controller@485c0000 { 116 compatible = "ti,am64-dmss-pktdma"; 117 reg = <0x00 0x485c0000 0x00 0x100>, 118 <0x00 0x4a800000 0x00 0x20000>, 119 <0x00 0x4aa00000 0x00 0x40000>, 120 <0x00 0x4b800000 0x00 0x400000>; 121 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 122 msi-parent = <&inta_main_dmss>; 123 #dma-cells = <2>; 124 ti,sci = <&dmsc>; 125 ti,sci-dev-id = <30>; 126 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 127 <0x24>, /* CPSW_TX_CHAN */ 128 <0x25>, /* SAUL_TX_0_CHAN */ 129 <0x26>; /* SAUL_TX_1_CHAN */ 130 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 131 <0x11>, /* RING_CPSW_TX_CHAN */ 132 <0x12>, /* RING_SAUL_TX_0_CHAN */ 133 <0x13>; /* RING_SAUL_TX_1_CHAN */ 134 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 135 <0x2b>, /* CPSW_RX_CHAN */ 136 <0x2d>, /* SAUL_RX_0_CHAN */ 137 <0x2f>, /* SAUL_RX_1_CHAN */ 138 <0x31>, /* SAUL_RX_2_CHAN */ 139 <0x33>; /* SAUL_RX_3_CHAN */ 140 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 141 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 142 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 143 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 144 }; 145 }; 146 147 dmsc: system-controller@44043000 { 148 compatible = "ti,k2g-sci"; 149 reg = <0x00 0x44043000 0x00 0xfe0>; 150 reg-names = "debug_messages"; 151 ti,host-id = <12>; 152 mbox-names = "rx", "tx"; 153 mboxes= <&secure_proxy_main 12>, 154 <&secure_proxy_main 13>; 155 156 k3_pds: power-controller { 157 compatible = "ti,sci-pm-domain"; 158 #power-domain-cells = <2>; 159 }; 160 161 k3_clks: clock-controller { 162 compatible = "ti,k2g-sci-clk"; 163 #clock-cells = <2>; 164 }; 165 166 k3_reset: reset-controller { 167 compatible = "ti,sci-reset"; 168 #reset-cells = <2>; 169 }; 170 }; 171 172 main_pmx0: pinctrl@f4000 { 173 compatible = "pinctrl-single"; 174 reg = <0x00 0xf4000 0x00 0x2ac>; 175 #pinctrl-cells = <1>; 176 pinctrl-single,register-width = <32>; 177 pinctrl-single,function-mask = <0xffffffff>; 178 }; 179 180 main_timer0: timer@2400000 { 181 compatible = "ti,am654-timer"; 182 reg = <0x00 0x2400000 0x00 0x400>; 183 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&k3_clks 36 2>; 185 clock-names = "fck"; 186 assigned-clocks = <&k3_clks 36 2>; 187 assigned-clock-parents = <&k3_clks 36 3>; 188 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 189 ti,timer-pwm; 190 }; 191 192 main_timer1: timer@2410000 { 193 compatible = "ti,am654-timer"; 194 reg = <0x00 0x2410000 0x00 0x400>; 195 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&k3_clks 37 2>; 197 clock-names = "fck"; 198 assigned-clocks = <&k3_clks 37 2>; 199 assigned-clock-parents = <&k3_clks 37 3>; 200 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 201 ti,timer-pwm; 202 }; 203 204 main_timer2: timer@2420000 { 205 compatible = "ti,am654-timer"; 206 reg = <0x00 0x2420000 0x00 0x400>; 207 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&k3_clks 38 2>; 209 clock-names = "fck"; 210 assigned-clocks = <&k3_clks 38 2>; 211 assigned-clock-parents = <&k3_clks 38 3>; 212 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 213 ti,timer-pwm; 214 }; 215 216 main_timer3: timer@2430000 { 217 compatible = "ti,am654-timer"; 218 reg = <0x00 0x2430000 0x00 0x400>; 219 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&k3_clks 39 2>; 221 clock-names = "fck"; 222 assigned-clocks = <&k3_clks 39 2>; 223 assigned-clock-parents = <&k3_clks 39 3>; 224 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 225 ti,timer-pwm; 226 }; 227 228 main_timer4: timer@2440000 { 229 compatible = "ti,am654-timer"; 230 reg = <0x00 0x2440000 0x00 0x400>; 231 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&k3_clks 40 2>; 233 clock-names = "fck"; 234 assigned-clocks = <&k3_clks 40 2>; 235 assigned-clock-parents = <&k3_clks 40 3>; 236 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 237 ti,timer-pwm; 238 }; 239 240 main_timer5: timer@2450000 { 241 compatible = "ti,am654-timer"; 242 reg = <0x00 0x2450000 0x00 0x400>; 243 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&k3_clks 41 2>; 245 clock-names = "fck"; 246 assigned-clocks = <&k3_clks 41 2>; 247 assigned-clock-parents = <&k3_clks 41 3>; 248 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 249 ti,timer-pwm; 250 }; 251 252 main_timer6: timer@2460000 { 253 compatible = "ti,am654-timer"; 254 reg = <0x00 0x2460000 0x00 0x400>; 255 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&k3_clks 42 2>; 257 clock-names = "fck"; 258 assigned-clocks = <&k3_clks 42 2>; 259 assigned-clock-parents = <&k3_clks 42 3>; 260 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 261 ti,timer-pwm; 262 }; 263 264 main_timer7: timer@2470000 { 265 compatible = "ti,am654-timer"; 266 reg = <0x00 0x2470000 0x00 0x400>; 267 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&k3_clks 43 2>; 269 clock-names = "fck"; 270 assigned-clocks = <&k3_clks 43 2>; 271 assigned-clock-parents = <&k3_clks 43 3>; 272 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 273 ti,timer-pwm; 274 }; 275 276 main_uart0: serial@2800000 { 277 compatible = "ti,am64-uart", "ti,am654-uart"; 278 reg = <0x00 0x02800000 0x00 0x100>; 279 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 280 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 281 clocks = <&k3_clks 146 0>; 282 clock-names = "fclk"; 283 status = "disabled"; 284 }; 285 286 main_uart1: serial@2810000 { 287 compatible = "ti,am64-uart", "ti,am654-uart"; 288 reg = <0x00 0x02810000 0x00 0x100>; 289 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 290 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 291 clocks = <&k3_clks 152 0>; 292 clock-names = "fclk"; 293 status = "disabled"; 294 }; 295 296 main_uart2: serial@2820000 { 297 compatible = "ti,am64-uart", "ti,am654-uart"; 298 reg = <0x00 0x02820000 0x00 0x100>; 299 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 300 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 301 clocks = <&k3_clks 153 0>; 302 clock-names = "fclk"; 303 status = "disabled"; 304 }; 305 306 main_uart3: serial@2830000 { 307 compatible = "ti,am64-uart", "ti,am654-uart"; 308 reg = <0x00 0x02830000 0x00 0x100>; 309 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 310 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 311 clocks = <&k3_clks 154 0>; 312 clock-names = "fclk"; 313 status = "disabled"; 314 }; 315 316 main_uart4: serial@2840000 { 317 compatible = "ti,am64-uart", "ti,am654-uart"; 318 reg = <0x00 0x02840000 0x00 0x100>; 319 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 320 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 321 clocks = <&k3_clks 155 0>; 322 clock-names = "fclk"; 323 status = "disabled"; 324 }; 325 326 main_uart5: serial@2850000 { 327 compatible = "ti,am64-uart", "ti,am654-uart"; 328 reg = <0x00 0x02850000 0x00 0x100>; 329 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 330 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 331 clocks = <&k3_clks 156 0>; 332 clock-names = "fclk"; 333 status = "disabled"; 334 }; 335 336 main_uart6: serial@2860000 { 337 compatible = "ti,am64-uart", "ti,am654-uart"; 338 reg = <0x00 0x02860000 0x00 0x100>; 339 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 340 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 341 clocks = <&k3_clks 158 0>; 342 clock-names = "fclk"; 343 status = "disabled"; 344 }; 345 346 main_i2c0: i2c@20000000 { 347 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 348 reg = <0x00 0x20000000 0x00 0x100>; 349 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 353 clocks = <&k3_clks 102 2>; 354 clock-names = "fck"; 355 status = "disabled"; 356 }; 357 358 main_i2c1: i2c@20010000 { 359 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 360 reg = <0x00 0x20010000 0x00 0x100>; 361 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 365 clocks = <&k3_clks 103 2>; 366 clock-names = "fck"; 367 status = "disabled"; 368 }; 369 370 main_i2c2: i2c@20020000 { 371 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 372 reg = <0x00 0x20020000 0x00 0x100>; 373 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 377 clocks = <&k3_clks 104 2>; 378 clock-names = "fck"; 379 status = "disabled"; 380 }; 381 382 main_i2c3: i2c@20030000 { 383 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 384 reg = <0x00 0x20030000 0x00 0x100>; 385 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 389 clocks = <&k3_clks 105 2>; 390 clock-names = "fck"; 391 status = "disabled"; 392 }; 393 394 main_spi0: spi@20100000 { 395 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 396 reg = <0x00 0x20100000 0x00 0x400>; 397 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 141 0>; 402 status = "disabled"; 403 }; 404 405 main_spi1: spi@20110000 { 406 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 407 reg = <0x00 0x20110000 0x00 0x400>; 408 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 412 clocks = <&k3_clks 142 0>; 413 status = "disabled"; 414 }; 415 416 main_spi2: spi@20120000 { 417 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 418 reg = <0x00 0x20120000 0x00 0x400>; 419 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 143 0>; 424 status = "disabled"; 425 }; 426 427 main_gpio_intr: interrupt-controller@a00000 { 428 compatible = "ti,sci-intr"; 429 reg = <0x00 0x00a00000 0x00 0x800>; 430 ti,intr-trigger-type = <1>; 431 interrupt-controller; 432 interrupt-parent = <&gic500>; 433 #interrupt-cells = <1>; 434 ti,sci = <&dmsc>; 435 ti,sci-dev-id = <3>; 436 ti,interrupt-ranges = <0 32 16>; 437 status = "disabled"; 438 }; 439 440 main_gpio0: gpio@600000 { 441 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 442 reg = <0x00 0x00600000 0x0 0x100>; 443 gpio-controller; 444 #gpio-cells = <2>; 445 interrupt-parent = <&main_gpio_intr>; 446 interrupts = <190>, <191>, <192>, 447 <193>, <194>, <195>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 ti,ngpio = <87>; 451 ti,davinci-gpio-unbanked = <0>; 452 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 453 clocks = <&k3_clks 77 0>; 454 clock-names = "gpio"; 455 status = "disabled"; 456 }; 457 458 main_gpio1: gpio@601000 { 459 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 460 reg = <0x00 0x00601000 0x0 0x100>; 461 gpio-controller; 462 #gpio-cells = <2>; 463 interrupt-parent = <&main_gpio_intr>; 464 interrupts = <180>, <181>, <182>, 465 <183>, <184>, <185>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 ti,ngpio = <88>; 469 ti,davinci-gpio-unbanked = <0>; 470 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 471 clocks = <&k3_clks 78 0>; 472 clock-names = "gpio"; 473 status = "disabled"; 474 }; 475 476 sdhci1: mmc@fa00000 { 477 compatible = "ti,am62-sdhci"; 478 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 479 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 480 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 481 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 482 clock-names = "clk_ahb", "clk_xin"; 483 ti,trm-icp = <0x2>; 484 ti,otap-del-sel-legacy = <0x0>; 485 ti,otap-del-sel-sd-hs = <0x0>; 486 ti,otap-del-sel-sdr12 = <0xf>; 487 ti,otap-del-sel-sdr25 = <0xf>; 488 ti,otap-del-sel-sdr50 = <0xc>; 489 ti,otap-del-sel-sdr104 = <0x6>; 490 ti,otap-del-sel-ddr50 = <0x9>; 491 ti,itap-del-sel-legacy = <0x0>; 492 ti,itap-del-sel-sd-hs = <0x0>; 493 ti,itap-del-sel-sdr12 = <0x0>; 494 ti,itap-del-sel-sdr25 = <0x0>; 495 ti,clkbuf-sel = <0x7>; 496 bus-width = <4>; 497 no-1-8-v; 498 status = "disabled"; 499 }; 500 501 usbss0: dwc3-usb@f900000 { 502 compatible = "ti,am62-usb"; 503 reg = <0x00 0x0f900000 0x00 0x800>; 504 clocks = <&k3_clks 161 3>; 505 clock-names = "ref"; 506 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; 507 #address-cells = <2>; 508 #size-cells = <2>; 509 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 510 ranges; 511 status = "disabled"; 512 513 usb0: usb@31000000 { 514 compatible = "snps,dwc3"; 515 reg =<0x00 0x31000000 0x00 0x50000>; 516 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 517 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 518 interrupt-names = "host", "peripheral"; 519 maximum-speed = "high-speed"; 520 dr_mode = "otg"; 521 }; 522 }; 523 524 usbss1: dwc3-usb@f910000 { 525 compatible = "ti,am62-usb"; 526 reg = <0x00 0x0f910000 0x00 0x800>; 527 clocks = <&k3_clks 162 3>; 528 clock-names = "ref"; 529 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; 530 #address-cells = <2>; 531 #size-cells = <2>; 532 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 533 ranges; 534 status = "disabled"; 535 536 usb1: usb@31100000 { 537 compatible = "snps,dwc3"; 538 reg =<0x00 0x31100000 0x00 0x50000>; 539 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 540 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 541 interrupt-names = "host", "peripheral"; 542 maximum-speed = "high-speed"; 543 dr_mode = "otg"; 544 }; 545 }; 546 547 fss: bus@fc00000 { 548 compatible = "simple-bus"; 549 reg = <0x00 0x0fc00000 0x00 0x70000>; 550 #address-cells = <2>; 551 #size-cells = <2>; 552 ranges; 553 status = "disabled"; 554 555 ospi0: spi@fc40000 { 556 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 557 reg = <0x00 0x0fc40000 0x00 0x100>, 558 <0x05 0x00000000 0x01 0x00000000>; 559 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 560 cdns,fifo-depth = <256>; 561 cdns,fifo-width = <4>; 562 cdns,trigger-address = <0x0>; 563 clocks = <&k3_clks 75 7>; 564 assigned-clocks = <&k3_clks 75 7>; 565 assigned-clock-parents = <&k3_clks 75 8>; 566 assigned-clock-rates = <166666666>; 567 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 }; 571 }; 572 573 cpsw3g: ethernet@8000000 { 574 compatible = "ti,am642-cpsw-nuss"; 575 #address-cells = <2>; 576 #size-cells = <2>; 577 reg = <0x0 0x8000000 0x0 0x200000>; 578 reg-names = "cpsw_nuss"; 579 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 580 clocks = <&k3_clks 13 0>; 581 assigned-clocks = <&k3_clks 13 3>; 582 assigned-clock-parents = <&k3_clks 13 11>; 583 clock-names = "fck"; 584 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 585 status = "disabled"; 586 587 dmas = <&main_pktdma 0xc600 15>, 588 <&main_pktdma 0xc601 15>, 589 <&main_pktdma 0xc602 15>, 590 <&main_pktdma 0xc603 15>, 591 <&main_pktdma 0xc604 15>, 592 <&main_pktdma 0xc605 15>, 593 <&main_pktdma 0xc606 15>, 594 <&main_pktdma 0xc607 15>, 595 <&main_pktdma 0x4600 15>; 596 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 597 "tx7", "rx"; 598 599 ethernet-ports { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 603 cpsw_port1: port@1 { 604 reg = <1>; 605 ti,mac-only; 606 label = "port1"; 607 phys = <&phy_gmii_sel 1>; 608 mac-address = [00 00 00 00 00 00]; 609 ti,syscon-efuse = <&wkup_conf 0x200>; 610 }; 611 612 cpsw_port2: port@2 { 613 reg = <2>; 614 ti,mac-only; 615 label = "port2"; 616 phys = <&phy_gmii_sel 2>; 617 mac-address = [00 00 00 00 00 00]; 618 }; 619 }; 620 621 cpsw3g_mdio: mdio@f00 { 622 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 623 reg = <0x0 0xf00 0x0 0x100>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 clocks = <&k3_clks 13 0>; 627 clock-names = "fck"; 628 bus_freq = <1000000>; 629 }; 630 631 cpts@3d000 { 632 compatible = "ti,j721e-cpts"; 633 reg = <0x0 0x3d000 0x0 0x400>; 634 clocks = <&k3_clks 13 3>; 635 clock-names = "cpts"; 636 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 637 interrupt-names = "cpts"; 638 ti,cpts-ext-ts-inputs = <4>; 639 ti,cpts-periodic-outputs = <2>; 640 }; 641 }; 642 643 hwspinlock: spinlock@2a000000 { 644 compatible = "ti,am64-hwspinlock"; 645 reg = <0x00 0x2a000000 0x00 0x1000>; 646 #hwlock-cells = <1>; 647 }; 648 649 mailbox0_cluster0: mailbox@29000000 { 650 compatible = "ti,am64-mailbox"; 651 reg = <0x00 0x29000000 0x00 0x200>; 652 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 653 #mbox-cells = <1>; 654 ti,mbox-num-users = <4>; 655 ti,mbox-num-fifos = <16>; 656 }; 657 658 mailbox0_cluster1: mailbox@29010000 { 659 compatible = "ti,am64-mailbox"; 660 reg = <0x00 0x29010000 0x00 0x200>; 661 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 662 #mbox-cells = <1>; 663 ti,mbox-num-users = <4>; 664 ti,mbox-num-fifos = <16>; 665 }; 666 667 mailbox0_cluster2: mailbox@29020000 { 668 compatible = "ti,am64-mailbox"; 669 reg = <0x00 0x29020000 0x00 0x200>; 670 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 671 #mbox-cells = <1>; 672 ti,mbox-num-users = <4>; 673 ti,mbox-num-fifos = <16>; 674 }; 675 676 mailbox0_cluster3: mailbox@29030000 { 677 compatible = "ti,am64-mailbox"; 678 reg = <0x00 0x29030000 0x00 0x200>; 679 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 680 #mbox-cells = <1>; 681 ti,mbox-num-users = <4>; 682 ti,mbox-num-fifos = <16>; 683 }; 684 685 main_mcan0: can@20701000 { 686 compatible = "bosch,m_can"; 687 reg = <0x00 0x20701000 0x00 0x200>, 688 <0x00 0x20708000 0x00 0x8000>; 689 reg-names = "m_can", "message_ram"; 690 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 691 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 692 clock-names = "hclk", "cclk"; 693 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 695 interrupt-names = "int0", "int1"; 696 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 697 status = "disabled"; 698 }; 699 700 main_rti0: watchdog@e000000 { 701 compatible = "ti,j7-rti-wdt"; 702 reg = <0x00 0x0e000000 0x00 0x100>; 703 clocks = <&k3_clks 125 0>; 704 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 705 assigned-clocks = <&k3_clks 125 0>; 706 assigned-clock-parents = <&k3_clks 125 2>; 707 }; 708 709 main_rti1: watchdog@e010000 { 710 compatible = "ti,j7-rti-wdt"; 711 reg = <0x00 0x0e010000 0x00 0x100>; 712 clocks = <&k3_clks 126 0>; 713 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 714 assigned-clocks = <&k3_clks 126 0>; 715 assigned-clock-parents = <&k3_clks 126 2>; 716 }; 717 718 main_rti2: watchdog@e020000 { 719 compatible = "ti,j7-rti-wdt"; 720 reg = <0x00 0x0e020000 0x00 0x100>; 721 clocks = <&k3_clks 127 0>; 722 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 723 assigned-clocks = <&k3_clks 127 0>; 724 assigned-clock-parents = <&k3_clks 127 2>; 725 }; 726 727 main_rti3: watchdog@e030000 { 728 compatible = "ti,j7-rti-wdt"; 729 reg = <0x00 0x0e030000 0x00 0x100>; 730 clocks = <&k3_clks 128 0>; 731 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 732 assigned-clocks = <&k3_clks 128 0>; 733 assigned-clock-parents = <&k3_clks 128 2>; 734 }; 735 736 main_rti4: watchdog@e040000 { 737 compatible = "ti,j7-rti-wdt"; 738 reg = <0x00 0x0e040000 0x00 0x100>; 739 clocks = <&k3_clks 205 0>; 740 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; 741 assigned-clocks = <&k3_clks 205 0>; 742 assigned-clock-parents = <&k3_clks 205 2>; 743 }; 744 745 epwm0: pwm@23000000 { 746 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 747 #pwm-cells = <3>; 748 reg = <0x00 0x23000000 0x00 0x100>; 749 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 750 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 751 clock-names = "tbclk", "fck"; 752 status = "disabled"; 753 }; 754 755 epwm1: pwm@23010000 { 756 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 757 #pwm-cells = <3>; 758 reg = <0x00 0x23010000 0x00 0x100>; 759 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 760 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 761 clock-names = "tbclk", "fck"; 762 status = "disabled"; 763 }; 764 765 epwm2: pwm@23020000 { 766 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 767 #pwm-cells = <3>; 768 reg = <0x00 0x23020000 0x00 0x100>; 769 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 770 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 771 clock-names = "tbclk", "fck"; 772 status = "disabled"; 773 }; 774 775 ecap0: pwm@23100000 { 776 compatible = "ti,am3352-ecap"; 777 #pwm-cells = <3>; 778 reg = <0x00 0x23100000 0x00 0x100>; 779 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 780 clocks = <&k3_clks 51 0>; 781 clock-names = "fck"; 782 status = "disabled"; 783 }; 784 785 ecap1: pwm@23110000 { 786 compatible = "ti,am3352-ecap"; 787 #pwm-cells = <3>; 788 reg = <0x00 0x23110000 0x00 0x100>; 789 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 790 clocks = <&k3_clks 52 0>; 791 clock-names = "fck"; 792 status = "disabled"; 793 }; 794 795 ecap2: pwm@23120000 { 796 compatible = "ti,am3352-ecap"; 797 #pwm-cells = <3>; 798 reg = <0x00 0x23120000 0x00 0x100>; 799 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 800 clocks = <&k3_clks 53 0>; 801 clock-names = "fck"; 802 status = "disabled"; 803 }; 804}; 805