arm64: dts: uniphier: add SD-ctrl node for LD11 SoC

The LD11 SoC is equipped with SD-ctrl (0x59810000) as well as
MIO-ctrl (0x5b3e0000). The SD-ctrl block on this SoC has just
one r

arm64: dts: uniphier: add SD-ctrl node for LD11 SoC

The LD11 SoC is equipped with SD-ctrl (0x59810000) as well as
MIO-ctrl (0x5b3e0000). The SD-ctrl block on this SoC has just
one register for controlling RST_n pin of the eMMC device.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: make compatible of syscon nodes SoC-specific

These hardware blocks are SoC-specific, so their compatible strings
should be SoC-specific as well. This change has no

arm64: dts: uniphier: make compatible of syscon nodes SoC-specific

These hardware blocks are SoC-specific, so their compatible strings
should be SoC-specific as well. This change has no impact on the
actual behavior since it is controlled by the generic "simple-mfd",
"syscon" compatible strings.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC

Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.

Note:
clock-latency-n

arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC

Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.

Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

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arm64: dts: uniphier: increase register region size of sysctrl node

The System Control node has 0x10000 byte of registers. The current
reg size must be expanded to use the cpufreq drive

arm64: dts: uniphier: increase register region size of sysctrl node

The System Control node has 0x10000 byte of registers. The current
reg size must be expanded to use the cpufreq driver because the
registers controlling CPU frequency are located at offset 0x8000.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: switch over to PSCI enable method

At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that momen

arm64: dts: uniphier: switch over to PSCI enable method

At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI.
Now I finished porting the ATF BL31 for the UniPhier platform, so it
is ready to migrate to PSCI enable method.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add LD11 SoC/Board support

This is a low-cost 64bit SoC from Socionext.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>