1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00080000; 47 48/ { 49 compatible = "socionext,uniphier-ld11"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 }; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0 0x000>; 73 enable-method = "psci"; 74 }; 75 76 cpu1: cpu@1 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 reg = <0 0x001>; 80 enable-method = "psci"; 81 }; 82 }; 83 84 psci { 85 compatible = "arm,psci-1.0"; 86 method = "smc"; 87 }; 88 89 clocks { 90 refclk: ref { 91 compatible = "fixed-clock"; 92 #clock-cells = <0>; 93 clock-frequency = <25000000>; 94 }; 95 }; 96 97 timer { 98 compatible = "arm,armv8-timer"; 99 interrupts = <1 13 4>, 100 <1 14 4>, 101 <1 11 4>, 102 <1 10 4>; 103 }; 104 105 soc { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0 0 0 0xffffffff>; 110 111 serial0: serial@54006800 { 112 compatible = "socionext,uniphier-uart"; 113 status = "disabled"; 114 reg = <0x54006800 0x40>; 115 interrupts = <0 33 4>; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_uart0>; 118 clocks = <&peri_clk 0>; 119 }; 120 121 serial1: serial@54006900 { 122 compatible = "socionext,uniphier-uart"; 123 status = "disabled"; 124 reg = <0x54006900 0x40>; 125 interrupts = <0 35 4>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_uart1>; 128 clocks = <&peri_clk 1>; 129 }; 130 131 serial2: serial@54006a00 { 132 compatible = "socionext,uniphier-uart"; 133 status = "disabled"; 134 reg = <0x54006a00 0x40>; 135 interrupts = <0 37 4>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_uart2>; 138 clocks = <&peri_clk 2>; 139 }; 140 141 serial3: serial@54006b00 { 142 compatible = "socionext,uniphier-uart"; 143 status = "disabled"; 144 reg = <0x54006b00 0x40>; 145 interrupts = <0 177 4>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_uart3>; 148 clocks = <&peri_clk 3>; 149 }; 150 151 i2c0: i2c@58780000 { 152 compatible = "socionext,uniphier-fi2c"; 153 status = "disabled"; 154 reg = <0x58780000 0x80>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 interrupts = <0 41 4>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_i2c0>; 160 clocks = <&peri_clk 4>; 161 clock-frequency = <100000>; 162 }; 163 164 i2c1: i2c@58781000 { 165 compatible = "socionext,uniphier-fi2c"; 166 status = "disabled"; 167 reg = <0x58781000 0x80>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 interrupts = <0 42 4>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_i2c1>; 173 clocks = <&peri_clk 5>; 174 clock-frequency = <100000>; 175 }; 176 177 i2c2: i2c@58782000 { 178 compatible = "socionext,uniphier-fi2c"; 179 reg = <0x58782000 0x80>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 interrupts = <0 43 4>; 183 clocks = <&peri_clk 6>; 184 clock-frequency = <400000>; 185 }; 186 187 i2c3: i2c@58783000 { 188 compatible = "socionext,uniphier-fi2c"; 189 status = "disabled"; 190 reg = <0x58783000 0x80>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 interrupts = <0 44 4>; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_i2c3>; 196 clocks = <&peri_clk 7>; 197 clock-frequency = <100000>; 198 }; 199 200 i2c4: i2c@58784000 { 201 compatible = "socionext,uniphier-fi2c"; 202 status = "disabled"; 203 reg = <0x58784000 0x80>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 interrupts = <0 45 4>; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_i2c4>; 209 clocks = <&peri_clk 8>; 210 clock-frequency = <100000>; 211 }; 212 213 i2c5: i2c@58785000 { 214 compatible = "socionext,uniphier-fi2c"; 215 reg = <0x58785000 0x80>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 interrupts = <0 25 4>; 219 clocks = <&peri_clk 9>; 220 clock-frequency = <400000>; 221 }; 222 223 system_bus: system-bus@58c00000 { 224 compatible = "socionext,uniphier-system-bus"; 225 status = "disabled"; 226 reg = <0x58c00000 0x400>; 227 #address-cells = <2>; 228 #size-cells = <1>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_system_bus>; 231 }; 232 233 smpctrl@59800000 { 234 compatible = "socionext,uniphier-smpctrl"; 235 reg = <0x59801000 0x400>; 236 }; 237 238 perictrl@59820000 { 239 compatible = "socionext,uniphier-perictrl", 240 "simple-mfd", "syscon"; 241 reg = <0x59820000 0x200>; 242 243 peri_clk: clock { 244 compatible = "socionext,uniphier-ld11-peri-clock"; 245 #clock-cells = <1>; 246 }; 247 248 peri_rst: reset { 249 compatible = "socionext,uniphier-ld11-peri-reset"; 250 #reset-cells = <1>; 251 }; 252 }; 253 254 usb0: usb@5a800100 { 255 compatible = "socionext,uniphier-ehci", "generic-ehci"; 256 status = "disabled"; 257 reg = <0x5a800100 0x100>; 258 interrupts = <0 243 4>; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_usb0>; 261 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 262 resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; 263 }; 264 265 usb1: usb@5a810100 { 266 compatible = "socionext,uniphier-ehci", "generic-ehci"; 267 status = "disabled"; 268 reg = <0x5a810100 0x100>; 269 interrupts = <0 244 4>; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_usb1>; 272 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 273 resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; 274 }; 275 276 usb2: usb@5a820100 { 277 compatible = "socionext,uniphier-ehci", "generic-ehci"; 278 status = "disabled"; 279 reg = <0x5a820100 0x100>; 280 interrupts = <0 245 4>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_usb2>; 283 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 284 resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; 285 }; 286 287 mioctrl@5b3e0000 { 288 compatible = "socionext,uniphier-mioctrl", 289 "simple-mfd", "syscon"; 290 reg = <0x5b3e0000 0x800>; 291 292 mio_clk: clock { 293 compatible = "socionext,uniphier-ld11-mio-clock"; 294 #clock-cells = <1>; 295 }; 296 297 mio_rst: reset { 298 compatible = "socionext,uniphier-ld11-mio-reset"; 299 #reset-cells = <1>; 300 resets = <&sys_rst 7>; 301 }; 302 }; 303 304 soc-glue@5f800000 { 305 compatible = "socionext,uniphier-soc-glue", 306 "simple-mfd", "syscon"; 307 reg = <0x5f800000 0x2000>; 308 309 pinctrl: pinctrl { 310 compatible = "socionext,uniphier-ld11-pinctrl"; 311 }; 312 }; 313 314 gic: interrupt-controller@5fe00000 { 315 compatible = "arm,gic-v3"; 316 reg = <0x5fe00000 0x10000>, /* GICD */ 317 <0x5fe40000 0x80000>; /* GICR */ 318 interrupt-controller; 319 #interrupt-cells = <3>; 320 interrupts = <1 9 4>; 321 }; 322 323 sysctrl@61840000 { 324 compatible = "socionext,uniphier-ld11-sysctrl", 325 "simple-mfd", "syscon"; 326 reg = <0x61840000 0x10000>; 327 328 sys_clk: clock { 329 compatible = "socionext,uniphier-ld11-clock"; 330 #clock-cells = <1>; 331 }; 332 333 sys_rst: reset { 334 compatible = "socionext,uniphier-ld11-reset"; 335 #reset-cells = <1>; 336 }; 337 }; 338 }; 339}; 340 341/include/ "uniphier-pinctrl.dtsi" 342