1/* 2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc 11 */ 12 13/include/ "skeleton_hs_idu.dtsi" 14 15/ { 16 compatible = "snps,arc"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpu_card { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 26 27 input_clk: input-clk { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <33333333>; 31 }; 32 33 core_clk: core-clk@80 { 34 compatible = "snps,axs10x-arc-pll-clock"; 35 reg = <0x80 0x10>, <0x100 0x10>; 36 #clock-cells = <0>; 37 clocks = <&input_clk>; 38 }; 39 40 core_intc: archs-intc@cpu { 41 compatible = "snps,archs-intc"; 42 interrupt-controller; 43 #interrupt-cells = <1>; 44 }; 45 46 idu_intc: idu-interrupt-controller { 47 compatible = "snps,archs-idu-intc"; 48 interrupt-controller; 49 interrupt-parent = <&core_intc>; 50 #interrupt-cells = <1>; 51 }; 52 53 /* 54 * this GPIO block ORs all interrupts on CPU card (creg,..) 55 * to uplink only 1 IRQ to ARC core intc 56 */ 57 dw-apb-gpio@0x2000 { 58 compatible = "snps,dw-apb-gpio"; 59 reg = < 0x2000 0x80 >; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 ictl_intc: gpio-controller@0 { 64 compatible = "snps,dw-apb-gpio-port"; 65 gpio-controller; 66 #gpio-cells = <2>; 67 snps,nr-gpios = <30>; 68 reg = <0>; 69 interrupt-controller; 70 #interrupt-cells = <2>; 71 interrupt-parent = <&idu_intc>; 72 interrupts = <1>; 73 }; 74 }; 75 76 debug_uart: dw-apb-uart@0x5000 { 77 compatible = "snps,dw-apb-uart"; 78 reg = <0x5000 0x100>; 79 clock-frequency = <33333000>; 80 interrupt-parent = <&ictl_intc>; 81 interrupts = <2 4>; 82 baud = <115200>; 83 reg-shift = <2>; 84 reg-io-width = <4>; 85 }; 86 87 arcpct0: pct { 88 compatible = "snps,archs-pct"; 89 #interrupt-cells = <1>; 90 interrupt-parent = <&core_intc>; 91 interrupts = <20>; 92 }; 93 }; 94 95 /* 96 * This INTC is actually connected to DW APB GPIO 97 * which acts as a wire between MB INTC and CPU INTC. 98 * GPIO INTC is configured in platform init code 99 * and here we mimic direct connection from MB INTC to 100 * CPU INTC, thus we set "interrupts = <0 1>" instead of 101 * "interrupts = <12>" 102 * 103 * This intc actually resides on MB, but we move it here to 104 * avoid duplicating the MB dtsi file given that IRQ from 105 * this intc to cpu intc are different for axs101 and axs103 106 */ 107 mb_intc: dw-apb-ictl@0xe0012000 { 108 #interrupt-cells = <1>; 109 compatible = "snps,dw-apb-ictl"; 110 reg = < 0x0 0xe0012000 0x0 0x200 >; 111 interrupt-controller; 112 interrupt-parent = <&idu_intc>; 113 interrupts = <0>; 114 }; 115 116 memory { 117 device_type = "memory"; 118 /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */ 119 reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ 120 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ 121 }; 122 123 reserved-memory { 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges; 127 /* 128 * Move frame buffer out of IOC aperture (0x8z-0xAz). 129 */ 130 frame_buffer: frame_buffer@be000000 { 131 compatible = "shared-dma-pool"; 132 reg = <0x0 0xbe000000 0x0 0x2000000>; 133 no-map; 134 }; 135 }; 136}; 137