1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 #ifndef __SDHCI_HW_H 11 #define __SDHCI_HW_H 12 13 #include <asm/io.h> 14 #include <mmc.h> 15 #include <asm/gpio.h> 16 17 /* 18 * Controller registers 19 */ 20 21 #define SDHCI_DMA_ADDRESS 0x00 22 23 #define SDHCI_BLOCK_SIZE 0x04 24 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 25 26 #define SDHCI_BLOCK_COUNT 0x06 27 28 #define SDHCI_ARGUMENT 0x08 29 30 #define SDHCI_TRANSFER_MODE 0x0C 31 #define SDHCI_TRNS_DMA BIT(0) 32 #define SDHCI_TRNS_BLK_CNT_EN BIT(1) 33 #define SDHCI_TRNS_ACMD12 BIT(2) 34 #define SDHCI_TRNS_READ BIT(4) 35 #define SDHCI_TRNS_MULTI BIT(5) 36 37 #define SDHCI_COMMAND 0x0E 38 #define SDHCI_CMD_RESP_MASK 0x03 39 #define SDHCI_CMD_CRC 0x08 40 #define SDHCI_CMD_INDEX 0x10 41 #define SDHCI_CMD_DATA 0x20 42 #define SDHCI_CMD_ABORTCMD 0xC0 43 44 #define SDHCI_CMD_RESP_NONE 0x00 45 #define SDHCI_CMD_RESP_LONG 0x01 46 #define SDHCI_CMD_RESP_SHORT 0x02 47 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 48 49 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 50 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 51 52 #define SDHCI_RESPONSE 0x10 53 54 #define SDHCI_BUFFER 0x20 55 56 #define SDHCI_PRESENT_STATE 0x24 57 #define SDHCI_CMD_INHIBIT BIT(0) 58 #define SDHCI_DATA_INHIBIT BIT(1) 59 #define SDHCI_DOING_WRITE BIT(8) 60 #define SDHCI_DOING_READ BIT(9) 61 #define SDHCI_SPACE_AVAILABLE BIT(10) 62 #define SDHCI_DATA_AVAILABLE BIT(11) 63 #define SDHCI_CARD_PRESENT BIT(16) 64 #define SDHCI_CARD_STATE_STABLE BIT(17) 65 #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18) 66 #define SDHCI_WRITE_PROTECT BIT(19) 67 68 #define SDHCI_HOST_CONTROL 0x28 69 #define SDHCI_CTRL_LED BIT(0) 70 #define SDHCI_CTRL_4BITBUS BIT(1) 71 #define SDHCI_CTRL_HISPD BIT(2) 72 #define SDHCI_CTRL_DMA_MASK 0x18 73 #define SDHCI_CTRL_SDMA 0x00 74 #define SDHCI_CTRL_ADMA1 0x08 75 #define SDHCI_CTRL_ADMA32 0x10 76 #define SDHCI_CTRL_ADMA64 0x18 77 #define SDHCI_CTRL_8BITBUS BIT(5) 78 #define SDHCI_CTRL_CD_TEST_INS BIT(6) 79 #define SDHCI_CTRL_CD_TEST BIT(7) 80 81 #define SDHCI_POWER_CONTROL 0x29 82 #define SDHCI_POWER_ON 0x01 83 #define SDHCI_POWER_180 0x0A 84 #define SDHCI_POWER_300 0x0C 85 #define SDHCI_POWER_330 0x0E 86 87 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 88 89 #define SDHCI_WAKE_UP_CONTROL 0x2B 90 #define SDHCI_WAKE_ON_INT BIT(0) 91 #define SDHCI_WAKE_ON_INSERT BIT(1) 92 #define SDHCI_WAKE_ON_REMOVE BIT(2) 93 94 #define SDHCI_CLOCK_CONTROL 0x2C 95 #define SDHCI_DIVIDER_SHIFT 8 96 #define SDHCI_DIVIDER_HI_SHIFT 6 97 #define SDHCI_DIV_MASK 0xFF 98 #define SDHCI_DIV_MASK_LEN 8 99 #define SDHCI_DIV_HI_MASK 0x300 100 #define SDHCI_PROG_CLOCK_MODE BIT(5) 101 #define SDHCI_CLOCK_CARD_EN BIT(2) 102 #define SDHCI_CLOCK_INT_STABLE BIT(1) 103 #define SDHCI_CLOCK_INT_EN BIT(0) 104 105 #define SDHCI_TIMEOUT_CONTROL 0x2E 106 107 #define SDHCI_SOFTWARE_RESET 0x2F 108 #define SDHCI_RESET_ALL 0x01 109 #define SDHCI_RESET_CMD 0x02 110 #define SDHCI_RESET_DATA 0x04 111 112 #define SDHCI_INT_STATUS 0x30 113 #define SDHCI_INT_ENABLE 0x34 114 #define SDHCI_SIGNAL_ENABLE 0x38 115 #define SDHCI_INT_RESPONSE BIT(0) 116 #define SDHCI_INT_DATA_END BIT(1) 117 #define SDHCI_INT_DMA_END BIT(3) 118 #define SDHCI_INT_SPACE_AVAIL BIT(4) 119 #define SDHCI_INT_DATA_AVAIL BIT(5) 120 #define SDHCI_INT_CARD_INSERT BIT(6) 121 #define SDHCI_INT_CARD_REMOVE BIT(7) 122 #define SDHCI_INT_CARD_INT BIT(8) 123 #define SDHCI_INT_ERROR BIT(15) 124 #define SDHCI_INT_TIMEOUT BIT(16) 125 #define SDHCI_INT_CRC BIT(17) 126 #define SDHCI_INT_END_BIT BIT(18) 127 #define SDHCI_INT_INDEX BIT(19) 128 #define SDHCI_INT_DATA_TIMEOUT BIT(20) 129 #define SDHCI_INT_DATA_CRC BIT(21) 130 #define SDHCI_INT_DATA_END_BIT BIT(22) 131 #define SDHCI_INT_BUS_POWER BIT(23) 132 #define SDHCI_INT_ACMD12ERR BIT(24) 133 #define SDHCI_INT_ADMA_ERROR BIT(25) 134 135 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 136 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 137 138 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 139 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 140 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 141 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 142 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 143 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) 144 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 145 146 #define SDHCI_ACMD12_ERR 0x3C 147 148 /* 3E-3F reserved */ 149 150 #define SDHCI_CAPABILITIES 0x40 151 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 152 #define SDHCI_TIMEOUT_CLK_SHIFT 0 153 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 154 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 155 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 156 #define SDHCI_CLOCK_BASE_SHIFT 8 157 #define SDHCI_MAX_BLOCK_MASK 0x00030000 158 #define SDHCI_MAX_BLOCK_SHIFT 16 159 #define SDHCI_CAN_DO_8BIT BIT(18) 160 #define SDHCI_CAN_DO_ADMA2 BIT(19) 161 #define SDHCI_CAN_DO_ADMA1 BIT(20) 162 #define SDHCI_CAN_DO_HISPD BIT(21) 163 #define SDHCI_CAN_DO_SDMA BIT(22) 164 #define SDHCI_CAN_VDD_330 BIT(24) 165 #define SDHCI_CAN_VDD_300 BIT(25) 166 #define SDHCI_CAN_VDD_180 BIT(26) 167 #define SDHCI_CAN_64BIT BIT(28) 168 169 #define SDHCI_CAPABILITIES_1 0x44 170 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 171 #define SDHCI_CLOCK_MUL_SHIFT 16 172 173 #define SDHCI_MAX_CURRENT 0x48 174 175 /* 4C-4F reserved for more max current */ 176 177 #define SDHCI_SET_ACMD12_ERROR 0x50 178 #define SDHCI_SET_INT_ERROR 0x52 179 180 #define SDHCI_ADMA_ERROR 0x54 181 182 /* 55-57 reserved */ 183 184 #define SDHCI_ADMA_ADDRESS 0x58 185 186 /* 60-FB reserved */ 187 188 #define SDHCI_SLOT_INT_STATUS 0xFC 189 190 #define SDHCI_HOST_VERSION 0xFE 191 #define SDHCI_VENDOR_VER_MASK 0xFF00 192 #define SDHCI_VENDOR_VER_SHIFT 8 193 #define SDHCI_SPEC_VER_MASK 0x00FF 194 #define SDHCI_SPEC_VER_SHIFT 0 195 #define SDHCI_SPEC_100 0 196 #define SDHCI_SPEC_200 1 197 #define SDHCI_SPEC_300 2 198 199 #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK) 200 201 /* 202 * End of controller registers. 203 */ 204 205 #define SDHCI_MAX_DIV_SPEC_200 256 206 #define SDHCI_MAX_DIV_SPEC_300 2046 207 208 /* 209 * quirks 210 */ 211 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) 212 #define SDHCI_QUIRK_REG32_RW (1 << 1) 213 #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) 214 #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) 215 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) 216 #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) 217 #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) 218 219 /* to make gcc happy */ 220 struct sdhci_host; 221 222 /* 223 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 224 */ 225 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 226 #define SDHCI_DEFAULT_BOUNDARY_ARG (7) 227 struct sdhci_ops { 228 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 229 u32 (*read_l)(struct sdhci_host *host, int reg); 230 u16 (*read_w)(struct sdhci_host *host, int reg); 231 u8 (*read_b)(struct sdhci_host *host, int reg); 232 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 233 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 234 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 235 #endif 236 int (*get_cd)(struct sdhci_host *host); 237 void (*set_control_reg)(struct sdhci_host *host); 238 void (*set_ios_post)(struct sdhci_host *host); 239 void (*set_clock)(struct sdhci_host *host, u32 div); 240 }; 241 242 struct sdhci_host { 243 const char *name; 244 void *ioaddr; 245 unsigned int quirks; 246 unsigned int host_caps; 247 unsigned int version; 248 unsigned int max_clk; /* Maximum Base Clock frequency */ 249 unsigned int clk_mul; /* Clock Multiplier value */ 250 unsigned int clock; 251 struct mmc *mmc; 252 const struct sdhci_ops *ops; 253 int index; 254 255 int bus_width; 256 struct gpio_desc pwr_gpio; /* Power GPIO */ 257 struct gpio_desc cd_gpio; /* Card Detect GPIO */ 258 259 uint voltages; 260 261 struct mmc_config cfg; 262 }; 263 264 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 265 266 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 267 { 268 if (unlikely(host->ops->write_l)) 269 host->ops->write_l(host, val, reg); 270 else 271 writel(val, host->ioaddr + reg); 272 } 273 274 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 275 { 276 if (unlikely(host->ops->write_w)) 277 host->ops->write_w(host, val, reg); 278 else 279 writew(val, host->ioaddr + reg); 280 } 281 282 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 283 { 284 if (unlikely(host->ops->write_b)) 285 host->ops->write_b(host, val, reg); 286 else 287 writeb(val, host->ioaddr + reg); 288 } 289 290 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 291 { 292 if (unlikely(host->ops->read_l)) 293 return host->ops->read_l(host, reg); 294 else 295 return readl(host->ioaddr + reg); 296 } 297 298 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 299 { 300 if (unlikely(host->ops->read_w)) 301 return host->ops->read_w(host, reg); 302 else 303 return readw(host->ioaddr + reg); 304 } 305 306 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 307 { 308 if (unlikely(host->ops->read_b)) 309 return host->ops->read_b(host, reg); 310 else 311 return readb(host->ioaddr + reg); 312 } 313 314 #else 315 316 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 317 { 318 writel(val, host->ioaddr + reg); 319 } 320 321 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 322 { 323 writew(val, host->ioaddr + reg); 324 } 325 326 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 327 { 328 writeb(val, host->ioaddr + reg); 329 } 330 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 331 { 332 return readl(host->ioaddr + reg); 333 } 334 335 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 336 { 337 return readw(host->ioaddr + reg); 338 } 339 340 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 341 { 342 return readb(host->ioaddr + reg); 343 } 344 #endif 345 346 #ifdef CONFIG_BLK 347 /** 348 * sdhci_setup_cfg() - Set up the configuration for DWMMC 349 * 350 * This is used to set up an SDHCI device when you are using CONFIG_BLK. 351 * 352 * This should be called from your MMC driver's probe() method once you have 353 * the information required. 354 * 355 * Generally your driver will have a platform data structure which holds both 356 * the configuration (struct mmc_config) and the MMC device info (struct mmc). 357 * For example: 358 * 359 * struct msm_sdhc_plat { 360 * struct mmc_config cfg; 361 * struct mmc mmc; 362 * }; 363 * 364 * ... 365 * 366 * Inside U_BOOT_DRIVER(): 367 * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat), 368 * 369 * To access platform data: 370 * struct msm_sdhc_plat *plat = dev_get_platdata(dev); 371 * 372 * See msm_sdhci.c for an example. 373 * 374 * @cfg: Configuration structure to fill in (generally &plat->mmc) 375 * @host: SDHCI host structure 376 * @f_max: Maximum supported clock frequency in HZ (0 for default) 377 * @f_min: Minimum supported clock frequency in HZ (0 for default) 378 */ 379 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, 380 u32 f_max, u32 f_min); 381 382 /** 383 * sdhci_bind() - Set up a new MMC block device 384 * 385 * This is used to set up an SDHCI block device when you are using CONFIG_BLK. 386 * It should be called from your driver's bind() method. 387 * 388 * See msm_sdhci.c for an example. 389 * 390 * @dev: Device to set up 391 * @mmc: Pointer to mmc structure (normally &plat->mmc) 392 * @cfg: Empty configuration structure (generally &plat->cfg). This is 393 * normally all zeroes at this point. The only purpose of passing 394 * this in is to set mmc->cfg to it. 395 * @return 0 if OK, -ve if the block device could not be created 396 */ 397 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); 398 #else 399 400 /** 401 * add_sdhci() - Add a new SDHCI interface 402 * 403 * This is used when you are not using CONFIG_BLK. Convert your driver over! 404 * 405 * @host: SDHCI host structure 406 * @f_max: Maximum supported clock frequency in HZ (0 for default) 407 * @f_min: Minimum supported clock frequency in HZ (0 for default) 408 * @return 0 if OK, -ve on error 409 */ 410 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min); 411 #endif /* !CONFIG_BLK */ 412 413 #ifdef CONFIG_DM_MMC_OPS 414 /* Export the operations to drivers */ 415 int sdhci_probe(struct udevice *dev); 416 extern const struct dm_mmc_ops sdhci_ops; 417 #else 418 #endif 419 420 #endif /* __SDHCI_HW_H */ 421