1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 * Back ported to the 8xx platform (from the 8260 platform) by 24 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 25 */ 26 #ifndef __SDHCI_HW_H 27 #define __SDHCI_HW_H 28 29 #include <asm/io.h> 30 #include <mmc.h> 31 32 /* 33 * Controller registers 34 */ 35 36 #define SDHCI_DMA_ADDRESS 0x00 37 38 #define SDHCI_BLOCK_SIZE 0x04 39 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 40 41 #define SDHCI_BLOCK_COUNT 0x06 42 43 #define SDHCI_ARGUMENT 0x08 44 45 #define SDHCI_TRANSFER_MODE 0x0C 46 #define SDHCI_TRNS_DMA 0x01 47 #define SDHCI_TRNS_BLK_CNT_EN 0x02 48 #define SDHCI_TRNS_ACMD12 0x04 49 #define SDHCI_TRNS_READ 0x10 50 #define SDHCI_TRNS_MULTI 0x20 51 52 #define SDHCI_COMMAND 0x0E 53 #define SDHCI_CMD_RESP_MASK 0x03 54 #define SDHCI_CMD_CRC 0x08 55 #define SDHCI_CMD_INDEX 0x10 56 #define SDHCI_CMD_DATA 0x20 57 #define SDHCI_CMD_ABORTCMD 0xC0 58 59 #define SDHCI_CMD_RESP_NONE 0x00 60 #define SDHCI_CMD_RESP_LONG 0x01 61 #define SDHCI_CMD_RESP_SHORT 0x02 62 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 63 64 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 65 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 66 67 #define SDHCI_RESPONSE 0x10 68 69 #define SDHCI_BUFFER 0x20 70 71 #define SDHCI_PRESENT_STATE 0x24 72 #define SDHCI_CMD_INHIBIT 0x00000001 73 #define SDHCI_DATA_INHIBIT 0x00000002 74 #define SDHCI_DOING_WRITE 0x00000100 75 #define SDHCI_DOING_READ 0x00000200 76 #define SDHCI_SPACE_AVAILABLE 0x00000400 77 #define SDHCI_DATA_AVAILABLE 0x00000800 78 #define SDHCI_CARD_PRESENT 0x00010000 79 #define SDHCI_WRITE_PROTECT 0x00080000 80 81 #define SDHCI_HOST_CONTROL 0x28 82 #define SDHCI_CTRL_LED 0x01 83 #define SDHCI_CTRL_4BITBUS 0x02 84 #define SDHCI_CTRL_HISPD 0x04 85 #define SDHCI_CTRL_DMA_MASK 0x18 86 #define SDHCI_CTRL_SDMA 0x00 87 #define SDHCI_CTRL_ADMA1 0x08 88 #define SDHCI_CTRL_ADMA32 0x10 89 #define SDHCI_CTRL_ADMA64 0x18 90 #define SDHCI_CTRL_8BITBUS 0x20 91 92 #define SDHCI_POWER_CONTROL 0x29 93 #define SDHCI_POWER_ON 0x01 94 #define SDHCI_POWER_180 0x0A 95 #define SDHCI_POWER_300 0x0C 96 #define SDHCI_POWER_330 0x0E 97 98 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 99 100 #define SDHCI_WAKE_UP_CONTROL 0x2B 101 #define SDHCI_WAKE_ON_INT 0x01 102 #define SDHCI_WAKE_ON_INSERT 0x02 103 #define SDHCI_WAKE_ON_REMOVE 0x04 104 105 #define SDHCI_CLOCK_CONTROL 0x2C 106 #define SDHCI_DIVIDER_SHIFT 8 107 #define SDHCI_DIVIDER_HI_SHIFT 6 108 #define SDHCI_DIV_MASK 0xFF 109 #define SDHCI_DIV_MASK_LEN 8 110 #define SDHCI_DIV_HI_MASK 0x300 111 #define SDHCI_CLOCK_CARD_EN 0x0004 112 #define SDHCI_CLOCK_INT_STABLE 0x0002 113 #define SDHCI_CLOCK_INT_EN 0x0001 114 115 #define SDHCI_TIMEOUT_CONTROL 0x2E 116 117 #define SDHCI_SOFTWARE_RESET 0x2F 118 #define SDHCI_RESET_ALL 0x01 119 #define SDHCI_RESET_CMD 0x02 120 #define SDHCI_RESET_DATA 0x04 121 122 #define SDHCI_INT_STATUS 0x30 123 #define SDHCI_INT_ENABLE 0x34 124 #define SDHCI_SIGNAL_ENABLE 0x38 125 #define SDHCI_INT_RESPONSE 0x00000001 126 #define SDHCI_INT_DATA_END 0x00000002 127 #define SDHCI_INT_DMA_END 0x00000008 128 #define SDHCI_INT_SPACE_AVAIL 0x00000010 129 #define SDHCI_INT_DATA_AVAIL 0x00000020 130 #define SDHCI_INT_CARD_INSERT 0x00000040 131 #define SDHCI_INT_CARD_REMOVE 0x00000080 132 #define SDHCI_INT_CARD_INT 0x00000100 133 #define SDHCI_INT_ERROR 0x00008000 134 #define SDHCI_INT_TIMEOUT 0x00010000 135 #define SDHCI_INT_CRC 0x00020000 136 #define SDHCI_INT_END_BIT 0x00040000 137 #define SDHCI_INT_INDEX 0x00080000 138 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 139 #define SDHCI_INT_DATA_CRC 0x00200000 140 #define SDHCI_INT_DATA_END_BIT 0x00400000 141 #define SDHCI_INT_BUS_POWER 0x00800000 142 #define SDHCI_INT_ACMD12ERR 0x01000000 143 #define SDHCI_INT_ADMA_ERROR 0x02000000 144 145 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 146 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 147 148 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 149 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 150 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 151 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 152 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 153 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) 154 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 155 156 #define SDHCI_ACMD12_ERR 0x3C 157 158 /* 3E-3F reserved */ 159 160 #define SDHCI_CAPABILITIES 0x40 161 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 162 #define SDHCI_TIMEOUT_CLK_SHIFT 0 163 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 164 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 165 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 166 #define SDHCI_CLOCK_BASE_SHIFT 8 167 #define SDHCI_MAX_BLOCK_MASK 0x00030000 168 #define SDHCI_MAX_BLOCK_SHIFT 16 169 #define SDHCI_CAN_DO_8BIT 0x00040000 170 #define SDHCI_CAN_DO_ADMA2 0x00080000 171 #define SDHCI_CAN_DO_ADMA1 0x00100000 172 #define SDHCI_CAN_DO_HISPD 0x00200000 173 #define SDHCI_CAN_DO_SDMA 0x00400000 174 #define SDHCI_CAN_VDD_330 0x01000000 175 #define SDHCI_CAN_VDD_300 0x02000000 176 #define SDHCI_CAN_VDD_180 0x04000000 177 #define SDHCI_CAN_64BIT 0x10000000 178 179 #define SDHCI_CAPABILITIES_1 0x44 180 181 #define SDHCI_MAX_CURRENT 0x48 182 183 /* 4C-4F reserved for more max current */ 184 185 #define SDHCI_SET_ACMD12_ERROR 0x50 186 #define SDHCI_SET_INT_ERROR 0x52 187 188 #define SDHCI_ADMA_ERROR 0x54 189 190 /* 55-57 reserved */ 191 192 #define SDHCI_ADMA_ADDRESS 0x58 193 194 /* 60-FB reserved */ 195 196 #define SDHCI_SLOT_INT_STATUS 0xFC 197 198 #define SDHCI_HOST_VERSION 0xFE 199 #define SDHCI_VENDOR_VER_MASK 0xFF00 200 #define SDHCI_VENDOR_VER_SHIFT 8 201 #define SDHCI_SPEC_VER_MASK 0x00FF 202 #define SDHCI_SPEC_VER_SHIFT 0 203 #define SDHCI_SPEC_100 0 204 #define SDHCI_SPEC_200 1 205 #define SDHCI_SPEC_300 2 206 207 /* 208 * End of controller registers. 209 */ 210 211 #define SDHCI_MAX_DIV_SPEC_200 256 212 #define SDHCI_MAX_DIV_SPEC_300 2046 213 214 /* 215 * quirks 216 */ 217 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) 218 #define SDHCI_QUIRK_REG32_RW (1 << 1) 219 #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) 220 #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) 221 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) 222 223 /* to make gcc happy */ 224 struct sdhci_host; 225 226 /* 227 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 228 */ 229 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 230 #define SDHCI_DEFAULT_BOUNDARY_ARG (7) 231 struct sdhci_ops { 232 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 233 u32 (*read_l)(struct sdhci_host *host, int reg); 234 u16 (*read_w)(struct sdhci_host *host, int reg); 235 u8 (*read_b)(struct sdhci_host *host, int reg); 236 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 237 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 238 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 239 #endif 240 }; 241 242 struct sdhci_host { 243 char *name; 244 void *ioaddr; 245 unsigned int quirks; 246 unsigned int host_caps; 247 unsigned int version; 248 unsigned int clock; 249 struct mmc *mmc; 250 const struct sdhci_ops *ops; 251 252 void (*set_control_reg)(struct sdhci_host *host); 253 uint voltages; 254 }; 255 256 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 257 258 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 259 { 260 if (unlikely(host->ops->write_l)) 261 host->ops->write_l(host, val, reg); 262 else 263 writel(val, host->ioaddr + reg); 264 } 265 266 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 267 { 268 if (unlikely(host->ops->write_w)) 269 host->ops->write_w(host, val, reg); 270 else 271 writew(val, host->ioaddr + reg); 272 } 273 274 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 275 { 276 if (unlikely(host->ops->write_b)) 277 host->ops->write_b(host, val, reg); 278 else 279 writeb(val, host->ioaddr + reg); 280 } 281 282 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 283 { 284 if (unlikely(host->ops->read_l)) 285 return host->ops->read_l(host, reg); 286 else 287 return readl(host->ioaddr + reg); 288 } 289 290 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 291 { 292 if (unlikely(host->ops->read_w)) 293 return host->ops->read_w(host, reg); 294 else 295 return readw(host->ioaddr + reg); 296 } 297 298 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 299 { 300 if (unlikely(host->ops->read_b)) 301 return host->ops->read_b(host, reg); 302 else 303 return readb(host->ioaddr + reg); 304 } 305 306 #else 307 308 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 309 { 310 writel(val, host->ioaddr + reg); 311 } 312 313 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 314 { 315 writew(val, host->ioaddr + reg); 316 } 317 318 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 319 { 320 writeb(val, host->ioaddr + reg); 321 } 322 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 323 { 324 return readl(host->ioaddr + reg); 325 } 326 327 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 328 { 329 return readw(host->ioaddr + reg); 330 } 331 332 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 333 { 334 return readb(host->ioaddr + reg); 335 } 336 #endif 337 338 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk); 339 #endif /* __SDHCI_HW_H */ 340