1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 #ifndef __SDHCI_HW_H 11 #define __SDHCI_HW_H 12 13 #include <asm/io.h> 14 #include <mmc.h> 15 #include <asm/gpio.h> 16 17 /* 18 * Controller registers 19 */ 20 21 #define SDHCI_DMA_ADDRESS 0x00 22 23 #define SDHCI_BLOCK_SIZE 0x04 24 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 25 26 #define SDHCI_BLOCK_COUNT 0x06 27 28 #define SDHCI_ARGUMENT 0x08 29 30 #define SDHCI_TRANSFER_MODE 0x0C 31 #define SDHCI_TRNS_DMA 0x01 32 #define SDHCI_TRNS_BLK_CNT_EN 0x02 33 #define SDHCI_TRNS_ACMD12 0x04 34 #define SDHCI_TRNS_READ 0x10 35 #define SDHCI_TRNS_MULTI 0x20 36 37 #define SDHCI_COMMAND 0x0E 38 #define SDHCI_CMD_RESP_MASK 0x03 39 #define SDHCI_CMD_CRC 0x08 40 #define SDHCI_CMD_INDEX 0x10 41 #define SDHCI_CMD_DATA 0x20 42 #define SDHCI_CMD_ABORTCMD 0xC0 43 44 #define SDHCI_CMD_RESP_NONE 0x00 45 #define SDHCI_CMD_RESP_LONG 0x01 46 #define SDHCI_CMD_RESP_SHORT 0x02 47 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 48 49 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 50 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 51 52 #define SDHCI_RESPONSE 0x10 53 54 #define SDHCI_BUFFER 0x20 55 56 #define SDHCI_PRESENT_STATE 0x24 57 #define SDHCI_CMD_INHIBIT 0x00000001 58 #define SDHCI_DATA_INHIBIT 0x00000002 59 #define SDHCI_DOING_WRITE 0x00000100 60 #define SDHCI_DOING_READ 0x00000200 61 #define SDHCI_SPACE_AVAILABLE 0x00000400 62 #define SDHCI_DATA_AVAILABLE 0x00000800 63 #define SDHCI_CARD_PRESENT 0x00010000 64 #define SDHCI_CARD_STATE_STABLE 0x00020000 65 #define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000 66 #define SDHCI_WRITE_PROTECT 0x00080000 67 68 #define SDHCI_HOST_CONTROL 0x28 69 #define SDHCI_CTRL_LED 0x01 70 #define SDHCI_CTRL_4BITBUS 0x02 71 #define SDHCI_CTRL_HISPD 0x04 72 #define SDHCI_CTRL_DMA_MASK 0x18 73 #define SDHCI_CTRL_SDMA 0x00 74 #define SDHCI_CTRL_ADMA1 0x08 75 #define SDHCI_CTRL_ADMA32 0x10 76 #define SDHCI_CTRL_ADMA64 0x18 77 #define SDHCI_CTRL_8BITBUS 0x20 78 #define SDHCI_CTRL_CD_TEST_INS 0x40 79 #define SDHCI_CTRL_CD_TEST 0x80 80 81 #define SDHCI_POWER_CONTROL 0x29 82 #define SDHCI_POWER_ON 0x01 83 #define SDHCI_POWER_180 0x0A 84 #define SDHCI_POWER_300 0x0C 85 #define SDHCI_POWER_330 0x0E 86 87 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 88 89 #define SDHCI_WAKE_UP_CONTROL 0x2B 90 #define SDHCI_WAKE_ON_INT 0x01 91 #define SDHCI_WAKE_ON_INSERT 0x02 92 #define SDHCI_WAKE_ON_REMOVE 0x04 93 94 #define SDHCI_CLOCK_CONTROL 0x2C 95 #define SDHCI_DIVIDER_SHIFT 8 96 #define SDHCI_DIVIDER_HI_SHIFT 6 97 #define SDHCI_DIV_MASK 0xFF 98 #define SDHCI_DIV_MASK_LEN 8 99 #define SDHCI_DIV_HI_MASK 0x300 100 #define SDHCI_PROG_CLOCK_MODE 0x0020 101 #define SDHCI_CLOCK_CARD_EN 0x0004 102 #define SDHCI_CLOCK_INT_STABLE 0x0002 103 #define SDHCI_CLOCK_INT_EN 0x0001 104 105 #define SDHCI_TIMEOUT_CONTROL 0x2E 106 107 #define SDHCI_SOFTWARE_RESET 0x2F 108 #define SDHCI_RESET_ALL 0x01 109 #define SDHCI_RESET_CMD 0x02 110 #define SDHCI_RESET_DATA 0x04 111 112 #define SDHCI_INT_STATUS 0x30 113 #define SDHCI_INT_ENABLE 0x34 114 #define SDHCI_SIGNAL_ENABLE 0x38 115 #define SDHCI_INT_RESPONSE 0x00000001 116 #define SDHCI_INT_DATA_END 0x00000002 117 #define SDHCI_INT_DMA_END 0x00000008 118 #define SDHCI_INT_SPACE_AVAIL 0x00000010 119 #define SDHCI_INT_DATA_AVAIL 0x00000020 120 #define SDHCI_INT_CARD_INSERT 0x00000040 121 #define SDHCI_INT_CARD_REMOVE 0x00000080 122 #define SDHCI_INT_CARD_INT 0x00000100 123 #define SDHCI_INT_ERROR 0x00008000 124 #define SDHCI_INT_TIMEOUT 0x00010000 125 #define SDHCI_INT_CRC 0x00020000 126 #define SDHCI_INT_END_BIT 0x00040000 127 #define SDHCI_INT_INDEX 0x00080000 128 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 129 #define SDHCI_INT_DATA_CRC 0x00200000 130 #define SDHCI_INT_DATA_END_BIT 0x00400000 131 #define SDHCI_INT_BUS_POWER 0x00800000 132 #define SDHCI_INT_ACMD12ERR 0x01000000 133 #define SDHCI_INT_ADMA_ERROR 0x02000000 134 135 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 136 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 137 138 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 139 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 140 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 141 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 142 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 143 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) 144 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 145 146 #define SDHCI_ACMD12_ERR 0x3C 147 148 /* 3E-3F reserved */ 149 150 #define SDHCI_CAPABILITIES 0x40 151 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 152 #define SDHCI_TIMEOUT_CLK_SHIFT 0 153 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 154 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 155 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 156 #define SDHCI_CLOCK_BASE_SHIFT 8 157 #define SDHCI_MAX_BLOCK_MASK 0x00030000 158 #define SDHCI_MAX_BLOCK_SHIFT 16 159 #define SDHCI_CAN_DO_8BIT 0x00040000 160 #define SDHCI_CAN_DO_ADMA2 0x00080000 161 #define SDHCI_CAN_DO_ADMA1 0x00100000 162 #define SDHCI_CAN_DO_HISPD 0x00200000 163 #define SDHCI_CAN_DO_SDMA 0x00400000 164 #define SDHCI_CAN_VDD_330 0x01000000 165 #define SDHCI_CAN_VDD_300 0x02000000 166 #define SDHCI_CAN_VDD_180 0x04000000 167 #define SDHCI_CAN_64BIT 0x10000000 168 169 #define SDHCI_CAPABILITIES_1 0x44 170 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 171 #define SDHCI_CLOCK_MUL_SHIFT 16 172 173 #define SDHCI_MAX_CURRENT 0x48 174 175 /* 4C-4F reserved for more max current */ 176 177 #define SDHCI_SET_ACMD12_ERROR 0x50 178 #define SDHCI_SET_INT_ERROR 0x52 179 180 #define SDHCI_ADMA_ERROR 0x54 181 182 /* 55-57 reserved */ 183 184 #define SDHCI_ADMA_ADDRESS 0x58 185 186 /* 60-FB reserved */ 187 188 #define SDHCI_SLOT_INT_STATUS 0xFC 189 190 #define SDHCI_HOST_VERSION 0xFE 191 #define SDHCI_VENDOR_VER_MASK 0xFF00 192 #define SDHCI_VENDOR_VER_SHIFT 8 193 #define SDHCI_SPEC_VER_MASK 0x00FF 194 #define SDHCI_SPEC_VER_SHIFT 0 195 #define SDHCI_SPEC_100 0 196 #define SDHCI_SPEC_200 1 197 #define SDHCI_SPEC_300 2 198 199 #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK) 200 201 /* 202 * End of controller registers. 203 */ 204 205 #define SDHCI_MAX_DIV_SPEC_200 256 206 #define SDHCI_MAX_DIV_SPEC_300 2046 207 208 /* 209 * quirks 210 */ 211 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) 212 #define SDHCI_QUIRK_REG32_RW (1 << 1) 213 #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) 214 #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) 215 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) 216 #define SDHCI_QUIRK_NO_CD (1 << 5) 217 #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) 218 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7) 219 #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) 220 221 /* to make gcc happy */ 222 struct sdhci_host; 223 224 /* 225 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 226 */ 227 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 228 #define SDHCI_DEFAULT_BOUNDARY_ARG (7) 229 struct sdhci_ops { 230 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 231 u32 (*read_l)(struct sdhci_host *host, int reg); 232 u16 (*read_w)(struct sdhci_host *host, int reg); 233 u8 (*read_b)(struct sdhci_host *host, int reg); 234 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 235 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 236 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 237 #endif 238 }; 239 240 struct sdhci_host { 241 const char *name; 242 void *ioaddr; 243 unsigned int quirks; 244 unsigned int host_caps; 245 unsigned int version; 246 unsigned int clk_mul; /* Clock Multiplier value */ 247 unsigned int clock; 248 struct mmc *mmc; 249 const struct sdhci_ops *ops; 250 int index; 251 252 int bus_width; 253 struct gpio_desc pwr_gpio; /* Power GPIO */ 254 struct gpio_desc cd_gpio; /* Card Detect GPIO */ 255 256 void (*set_control_reg)(struct sdhci_host *host); 257 void (*set_clock)(int dev_index, unsigned int div); 258 uint voltages; 259 260 struct mmc_config cfg; 261 }; 262 263 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 264 265 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 266 { 267 if (unlikely(host->ops->write_l)) 268 host->ops->write_l(host, val, reg); 269 else 270 writel(val, host->ioaddr + reg); 271 } 272 273 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 274 { 275 if (unlikely(host->ops->write_w)) 276 host->ops->write_w(host, val, reg); 277 else 278 writew(val, host->ioaddr + reg); 279 } 280 281 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 282 { 283 if (unlikely(host->ops->write_b)) 284 host->ops->write_b(host, val, reg); 285 else 286 writeb(val, host->ioaddr + reg); 287 } 288 289 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 290 { 291 if (unlikely(host->ops->read_l)) 292 return host->ops->read_l(host, reg); 293 else 294 return readl(host->ioaddr + reg); 295 } 296 297 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 298 { 299 if (unlikely(host->ops->read_w)) 300 return host->ops->read_w(host, reg); 301 else 302 return readw(host->ioaddr + reg); 303 } 304 305 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 306 { 307 if (unlikely(host->ops->read_b)) 308 return host->ops->read_b(host, reg); 309 else 310 return readb(host->ioaddr + reg); 311 } 312 313 #else 314 315 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 316 { 317 writel(val, host->ioaddr + reg); 318 } 319 320 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 321 { 322 writew(val, host->ioaddr + reg); 323 } 324 325 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 326 { 327 writeb(val, host->ioaddr + reg); 328 } 329 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 330 { 331 return readl(host->ioaddr + reg); 332 } 333 334 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 335 { 336 return readw(host->ioaddr + reg); 337 } 338 339 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 340 { 341 return readb(host->ioaddr + reg); 342 } 343 #endif 344 345 #ifdef CONFIG_BLK 346 /** 347 * sdhci_setup_cfg() - Set up the configuration for DWMMC 348 * 349 * This is used to set up an SDHCI device when you are using CONFIG_BLK. 350 * 351 * This should be called from your MMC driver's probe() method once you have 352 * the information required. 353 * 354 * Generally your driver will have a platform data structure which holds both 355 * the configuration (struct mmc_config) and the MMC device info (struct mmc). 356 * For example: 357 * 358 * struct msm_sdhc_plat { 359 * struct mmc_config cfg; 360 * struct mmc mmc; 361 * }; 362 * 363 * ... 364 * 365 * Inside U_BOOT_DRIVER(): 366 * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat), 367 * 368 * To access platform data: 369 * struct msm_sdhc_plat *plat = dev_get_platdata(dev); 370 * 371 * See msm_sdhci.c for an example. 372 * 373 * @cfg: Configuration structure to fill in (generally &plat->mmc) 374 * @host: SDHCI host structure 375 * @max_clk: Maximum supported clock speed in HZ (0 for default) 376 * @min_clk: Minimum supported clock speed in HZ (0 for default) 377 */ 378 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, 379 u32 max_clk, u32 min_clk); 380 381 /** 382 * sdhci_bind() - Set up a new MMC block device 383 * 384 * This is used to set up an SDHCI block device when you are using CONFIG_BLK. 385 * It should be called from your driver's bind() method. 386 * 387 * See msm_sdhci.c for an example. 388 * 389 * @dev: Device to set up 390 * @mmc: Pointer to mmc structure (normally &plat->mmc) 391 * @cfg: Empty configuration structure (generally &plat->cfg). This is 392 * normally all zeroes at this point. The only purpose of passing 393 * this in is to set mmc->cfg to it. 394 * @return 0 if OK, -ve if the block device could not be created 395 */ 396 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); 397 #else 398 399 /** 400 * add_sdhci() - Add a new SDHCI interface 401 * 402 * This is used when you are not using CONFIG_BLK. Convert your driver over! 403 * 404 * @host: SDHCI host structure 405 * @max_clk: Maximum supported clock speed in HZ (0 for default) 406 * @min_clk: Minimum supported clock speed in HZ (0 for default) 407 * @return 0 if OK, -ve on error 408 */ 409 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk); 410 #endif /* !CONFIG_BLK */ 411 412 #ifdef CONFIG_DM_MMC_OPS 413 /* Export the operations to drivers */ 414 int sdhci_probe(struct udevice *dev); 415 extern const struct dm_mmc_ops sdhci_ops; 416 #else 417 #endif 418 419 #endif /* __SDHCI_HW_H */ 420