1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 * Back ported to the 8xx platform (from the 8260 platform) by 24 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 25 */ 26 #ifndef __SDHCI_HW_H 27 #define __SDHCI_HW_H 28 29 #include <asm/io.h> 30 #include <mmc.h> 31 32 /* 33 * Controller registers 34 */ 35 36 #define SDHCI_DMA_ADDRESS 0x00 37 38 #define SDHCI_BLOCK_SIZE 0x04 39 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 40 41 #define SDHCI_BLOCK_COUNT 0x06 42 43 #define SDHCI_ARGUMENT 0x08 44 45 #define SDHCI_TRANSFER_MODE 0x0C 46 #define SDHCI_TRNS_DMA 0x01 47 #define SDHCI_TRNS_BLK_CNT_EN 0x02 48 #define SDHCI_TRNS_ACMD12 0x04 49 #define SDHCI_TRNS_READ 0x10 50 #define SDHCI_TRNS_MULTI 0x20 51 52 #define SDHCI_COMMAND 0x0E 53 #define SDHCI_CMD_RESP_MASK 0x03 54 #define SDHCI_CMD_CRC 0x08 55 #define SDHCI_CMD_INDEX 0x10 56 #define SDHCI_CMD_DATA 0x20 57 #define SDHCI_CMD_ABORTCMD 0xC0 58 59 #define SDHCI_CMD_RESP_NONE 0x00 60 #define SDHCI_CMD_RESP_LONG 0x01 61 #define SDHCI_CMD_RESP_SHORT 0x02 62 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 63 64 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 65 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 66 67 #define SDHCI_RESPONSE 0x10 68 69 #define SDHCI_BUFFER 0x20 70 71 #define SDHCI_PRESENT_STATE 0x24 72 #define SDHCI_CMD_INHIBIT 0x00000001 73 #define SDHCI_DATA_INHIBIT 0x00000002 74 #define SDHCI_DOING_WRITE 0x00000100 75 #define SDHCI_DOING_READ 0x00000200 76 #define SDHCI_SPACE_AVAILABLE 0x00000400 77 #define SDHCI_DATA_AVAILABLE 0x00000800 78 #define SDHCI_CARD_PRESENT 0x00010000 79 #define SDHCI_CARD_STATE_STABLE 0x00020000 80 #define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000 81 #define SDHCI_WRITE_PROTECT 0x00080000 82 83 #define SDHCI_HOST_CONTROL 0x28 84 #define SDHCI_CTRL_LED 0x01 85 #define SDHCI_CTRL_4BITBUS 0x02 86 #define SDHCI_CTRL_HISPD 0x04 87 #define SDHCI_CTRL_DMA_MASK 0x18 88 #define SDHCI_CTRL_SDMA 0x00 89 #define SDHCI_CTRL_ADMA1 0x08 90 #define SDHCI_CTRL_ADMA32 0x10 91 #define SDHCI_CTRL_ADMA64 0x18 92 #define SDHCI_CTRL_8BITBUS 0x20 93 #define SDHCI_CTRL_CD_TEST_INS 0x40 94 #define SDHCI_CTRL_CD_TEST 0x80 95 96 #define SDHCI_POWER_CONTROL 0x29 97 #define SDHCI_POWER_ON 0x01 98 #define SDHCI_POWER_180 0x0A 99 #define SDHCI_POWER_300 0x0C 100 #define SDHCI_POWER_330 0x0E 101 102 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 103 104 #define SDHCI_WAKE_UP_CONTROL 0x2B 105 #define SDHCI_WAKE_ON_INT 0x01 106 #define SDHCI_WAKE_ON_INSERT 0x02 107 #define SDHCI_WAKE_ON_REMOVE 0x04 108 109 #define SDHCI_CLOCK_CONTROL 0x2C 110 #define SDHCI_DIVIDER_SHIFT 8 111 #define SDHCI_DIVIDER_HI_SHIFT 6 112 #define SDHCI_DIV_MASK 0xFF 113 #define SDHCI_DIV_MASK_LEN 8 114 #define SDHCI_DIV_HI_MASK 0x300 115 #define SDHCI_CLOCK_CARD_EN 0x0004 116 #define SDHCI_CLOCK_INT_STABLE 0x0002 117 #define SDHCI_CLOCK_INT_EN 0x0001 118 119 #define SDHCI_TIMEOUT_CONTROL 0x2E 120 121 #define SDHCI_SOFTWARE_RESET 0x2F 122 #define SDHCI_RESET_ALL 0x01 123 #define SDHCI_RESET_CMD 0x02 124 #define SDHCI_RESET_DATA 0x04 125 126 #define SDHCI_INT_STATUS 0x30 127 #define SDHCI_INT_ENABLE 0x34 128 #define SDHCI_SIGNAL_ENABLE 0x38 129 #define SDHCI_INT_RESPONSE 0x00000001 130 #define SDHCI_INT_DATA_END 0x00000002 131 #define SDHCI_INT_DMA_END 0x00000008 132 #define SDHCI_INT_SPACE_AVAIL 0x00000010 133 #define SDHCI_INT_DATA_AVAIL 0x00000020 134 #define SDHCI_INT_CARD_INSERT 0x00000040 135 #define SDHCI_INT_CARD_REMOVE 0x00000080 136 #define SDHCI_INT_CARD_INT 0x00000100 137 #define SDHCI_INT_ERROR 0x00008000 138 #define SDHCI_INT_TIMEOUT 0x00010000 139 #define SDHCI_INT_CRC 0x00020000 140 #define SDHCI_INT_END_BIT 0x00040000 141 #define SDHCI_INT_INDEX 0x00080000 142 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 143 #define SDHCI_INT_DATA_CRC 0x00200000 144 #define SDHCI_INT_DATA_END_BIT 0x00400000 145 #define SDHCI_INT_BUS_POWER 0x00800000 146 #define SDHCI_INT_ACMD12ERR 0x01000000 147 #define SDHCI_INT_ADMA_ERROR 0x02000000 148 149 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 150 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 151 152 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 153 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 154 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 155 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 156 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 157 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) 158 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 159 160 #define SDHCI_ACMD12_ERR 0x3C 161 162 /* 3E-3F reserved */ 163 164 #define SDHCI_CAPABILITIES 0x40 165 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 166 #define SDHCI_TIMEOUT_CLK_SHIFT 0 167 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 168 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 169 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 170 #define SDHCI_CLOCK_BASE_SHIFT 8 171 #define SDHCI_MAX_BLOCK_MASK 0x00030000 172 #define SDHCI_MAX_BLOCK_SHIFT 16 173 #define SDHCI_CAN_DO_8BIT 0x00040000 174 #define SDHCI_CAN_DO_ADMA2 0x00080000 175 #define SDHCI_CAN_DO_ADMA1 0x00100000 176 #define SDHCI_CAN_DO_HISPD 0x00200000 177 #define SDHCI_CAN_DO_SDMA 0x00400000 178 #define SDHCI_CAN_VDD_330 0x01000000 179 #define SDHCI_CAN_VDD_300 0x02000000 180 #define SDHCI_CAN_VDD_180 0x04000000 181 #define SDHCI_CAN_64BIT 0x10000000 182 183 #define SDHCI_CAPABILITIES_1 0x44 184 185 #define SDHCI_MAX_CURRENT 0x48 186 187 /* 4C-4F reserved for more max current */ 188 189 #define SDHCI_SET_ACMD12_ERROR 0x50 190 #define SDHCI_SET_INT_ERROR 0x52 191 192 #define SDHCI_ADMA_ERROR 0x54 193 194 /* 55-57 reserved */ 195 196 #define SDHCI_ADMA_ADDRESS 0x58 197 198 /* 60-FB reserved */ 199 200 #define SDHCI_SLOT_INT_STATUS 0xFC 201 202 #define SDHCI_HOST_VERSION 0xFE 203 #define SDHCI_VENDOR_VER_MASK 0xFF00 204 #define SDHCI_VENDOR_VER_SHIFT 8 205 #define SDHCI_SPEC_VER_MASK 0x00FF 206 #define SDHCI_SPEC_VER_SHIFT 0 207 #define SDHCI_SPEC_100 0 208 #define SDHCI_SPEC_200 1 209 #define SDHCI_SPEC_300 2 210 211 /* 212 * End of controller registers. 213 */ 214 215 #define SDHCI_MAX_DIV_SPEC_200 256 216 #define SDHCI_MAX_DIV_SPEC_300 2046 217 218 /* 219 * quirks 220 */ 221 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) 222 #define SDHCI_QUIRK_REG32_RW (1 << 1) 223 #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) 224 #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) 225 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) 226 #define SDHCI_QUIRK_NO_CD (1 << 5) 227 228 /* to make gcc happy */ 229 struct sdhci_host; 230 231 /* 232 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 233 */ 234 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 235 #define SDHCI_DEFAULT_BOUNDARY_ARG (7) 236 struct sdhci_ops { 237 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 238 u32 (*read_l)(struct sdhci_host *host, int reg); 239 u16 (*read_w)(struct sdhci_host *host, int reg); 240 u8 (*read_b)(struct sdhci_host *host, int reg); 241 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 242 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 243 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 244 #endif 245 }; 246 247 struct sdhci_host { 248 char *name; 249 void *ioaddr; 250 unsigned int quirks; 251 unsigned int host_caps; 252 unsigned int version; 253 unsigned int clock; 254 struct mmc *mmc; 255 const struct sdhci_ops *ops; 256 int index; 257 258 void (*set_control_reg)(struct sdhci_host *host); 259 void (*set_clock)(int dev_index, unsigned int div); 260 uint voltages; 261 }; 262 263 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 264 265 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 266 { 267 if (unlikely(host->ops->write_l)) 268 host->ops->write_l(host, val, reg); 269 else 270 writel(val, host->ioaddr + reg); 271 } 272 273 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 274 { 275 if (unlikely(host->ops->write_w)) 276 host->ops->write_w(host, val, reg); 277 else 278 writew(val, host->ioaddr + reg); 279 } 280 281 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 282 { 283 if (unlikely(host->ops->write_b)) 284 host->ops->write_b(host, val, reg); 285 else 286 writeb(val, host->ioaddr + reg); 287 } 288 289 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 290 { 291 if (unlikely(host->ops->read_l)) 292 return host->ops->read_l(host, reg); 293 else 294 return readl(host->ioaddr + reg); 295 } 296 297 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 298 { 299 if (unlikely(host->ops->read_w)) 300 return host->ops->read_w(host, reg); 301 else 302 return readw(host->ioaddr + reg); 303 } 304 305 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 306 { 307 if (unlikely(host->ops->read_b)) 308 return host->ops->read_b(host, reg); 309 else 310 return readb(host->ioaddr + reg); 311 } 312 313 #else 314 315 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 316 { 317 writel(val, host->ioaddr + reg); 318 } 319 320 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 321 { 322 writew(val, host->ioaddr + reg); 323 } 324 325 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 326 { 327 writeb(val, host->ioaddr + reg); 328 } 329 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 330 { 331 return readl(host->ioaddr + reg); 332 } 333 334 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 335 { 336 return readw(host->ioaddr + reg); 337 } 338 339 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 340 { 341 return readb(host->ioaddr + reg); 342 } 343 #endif 344 345 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk); 346 #endif /* __SDHCI_HW_H */ 347