xref: /openbmc/u-boot/include/exynos_lcd.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * exynos_lcd.h - Exynos LCD Controller structures
4  *
5  * (C) Copyright 2001
6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7  */
8 
9 #ifndef _EXYNOS_LCD_H_
10 #define _EXYNOS_LCD_H_
11 
12 enum {
13 	FIMD_RGB_INTERFACE = 1,
14 	FIMD_CPU_INTERFACE = 2,
15 };
16 
17 enum exynos_fb_rgb_mode_t {
18 	MODE_RGB_P = 0,
19 	MODE_BGR_P = 1,
20 	MODE_RGB_S = 2,
21 	MODE_BGR_S = 3,
22 };
23 
24 typedef struct vidinfo {
25 	ushort vl_col;		/* Number of columns (i.e. 640) */
26 	ushort vl_row;		/* Number of rows (i.e. 480) */
27 	ushort vl_rot;		/* Rotation of Display (0, 1, 2, 3) */
28 	ushort vl_width;	/* Width of display area in millimeters */
29 	ushort vl_height;	/* Height of display area in millimeters */
30 
31 	/* LCD configuration register */
32 	u_char vl_freq;		/* Frequency */
33 	u_char vl_clkp;		/* Clock polarity */
34 	u_char vl_oep;		/* Output Enable polarity */
35 	u_char vl_hsp;		/* Horizontal Sync polarity */
36 	u_char vl_vsp;		/* Vertical Sync polarity */
37 	u_char vl_dp;		/* Data polarity */
38 	u_char vl_bpix;		/* Bits per pixel */
39 
40 	/* Horizontal control register. Timing from data sheet */
41 	u_char vl_hspw;		/* Horz sync pulse width */
42 	u_char vl_hfpd;		/* Wait before of line */
43 	u_char vl_hbpd;		/* Wait end of line */
44 
45 	/* Vertical control register. */
46 	u_char	vl_vspw;	/* Vertical sync pulse width */
47 	u_char	vl_vfpd;	/* Wait before of frame */
48 	u_char	vl_vbpd;	/* Wait end of frame */
49 	u_char  vl_cmd_allow_len; /* Wait end of frame */
50 
51 	unsigned int win_id;
52 	unsigned int init_delay;
53 	unsigned int power_on_delay;
54 	unsigned int reset_delay;
55 	unsigned int interface_mode;
56 	unsigned int mipi_enabled;
57 	unsigned int dp_enabled;
58 	unsigned int cs_setup;
59 	unsigned int wr_setup;
60 	unsigned int wr_act;
61 	unsigned int wr_hold;
62 	unsigned int logo_on;
63 	unsigned int logo_width;
64 	unsigned int logo_height;
65 	int logo_x_offset;
66 	int logo_y_offset;
67 	unsigned long logo_addr;
68 	unsigned int rgb_mode;
69 	unsigned int resolution;
70 
71 	/* parent clock name(MPLL, EPLL or VPLL) */
72 	unsigned int pclk_name;
73 	/* ratio value for source clock from parent clock. */
74 	unsigned int sclk_div;
75 
76 	unsigned int dual_lcd_enabled;
77 	struct exynos_fb *reg;
78 	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
79 } vidinfo_t;
80 
81 #endif
82