1 /*
2  * (C) Copyright 2015
3  * (C) Copyright 2014
4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5  *
6  * Based on:
7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
8  *
9  * Configuration settings for the Freescale i.MX6Q SabreSD board.
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 #ifndef __ARISTAINETOS_COMMON_CONFIG_H
14 #define __ARISTAINETOS_COMMON_CONFIG_H
15 
16 #include "mx6_common.h"
17 
18 #define CONFIG_MACH_TYPE	4501
19 #define CONFIG_MMCROOT		"/dev/mmcblk0p1"
20 #define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
21 
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN		(64 * SZ_1M)
24 
25 #define CONFIG_BOARD_EARLY_INIT_F
26 
27 #define CONFIG_MXC_UART
28 
29 /* MMC Configs */
30 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
31 
32 #define CONFIG_CMD_PING
33 #define CONFIG_CMD_DHCP
34 #define CONFIG_CMD_MII
35 #define CONFIG_FEC_MXC
36 #define CONFIG_MII
37 #define IMX_FEC_BASE			ENET_BASE_ADDR
38 #define CONFIG_ETHPRIME			"FEC"
39 #define CONFIG_FEC_MXC_PHYADDR		0
40 
41 #define CONFIG_PHYLIB
42 #define CONFIG_PHY_MICREL
43 
44 #define CONFIG_CMD_SF
45 #define CONFIG_SPI_FLASH_MTD
46 #define CONFIG_SPI_FLASH_STMICRO
47 #define CONFIG_MXC_SPI
48 #define CONFIG_SF_DEFAULT_SPEED		20000000
49 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
50 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
51 
52 /* Command definition */
53 #define CONFIG_CMD_BMODE
54 
55 #define CONFIG_EXTRA_ENV_SETTINGS \
56 	"script=u-boot.scr\0" \
57 	"fit_file=/boot/system.itb\0" \
58 	"loadaddr=0x12000000\0" \
59 	"fit_addr_r=0x14000000\0" \
60 	"uboot=/boot/u-boot.imx\0" \
61 	"uboot_sz=d0000\0" \
62 	"rescue_sys_addr=f0000\0" \
63 	"rescue_sys_length=f10000\0" \
64 	"panel=lb07wv8\0" \
65 	"splashpos=m,m\0" \
66 	"console=" CONFIG_CONSOLE_DEV "\0" \
67 	"fdt_high=0xffffffff\0"	  \
68 	"initrd_high=0xffffffff\0" \
69 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
70 	"set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
71 		"default ${board_type}\0" \
72 	"get_env=mw ${loadaddr} 0 0x20000;" \
73 		"mmc rescan;" \
74 		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
75 		"env import -t ${loadaddr}\0" \
76 	"default_env=mw ${loadaddr} 0 0x20000;" \
77 		"env export -t ${loadaddr} serial# ethaddr eth1addr " \
78 		"board_type panel;" \
79 		"env default -a;" \
80 		"env import -t ${loadaddr}\0" \
81 	"loadbootscript=" \
82 		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
83 	"bootscript=echo Running bootscript from mmc ...; " \
84 		"source\0" \
85 	"mmcpart=1\0" \
86 	"mmcdev=0\0" \
87 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
88 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
89 		"root=${mmcroot}\0" \
90 	"mmcboot=echo Booting from mmc ...; " \
91 		"run mmcargs addmtd addmisc set_fit_default;" \
92 		"bootm ${fit_addr_r}\0" \
93 	"mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
94 		"${fit_file}\0" \
95 	"mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
96 		"${uboot}\0" \
97 	"mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
98 		"setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
99 		"setexpr uboot_maxsize ${uboot_sz} - 400;" \
100 		"mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
101 		"run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
102 		"sf write ${loadaddr} 400 ${filesize};" \
103 		"sf read ${cmp_buf} 400 ${uboot_sz};" \
104 		"cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
105 	"ubiboot=echo Booting from ubi ...; " \
106 		"run ubiargs addmtd addmisc set_fit_default;" \
107 		"bootm ${fit_addr_r}\0" \
108 	"rescueargs=setenv bootargs console=${console},${baudrate} " \
109 		"root=/dev/ram rw\0 " \
110 	"rescueboot=echo Booting rescue system from NOR ...; " \
111 		"run rescueargs addmtd addmisc set_fit_default;" \
112 		"bootm ${fit_addr_r}\0" \
113 	"rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
114 		"${rescue_sys_length}; imi ${fit_addr_r}\0" \
115 	CONFIG_EXTRA_ENV_BOARD_SETTINGS
116 
117 #define CONFIG_BOOTCOMMAND \
118 	"mmc dev ${mmcdev};" \
119 	"if mmc rescan; then " \
120 		"if run loadbootscript; then " \
121 			"run bootscript; " \
122 		"else " \
123 			"if run mmc_load_fit; then " \
124 				"run mmcboot; " \
125 			"else " \
126 				"if run ubifs_load_fit; then " \
127 					"run ubiboot; " \
128 				"else " \
129 					"if run rescue_load_fit; then " \
130 						"run rescueboot; " \
131 					"else " \
132 						"echo RESCUE SYSTEM BOOT " \
133 							"FAILURE;" \
134 					"fi; " \
135 				"fi; " \
136 			"fi; " \
137 		"fi; " \
138 	"else " \
139 		"if run ubifs_load_fit; then " \
140 			"run ubiboot; " \
141 		"else " \
142 			"if run rescue_load_fit; then " \
143 				"run rescueboot; " \
144 			"else " \
145 				"echo RESCUE SYSTEM BOOT FAILURE;" \
146 			"fi; " \
147 		"fi; " \
148 	"fi"
149 
150 #define CONFIG_ARP_TIMEOUT		200UL
151 
152 /* Print Buffer Size */
153 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
154 
155 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
156 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
157 #define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
158 
159 #define CONFIG_STACKSIZE		(128 * 1024)
160 
161 /* Physical Memory Map */
162 #define CONFIG_NR_DRAM_BANKS		1
163 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
164 
165 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
166 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
167 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
168 
169 #define CONFIG_SYS_INIT_SP_OFFSET \
170 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
171 #define CONFIG_SYS_INIT_SP_ADDR \
172 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
173 
174 /* Environment organization */
175 #define CONFIG_ENV_SIZE			(12 * 1024)
176 #define CONFIG_ENV_IS_IN_SPI_FLASH
177 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
178 #define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
179 #define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
180 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
181 #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
182 #define CONFIG_ENV_SECT_SIZE		(0x010000)
183 #define CONFIG_ENV_OFFSET		(0x0d0000)
184 #define CONFIG_ENV_OFFSET_REDUND	(0x0e0000)
185 
186 #define CONFIG_SYS_FSL_USDHC_NUM	2
187 
188 /* I2C */
189 #define CONFIG_CMD_I2C
190 #define CONFIG_SYS_I2C
191 #define CONFIG_SYS_I2C_MXC
192 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
193 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
194 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
195 #define CONFIG_SYS_I2C_SPEED		100000
196 #define CONFIG_SYS_I2C_SLAVE		0x7f
197 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x00} }
198 
199 /* NAND stuff */
200 #define CONFIG_CMD_NAND
201 #define CONFIG_CMD_NAND_TRIMFFS
202 #define CONFIG_NAND_MXS
203 #define CONFIG_SYS_MAX_NAND_DEVICE	1
204 #define CONFIG_SYS_NAND_BASE		0x40000000
205 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
206 #define CONFIG_SYS_NAND_ONFI_DETECTION
207 
208 /* DMA stuff, needed for GPMI/MXS NAND support */
209 #define CONFIG_APBH_DMA
210 #define CONFIG_APBH_DMA_BURST
211 #define CONFIG_APBH_DMA_BURST8
212 
213 /* RTC */
214 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
215 #define CONFIG_SYS_RTC_BUS_NUM	2
216 #define CONFIG_RTC_M41T11
217 #define CONFIG_CMD_DATE
218 
219 /* USB Configs */
220 #define CONFIG_CMD_USB
221 #define CONFIG_USB_EHCI
222 #define CONFIG_USB_EHCI_MX6
223 #define CONFIG_USB_STORAGE
224 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
225 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
226 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
227 #define CONFIG_MXC_USB_FLAGS	0
228 
229 /* UBI support */
230 #define CONFIG_LZO
231 #define CONFIG_CMD_MTDPARTS
232 #define CONFIG_MTD_PARTITIONS
233 #define CONFIG_MTD_DEVICE
234 #define CONFIG_RBTREE
235 #define CONFIG_CMD_UBI
236 #define CONFIG_CMD_UBIFS
237 
238 #define CONFIG_MTD_UBI_FASTMAP
239 #define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT	1
240 
241 #define CONFIG_HW_WATCHDOG
242 #define CONFIG_IMX_WATCHDOG
243 
244 #define CONFIG_FIT
245 
246 /* Framebuffer */
247 #define CONFIG_VIDEO
248 #define CONFIG_VIDEO_IPUV3
249 /* check this console not needed, after test remove it */
250 #define CONFIG_CFB_CONSOLE
251 #define CONFIG_VGA_AS_SINGLE_DEVICE
252 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
253 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
254 #define CONFIG_VIDEO_BMP_RLE8
255 #define CONFIG_SPLASH_SCREEN
256 #define CONFIG_SPLASH_SCREEN_ALIGN
257 #define CONFIG_BMP_16BPP
258 #define CONFIG_VIDEO_LOGO
259 #define CONFIG_VIDEO_BMP_LOGO
260 #define CONFIG_IPUV3_CLK 198000000
261 #define CONFIG_IMX_VIDEO_SKIP
262 
263 #define CONFIG_CMD_BMP
264 
265 #define CONFIG_PWM_IMX
266 #define CONFIG_IMX6_PWM_PER_CLK	66000000
267 
268 #endif /* __ARISTAINETOS_COMMON_CONFIG_H */
269