1 /* 2 * (C) Copyright 2015 3 * (C) Copyright 2014 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 * 6 * Based on: 7 * Copyright (C) 2012 Freescale Semiconductor, Inc. 8 * 9 * Configuration settings for the Freescale i.MX6Q SabreSD board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #ifndef __ARISTAINETOS_COMMON_CONFIG_H 14 #define __ARISTAINETOS_COMMON_CONFIG_H 15 16 #include "mx6_common.h" 17 18 #define CONFIG_MACH_TYPE 4501 19 #define CONFIG_MMCROOT "/dev/mmcblk0p1" 20 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 21 22 /* Size of malloc() pool */ 23 #define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) 24 25 #define CONFIG_BOARD_EARLY_INIT_F 26 27 #define CONFIG_MXC_UART 28 29 #define CONFIG_CMD_FUSE 30 #define CONFIG_MXC_OCOTP 31 32 /* MMC Configs */ 33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 34 35 #define CONFIG_CMD_PING 36 #define CONFIG_CMD_DHCP 37 #define CONFIG_CMD_MII 38 #define CONFIG_FEC_MXC 39 #define CONFIG_MII 40 #define IMX_FEC_BASE ENET_BASE_ADDR 41 #define CONFIG_ETHPRIME "FEC" 42 #define CONFIG_FEC_MXC_PHYADDR 0 43 44 #define CONFIG_PHYLIB 45 #define CONFIG_PHY_MICREL 46 47 #define CONFIG_CMD_SF 48 #define CONFIG_SPI_FLASH_MTD 49 #define CONFIG_SPI_FLASH_STMICRO 50 #define CONFIG_MXC_SPI 51 #define CONFIG_SF_DEFAULT_BUS 3 52 #define CONFIG_SF_DEFAULT_SPEED 20000000 53 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 54 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN 55 56 /* Command definition */ 57 #define CONFIG_CMD_BMODE 58 59 #define CONFIG_EXTRA_ENV_SETTINGS \ 60 "script=u-boot.scr\0" \ 61 "fit_file=/boot/system.itb\0" \ 62 "loadaddr=0x12000000\0" \ 63 "fit_addr_r=0x14000000\0" \ 64 "uboot=/boot/u-boot.imx\0" \ 65 "uboot_sz=d0000\0" \ 66 "rescue_sys_addr=f0000\0" \ 67 "rescue_sys_length=f10000\0" \ 68 "panel=lb07wv8\0" \ 69 "splashpos=m,m\0" \ 70 "console=" CONFIG_CONSOLE_DEV "\0" \ 71 "fdt_high=0xffffffff\0" \ 72 "initrd_high=0xffffffff\0" \ 73 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 74 "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ 75 "default ${board_type}\0" \ 76 "get_env=mw ${loadaddr} 0 0x20000;" \ 77 "mmc rescan;" \ 78 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ 79 "env import -t ${loadaddr}\0" \ 80 "default_env=mw ${loadaddr} 0 0x20000;" \ 81 "env export -t ${loadaddr} serial# ethaddr eth1addr " \ 82 "board_type panel;" \ 83 "env default -a;" \ 84 "env import -t ${loadaddr}\0" \ 85 "loadbootscript=" \ 86 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 87 "bootscript=echo Running bootscript from mmc ...; " \ 88 "source\0" \ 89 "mmcpart=1\0" \ 90 "mmcdev=0\0" \ 91 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 92 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 93 "root=${mmcroot}\0" \ 94 "mmcboot=echo Booting from mmc ...; " \ 95 "run mmcargs addmtd addmisc set_fit_default;" \ 96 "bootm ${fit_addr_r}\0" \ 97 "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ 98 "${fit_file}\0" \ 99 "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ 100 "${uboot}\0" \ 101 "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ 102 "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ 103 "setexpr uboot_maxsize ${uboot_sz} - 400;" \ 104 "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ 105 "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ 106 "sf write ${loadaddr} 400 ${filesize};" \ 107 "sf read ${cmp_buf} 400 ${uboot_sz};" \ 108 "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ 109 "ubiboot=echo Booting from ubi ...; " \ 110 "run ubiargs addmtd addmisc set_fit_default;" \ 111 "bootm ${fit_addr_r}\0" \ 112 "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \ 113 "ubifsload ${fit_addr_r} /boot/system.itb; " \ 114 "imi ${fit_addr_r}\0 " \ 115 "rescueargs=setenv bootargs console=${console},${baudrate} " \ 116 "root=/dev/ram rw\0 " \ 117 "rescueboot=echo Booting rescue system from NOR ...; " \ 118 "run rescueargs addmtd addmisc set_fit_default;" \ 119 "bootm ${fit_addr_r}\0" \ 120 "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ 121 "${rescue_sys_length}; imi ${fit_addr_r}\0" \ 122 CONFIG_EXTRA_ENV_BOARD_SETTINGS 123 124 #define CONFIG_BOOTCOMMAND \ 125 "mmc dev ${mmcdev};" \ 126 "if mmc rescan; then " \ 127 "if run loadbootscript; then " \ 128 "run bootscript; " \ 129 "else " \ 130 "if run mmc_load_fit; then " \ 131 "run mmcboot; " \ 132 "else " \ 133 "if run ubifs_load_fit; then " \ 134 "run ubiboot; " \ 135 "else " \ 136 "if run rescue_load_fit; then " \ 137 "run rescueboot; " \ 138 "else " \ 139 "echo RESCUE SYSTEM BOOT " \ 140 "FAILURE;" \ 141 "fi; " \ 142 "fi; " \ 143 "fi; " \ 144 "fi; " \ 145 "else " \ 146 "if run ubifs_load_fit; then " \ 147 "run ubiboot; " \ 148 "else " \ 149 "if run rescue_load_fit; then " \ 150 "run rescueboot; " \ 151 "else " \ 152 "echo RESCUE SYSTEM BOOT FAILURE;" \ 153 "fi; " \ 154 "fi; " \ 155 "fi" 156 157 #define CONFIG_ARP_TIMEOUT 200UL 158 159 /* Print Buffer Size */ 160 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 161 162 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 163 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) 164 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 165 166 #define CONFIG_STACKSIZE (128 * 1024) 167 168 /* Physical Memory Map */ 169 #define CONFIG_NR_DRAM_BANKS 1 170 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 171 172 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 173 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 174 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 175 176 #define CONFIG_SYS_INIT_SP_OFFSET \ 177 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 178 #define CONFIG_SYS_INIT_SP_ADDR \ 179 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 180 181 /* Environment organization */ 182 #define CONFIG_ENV_SIZE (12 * 1024) 183 #define CONFIG_ENV_IS_IN_SPI_FLASH 184 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 185 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 186 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 187 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 188 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 189 #define CONFIG_ENV_SECT_SIZE (0x010000) 190 #define CONFIG_ENV_OFFSET (0x0d0000) 191 #define CONFIG_ENV_OFFSET_REDUND (0x0e0000) 192 193 #define CONFIG_SYS_FSL_USDHC_NUM 2 194 195 /* I2C */ 196 #define CONFIG_CMD_I2C 197 #define CONFIG_SYS_I2C 198 #define CONFIG_SYS_I2C_MXC 199 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 200 #define CONFIG_SYS_I2C_SPEED 100000 201 #define CONFIG_SYS_I2C_SLAVE 0x7f 202 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } 203 204 /* NAND stuff */ 205 #define CONFIG_CMD_NAND 206 #define CONFIG_CMD_NAND_TRIMFFS 207 #define CONFIG_NAND_MXS 208 #define CONFIG_SYS_MAX_NAND_DEVICE 1 209 #define CONFIG_SYS_NAND_BASE 0x40000000 210 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 211 #define CONFIG_SYS_NAND_ONFI_DETECTION 212 213 /* DMA stuff, needed for GPMI/MXS NAND support */ 214 #define CONFIG_APBH_DMA 215 #define CONFIG_APBH_DMA_BURST 216 #define CONFIG_APBH_DMA_BURST8 217 218 /* RTC */ 219 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 220 #define CONFIG_SYS_RTC_BUS_NUM 2 221 #define CONFIG_RTC_M41T11 222 #define CONFIG_CMD_DATE 223 224 /* USB Configs */ 225 #define CONFIG_CMD_USB 226 #define CONFIG_USB_EHCI 227 #define CONFIG_USB_EHCI_MX6 228 #define CONFIG_USB_STORAGE 229 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 230 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 231 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 232 #define CONFIG_MXC_USB_FLAGS 0 233 234 /* UBI support */ 235 #define CONFIG_LZO 236 #define CONFIG_CMD_MTDPARTS 237 #define CONFIG_MTD_PARTITIONS 238 #define CONFIG_MTD_DEVICE 239 #define CONFIG_RBTREE 240 #define CONFIG_CMD_UBI 241 #define CONFIG_CMD_UBIFS 242 243 #define CONFIG_MTD_UBI_FASTMAP 244 #define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1 245 246 #define CONFIG_HW_WATCHDOG 247 #define CONFIG_IMX_WATCHDOG 248 249 #define CONFIG_FIT 250 251 /* Framebuffer */ 252 #define CONFIG_VIDEO 253 #define CONFIG_VIDEO_IPUV3 254 /* check this console not needed, after test remove it */ 255 #define CONFIG_CFB_CONSOLE 256 #define CONFIG_VGA_AS_SINGLE_DEVICE 257 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 258 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 259 #define CONFIG_VIDEO_BMP_RLE8 260 #define CONFIG_SPLASH_SCREEN 261 #define CONFIG_SPLASH_SCREEN_ALIGN 262 #define CONFIG_BMP_16BPP 263 #define CONFIG_VIDEO_LOGO 264 #define CONFIG_VIDEO_BMP_LOGO 265 #define CONFIG_IPUV3_CLK 198000000 266 #define CONFIG_IMX_VIDEO_SKIP 267 268 #define CONFIG_CMD_BMP 269 270 #define CONFIG_PWM_IMX 271 #define CONFIG_IMX6_PWM_PER_CLK 66000000 272 273 #endif /* __ARISTAINETOS_COMMON_CONFIG_H */ 274