1*4782ac80SJin Zhengxiong /* 2*4782ac80SJin Zhengxiong * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 3*4782ac80SJin Zhengxiong * Author: Jason Jin<Jason.jin@freescale.com> 4*4782ac80SJin Zhengxiong * Zhang Wei<wei.zhang@freescale.com> 5*4782ac80SJin Zhengxiong * 6*4782ac80SJin Zhengxiong * See file CREDITS for list of people who contributed to this 7*4782ac80SJin Zhengxiong * project. 8*4782ac80SJin Zhengxiong * 9*4782ac80SJin Zhengxiong * This program is free software; you can redistribute it and/or 10*4782ac80SJin Zhengxiong * modify it under the terms of the GNU General Public License as 11*4782ac80SJin Zhengxiong * published by the Free Software Foundation; either version 2 of 12*4782ac80SJin Zhengxiong * the License, or (at your option) any later version. 13*4782ac80SJin Zhengxiong * 14*4782ac80SJin Zhengxiong * This program is distributed in the hope that it will be useful, 15*4782ac80SJin Zhengxiong * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4782ac80SJin Zhengxiong * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4782ac80SJin Zhengxiong * GNU General Public License for more details. 18*4782ac80SJin Zhengxiong * 19*4782ac80SJin Zhengxiong * You should have received a copy of the GNU General Public License 20*4782ac80SJin Zhengxiong * along with this program; if not, write to the Free Software 21*4782ac80SJin Zhengxiong * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*4782ac80SJin Zhengxiong * MA 02111-1307 USA 23*4782ac80SJin Zhengxiong * 24*4782ac80SJin Zhengxiong */ 25*4782ac80SJin Zhengxiong #ifndef _AHCI_H_ 26*4782ac80SJin Zhengxiong #define _AHCI_H_ 27*4782ac80SJin Zhengxiong 28*4782ac80SJin Zhengxiong #define AHCI_PCI_BAR 0x24 29*4782ac80SJin Zhengxiong #define AHCI_MAX_SG 56 /* hardware max is 64K */ 30*4782ac80SJin Zhengxiong #define AHCI_CMD_SLOT_SZ 32 31*4782ac80SJin Zhengxiong #define AHCI_RX_FIS_SZ 256 32*4782ac80SJin Zhengxiong #define AHCI_CMD_TBL_HDR 0x80 33*4782ac80SJin Zhengxiong #define AHCI_CMD_TBL_CDB 0x40 34*4782ac80SJin Zhengxiong #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) 35*4782ac80SJin Zhengxiong #define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ 36*4782ac80SJin Zhengxiong + AHCI_RX_FIS_SZ 37*4782ac80SJin Zhengxiong #define AHCI_CMD_ATAPI (1 << 5) 38*4782ac80SJin Zhengxiong #define AHCI_CMD_WRITE (1 << 6) 39*4782ac80SJin Zhengxiong #define AHCI_CMD_PREFETCH (1 << 7) 40*4782ac80SJin Zhengxiong #define AHCI_CMD_RESET (1 << 8) 41*4782ac80SJin Zhengxiong #define AHCI_CMD_CLR_BUSY (1 << 10) 42*4782ac80SJin Zhengxiong 43*4782ac80SJin Zhengxiong #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ 44*4782ac80SJin Zhengxiong 45*4782ac80SJin Zhengxiong /* Global controller registers */ 46*4782ac80SJin Zhengxiong #define HOST_CAP 0x00 /* host capabilities */ 47*4782ac80SJin Zhengxiong #define HOST_CTL 0x04 /* global host control */ 48*4782ac80SJin Zhengxiong #define HOST_IRQ_STAT 0x08 /* interrupt status */ 49*4782ac80SJin Zhengxiong #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ 50*4782ac80SJin Zhengxiong #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ 51*4782ac80SJin Zhengxiong 52*4782ac80SJin Zhengxiong /* HOST_CTL bits */ 53*4782ac80SJin Zhengxiong #define HOST_RESET (1 << 0) /* reset controller; self-clear */ 54*4782ac80SJin Zhengxiong #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ 55*4782ac80SJin Zhengxiong #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ 56*4782ac80SJin Zhengxiong 57*4782ac80SJin Zhengxiong /* Registers for each SATA port */ 58*4782ac80SJin Zhengxiong #define PORT_LST_ADDR 0x00 /* command list DMA addr */ 59*4782ac80SJin Zhengxiong #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ 60*4782ac80SJin Zhengxiong #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ 61*4782ac80SJin Zhengxiong #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ 62*4782ac80SJin Zhengxiong #define PORT_IRQ_STAT 0x10 /* interrupt status */ 63*4782ac80SJin Zhengxiong #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ 64*4782ac80SJin Zhengxiong #define PORT_CMD 0x18 /* port command */ 65*4782ac80SJin Zhengxiong #define PORT_TFDATA 0x20 /* taskfile data */ 66*4782ac80SJin Zhengxiong #define PORT_SIG 0x24 /* device TF signature */ 67*4782ac80SJin Zhengxiong #define PORT_CMD_ISSUE 0x38 /* command issue */ 68*4782ac80SJin Zhengxiong #define PORT_SCR 0x28 /* SATA phy register block */ 69*4782ac80SJin Zhengxiong #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ 70*4782ac80SJin Zhengxiong #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ 71*4782ac80SJin Zhengxiong #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ 72*4782ac80SJin Zhengxiong #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ 73*4782ac80SJin Zhengxiong 74*4782ac80SJin Zhengxiong /* PORT_IRQ_{STAT,MASK} bits */ 75*4782ac80SJin Zhengxiong #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ 76*4782ac80SJin Zhengxiong #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ 77*4782ac80SJin Zhengxiong #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ 78*4782ac80SJin Zhengxiong #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ 79*4782ac80SJin Zhengxiong #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ 80*4782ac80SJin Zhengxiong #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ 81*4782ac80SJin Zhengxiong #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ 82*4782ac80SJin Zhengxiong #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ 83*4782ac80SJin Zhengxiong 84*4782ac80SJin Zhengxiong #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ 85*4782ac80SJin Zhengxiong #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ 86*4782ac80SJin Zhengxiong #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ 87*4782ac80SJin Zhengxiong #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ 88*4782ac80SJin Zhengxiong #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ 89*4782ac80SJin Zhengxiong #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ 90*4782ac80SJin Zhengxiong #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ 91*4782ac80SJin Zhengxiong #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ 92*4782ac80SJin Zhengxiong #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ 93*4782ac80SJin Zhengxiong 94*4782ac80SJin Zhengxiong #define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ 95*4782ac80SJin Zhengxiong | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR 96*4782ac80SJin Zhengxiong 97*4782ac80SJin Zhengxiong #define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ 98*4782ac80SJin Zhengxiong | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ 99*4782ac80SJin Zhengxiong | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ 100*4782ac80SJin Zhengxiong | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ 101*4782ac80SJin Zhengxiong | PORT_IRQ_D2H_REG_FIS 102*4782ac80SJin Zhengxiong 103*4782ac80SJin Zhengxiong /* PORT_CMD bits */ 104*4782ac80SJin Zhengxiong #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ 105*4782ac80SJin Zhengxiong #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ 106*4782ac80SJin Zhengxiong #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ 107*4782ac80SJin Zhengxiong #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ 108*4782ac80SJin Zhengxiong #define PORT_CMD_CLO (1 << 3) /* Command list override */ 109*4782ac80SJin Zhengxiong #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ 110*4782ac80SJin Zhengxiong #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ 111*4782ac80SJin Zhengxiong #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ 112*4782ac80SJin Zhengxiong 113*4782ac80SJin Zhengxiong #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ 114*4782ac80SJin Zhengxiong #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ 115*4782ac80SJin Zhengxiong #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ 116*4782ac80SJin Zhengxiong 117*4782ac80SJin Zhengxiong #define AHCI_MAX_PORTS 32 118*4782ac80SJin Zhengxiong 119*4782ac80SJin Zhengxiong /* SETFEATURES stuff */ 120*4782ac80SJin Zhengxiong #define SETFEATURES_XFER 0x03 121*4782ac80SJin Zhengxiong #define XFER_UDMA_7 0x47 122*4782ac80SJin Zhengxiong #define XFER_UDMA_6 0x46 123*4782ac80SJin Zhengxiong #define XFER_UDMA_5 0x45 124*4782ac80SJin Zhengxiong #define XFER_UDMA_4 0x44 125*4782ac80SJin Zhengxiong #define XFER_UDMA_3 0x43 126*4782ac80SJin Zhengxiong #define XFER_UDMA_2 0x42 127*4782ac80SJin Zhengxiong #define XFER_UDMA_1 0x41 128*4782ac80SJin Zhengxiong #define XFER_UDMA_0 0x40 129*4782ac80SJin Zhengxiong #define XFER_MW_DMA_2 0x22 130*4782ac80SJin Zhengxiong #define XFER_MW_DMA_1 0x21 131*4782ac80SJin Zhengxiong #define XFER_MW_DMA_0 0x20 132*4782ac80SJin Zhengxiong #define XFER_SW_DMA_2 0x12 133*4782ac80SJin Zhengxiong #define XFER_SW_DMA_1 0x11 134*4782ac80SJin Zhengxiong #define XFER_SW_DMA_0 0x10 135*4782ac80SJin Zhengxiong #define XFER_PIO_4 0x0C 136*4782ac80SJin Zhengxiong #define XFER_PIO_3 0x0B 137*4782ac80SJin Zhengxiong #define XFER_PIO_2 0x0A 138*4782ac80SJin Zhengxiong #define XFER_PIO_1 0x09 139*4782ac80SJin Zhengxiong #define XFER_PIO_0 0x08 140*4782ac80SJin Zhengxiong #define XFER_PIO_SLOW 0x00 141*4782ac80SJin Zhengxiong 142*4782ac80SJin Zhengxiong #define ATA_FLAG_SATA (1 << 3) 143*4782ac80SJin Zhengxiong #define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ 144*4782ac80SJin Zhengxiong #define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ 145*4782ac80SJin Zhengxiong #define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ 146*4782ac80SJin Zhengxiong #define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ 147*4782ac80SJin Zhengxiong #define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ 148*4782ac80SJin Zhengxiong 149*4782ac80SJin Zhengxiong struct ahci_cmd_hdr { 150*4782ac80SJin Zhengxiong u32 opts; 151*4782ac80SJin Zhengxiong u32 status; 152*4782ac80SJin Zhengxiong u32 tbl_addr; 153*4782ac80SJin Zhengxiong u32 tbl_addr_hi; 154*4782ac80SJin Zhengxiong u32 reserved[4]; 155*4782ac80SJin Zhengxiong }; 156*4782ac80SJin Zhengxiong 157*4782ac80SJin Zhengxiong struct ahci_sg { 158*4782ac80SJin Zhengxiong u32 addr; 159*4782ac80SJin Zhengxiong u32 addr_hi; 160*4782ac80SJin Zhengxiong u32 reserved; 161*4782ac80SJin Zhengxiong u32 flags_size; 162*4782ac80SJin Zhengxiong }; 163*4782ac80SJin Zhengxiong 164*4782ac80SJin Zhengxiong struct ahci_ioports { 165*4782ac80SJin Zhengxiong u32 cmd_addr; 166*4782ac80SJin Zhengxiong u32 scr_addr; 167*4782ac80SJin Zhengxiong u32 port_mmio; 168*4782ac80SJin Zhengxiong struct ahci_cmd_hdr *cmd_slot; 169*4782ac80SJin Zhengxiong struct ahci_sg *cmd_tbl_sg; 170*4782ac80SJin Zhengxiong u32 cmd_tbl; 171*4782ac80SJin Zhengxiong u32 rx_fis; 172*4782ac80SJin Zhengxiong }; 173*4782ac80SJin Zhengxiong 174*4782ac80SJin Zhengxiong struct ahci_probe_ent { 175*4782ac80SJin Zhengxiong pci_dev_t dev; 176*4782ac80SJin Zhengxiong struct ahci_ioports port[AHCI_MAX_PORTS]; 177*4782ac80SJin Zhengxiong u32 n_ports; 178*4782ac80SJin Zhengxiong u32 hard_port_no; 179*4782ac80SJin Zhengxiong u32 host_flags; 180*4782ac80SJin Zhengxiong u32 host_set_flags; 181*4782ac80SJin Zhengxiong u32 mmio_base; 182*4782ac80SJin Zhengxiong u32 pio_mask; 183*4782ac80SJin Zhengxiong u32 udma_mask; 184*4782ac80SJin Zhengxiong u32 flags; 185*4782ac80SJin Zhengxiong u32 cap; /* cache of HOST_CAP register */ 186*4782ac80SJin Zhengxiong u32 port_map; /* cache of HOST_PORTS_IMPL reg */ 187*4782ac80SJin Zhengxiong u32 link_port_map; /*linkup port map*/ 188*4782ac80SJin Zhengxiong }; 189*4782ac80SJin Zhengxiong 190*4782ac80SJin Zhengxiong #endif 191