14782ac80SJin Zhengxiong /* 24c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 34782ac80SJin Zhengxiong * Author: Jason Jin<Jason.jin@freescale.com> 44782ac80SJin Zhengxiong * Zhang Wei<wei.zhang@freescale.com> 54782ac80SJin Zhengxiong * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 74782ac80SJin Zhengxiong */ 84782ac80SJin Zhengxiong #ifndef _AHCI_H_ 94782ac80SJin Zhengxiong #define _AHCI_H_ 104782ac80SJin Zhengxiong 11942e3143SRob Herring #include <pci.h> 12942e3143SRob Herring 134782ac80SJin Zhengxiong #define AHCI_PCI_BAR 0x24 144782ac80SJin Zhengxiong #define AHCI_MAX_SG 56 /* hardware max is 64K */ 154782ac80SJin Zhengxiong #define AHCI_CMD_SLOT_SZ 32 169f472e65SStefano Babic #define AHCI_MAX_CMD_SLOT 32 174782ac80SJin Zhengxiong #define AHCI_RX_FIS_SZ 256 184782ac80SJin Zhengxiong #define AHCI_CMD_TBL_HDR 0x80 194782ac80SJin Zhengxiong #define AHCI_CMD_TBL_CDB 0x40 204782ac80SJin Zhengxiong #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) 219f472e65SStefano Babic #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ 229f472e65SStefano Babic AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) 234782ac80SJin Zhengxiong #define AHCI_CMD_ATAPI (1 << 5) 244782ac80SJin Zhengxiong #define AHCI_CMD_WRITE (1 << 6) 254782ac80SJin Zhengxiong #define AHCI_CMD_PREFETCH (1 << 7) 264782ac80SJin Zhengxiong #define AHCI_CMD_RESET (1 << 8) 274782ac80SJin Zhengxiong #define AHCI_CMD_CLR_BUSY (1 << 10) 284782ac80SJin Zhengxiong 294782ac80SJin Zhengxiong #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ 304782ac80SJin Zhengxiong 314782ac80SJin Zhengxiong /* Global controller registers */ 324782ac80SJin Zhengxiong #define HOST_CAP 0x00 /* host capabilities */ 334782ac80SJin Zhengxiong #define HOST_CTL 0x04 /* global host control */ 344782ac80SJin Zhengxiong #define HOST_IRQ_STAT 0x08 /* interrupt status */ 354782ac80SJin Zhengxiong #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ 364782ac80SJin Zhengxiong #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ 374e422bceSStefan Reinauer #define HOST_CAP2 0x24 /* host capabilities, extended */ 384782ac80SJin Zhengxiong 394782ac80SJin Zhengxiong /* HOST_CTL bits */ 404782ac80SJin Zhengxiong #define HOST_RESET (1 << 0) /* reset controller; self-clear */ 414782ac80SJin Zhengxiong #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ 424782ac80SJin Zhengxiong #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ 434782ac80SJin Zhengxiong 444782ac80SJin Zhengxiong /* Registers for each SATA port */ 454782ac80SJin Zhengxiong #define PORT_LST_ADDR 0x00 /* command list DMA addr */ 464782ac80SJin Zhengxiong #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ 474782ac80SJin Zhengxiong #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ 484782ac80SJin Zhengxiong #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ 494782ac80SJin Zhengxiong #define PORT_IRQ_STAT 0x10 /* interrupt status */ 504782ac80SJin Zhengxiong #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ 514782ac80SJin Zhengxiong #define PORT_CMD 0x18 /* port command */ 524782ac80SJin Zhengxiong #define PORT_TFDATA 0x20 /* taskfile data */ 534782ac80SJin Zhengxiong #define PORT_SIG 0x24 /* device TF signature */ 544782ac80SJin Zhengxiong #define PORT_CMD_ISSUE 0x38 /* command issue */ 554782ac80SJin Zhengxiong #define PORT_SCR 0x28 /* SATA phy register block */ 564782ac80SJin Zhengxiong #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ 574782ac80SJin Zhengxiong #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ 584782ac80SJin Zhengxiong #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ 594782ac80SJin Zhengxiong #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ 604782ac80SJin Zhengxiong 614782ac80SJin Zhengxiong /* PORT_IRQ_{STAT,MASK} bits */ 624782ac80SJin Zhengxiong #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ 634782ac80SJin Zhengxiong #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ 644782ac80SJin Zhengxiong #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ 654782ac80SJin Zhengxiong #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ 664782ac80SJin Zhengxiong #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ 674782ac80SJin Zhengxiong #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ 684782ac80SJin Zhengxiong #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ 694782ac80SJin Zhengxiong #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ 704782ac80SJin Zhengxiong 714782ac80SJin Zhengxiong #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ 724782ac80SJin Zhengxiong #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ 734782ac80SJin Zhengxiong #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ 744782ac80SJin Zhengxiong #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ 754782ac80SJin Zhengxiong #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ 764782ac80SJin Zhengxiong #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ 774782ac80SJin Zhengxiong #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ 784782ac80SJin Zhengxiong #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ 794782ac80SJin Zhengxiong #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ 804782ac80SJin Zhengxiong 814782ac80SJin Zhengxiong #define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ 824782ac80SJin Zhengxiong | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR 834782ac80SJin Zhengxiong 844782ac80SJin Zhengxiong #define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ 854782ac80SJin Zhengxiong | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ 864782ac80SJin Zhengxiong | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ 874782ac80SJin Zhengxiong | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ 884782ac80SJin Zhengxiong | PORT_IRQ_D2H_REG_FIS 894782ac80SJin Zhengxiong 904782ac80SJin Zhengxiong /* PORT_CMD bits */ 914782ac80SJin Zhengxiong #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ 924782ac80SJin Zhengxiong #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ 934782ac80SJin Zhengxiong #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ 944782ac80SJin Zhengxiong #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ 954782ac80SJin Zhengxiong #define PORT_CMD_CLO (1 << 3) /* Command list override */ 964782ac80SJin Zhengxiong #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ 974782ac80SJin Zhengxiong #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ 984782ac80SJin Zhengxiong #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ 994782ac80SJin Zhengxiong 1004782ac80SJin Zhengxiong #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ 1014782ac80SJin Zhengxiong #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ 1024782ac80SJin Zhengxiong #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ 1034782ac80SJin Zhengxiong 1044782ac80SJin Zhengxiong #define AHCI_MAX_PORTS 32 1054782ac80SJin Zhengxiong 1064782ac80SJin Zhengxiong /* SETFEATURES stuff */ 1074782ac80SJin Zhengxiong #define SETFEATURES_XFER 0x03 1084782ac80SJin Zhengxiong #define XFER_UDMA_7 0x47 1094782ac80SJin Zhengxiong #define XFER_UDMA_6 0x46 1104782ac80SJin Zhengxiong #define XFER_UDMA_5 0x45 1114782ac80SJin Zhengxiong #define XFER_UDMA_4 0x44 1124782ac80SJin Zhengxiong #define XFER_UDMA_3 0x43 1134782ac80SJin Zhengxiong #define XFER_UDMA_2 0x42 1144782ac80SJin Zhengxiong #define XFER_UDMA_1 0x41 1154782ac80SJin Zhengxiong #define XFER_UDMA_0 0x40 1164782ac80SJin Zhengxiong #define XFER_MW_DMA_2 0x22 1174782ac80SJin Zhengxiong #define XFER_MW_DMA_1 0x21 1184782ac80SJin Zhengxiong #define XFER_MW_DMA_0 0x20 1194782ac80SJin Zhengxiong #define XFER_SW_DMA_2 0x12 1204782ac80SJin Zhengxiong #define XFER_SW_DMA_1 0x11 1214782ac80SJin Zhengxiong #define XFER_SW_DMA_0 0x10 1224782ac80SJin Zhengxiong #define XFER_PIO_4 0x0C 1234782ac80SJin Zhengxiong #define XFER_PIO_3 0x0B 1244782ac80SJin Zhengxiong #define XFER_PIO_2 0x0A 1254782ac80SJin Zhengxiong #define XFER_PIO_1 0x09 1264782ac80SJin Zhengxiong #define XFER_PIO_0 0x08 1274782ac80SJin Zhengxiong #define XFER_PIO_SLOW 0x00 1284782ac80SJin Zhengxiong 1294782ac80SJin Zhengxiong #define ATA_FLAG_SATA (1 << 3) 1304782ac80SJin Zhengxiong #define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ 1314782ac80SJin Zhengxiong #define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ 1324782ac80SJin Zhengxiong #define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ 1334782ac80SJin Zhengxiong #define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ 1344782ac80SJin Zhengxiong #define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ 1354782ac80SJin Zhengxiong 1364782ac80SJin Zhengxiong struct ahci_cmd_hdr { 1374782ac80SJin Zhengxiong u32 opts; 1384782ac80SJin Zhengxiong u32 status; 1394782ac80SJin Zhengxiong u32 tbl_addr; 1404782ac80SJin Zhengxiong u32 tbl_addr_hi; 1414782ac80SJin Zhengxiong u32 reserved[4]; 1424782ac80SJin Zhengxiong }; 1434782ac80SJin Zhengxiong 1444782ac80SJin Zhengxiong struct ahci_sg { 1454782ac80SJin Zhengxiong u32 addr; 1464782ac80SJin Zhengxiong u32 addr_hi; 1474782ac80SJin Zhengxiong u32 reserved; 1484782ac80SJin Zhengxiong u32 flags_size; 1494782ac80SJin Zhengxiong }; 1504782ac80SJin Zhengxiong 1514782ac80SJin Zhengxiong struct ahci_ioports { 1524782ac80SJin Zhengxiong u32 cmd_addr; 1534782ac80SJin Zhengxiong u32 scr_addr; 1544782ac80SJin Zhengxiong u32 port_mmio; 1554782ac80SJin Zhengxiong struct ahci_cmd_hdr *cmd_slot; 1564782ac80SJin Zhengxiong struct ahci_sg *cmd_tbl_sg; 1574782ac80SJin Zhengxiong u32 cmd_tbl; 1584782ac80SJin Zhengxiong u32 rx_fis; 1594782ac80SJin Zhengxiong }; 1604782ac80SJin Zhengxiong 1614782ac80SJin Zhengxiong struct ahci_probe_ent { 1624782ac80SJin Zhengxiong pci_dev_t dev; 1634782ac80SJin Zhengxiong struct ahci_ioports port[AHCI_MAX_PORTS]; 1644782ac80SJin Zhengxiong u32 n_ports; 1654782ac80SJin Zhengxiong u32 hard_port_no; 1664782ac80SJin Zhengxiong u32 host_flags; 1674782ac80SJin Zhengxiong u32 host_set_flags; 1684782ac80SJin Zhengxiong u32 mmio_base; 1694782ac80SJin Zhengxiong u32 pio_mask; 1704782ac80SJin Zhengxiong u32 udma_mask; 1714782ac80SJin Zhengxiong u32 flags; 1724782ac80SJin Zhengxiong u32 cap; /* cache of HOST_CAP register */ 1734782ac80SJin Zhengxiong u32 port_map; /* cache of HOST_PORTS_IMPL reg */ 1744782ac80SJin Zhengxiong u32 link_port_map; /*linkup port map*/ 1754782ac80SJin Zhengxiong }; 1764782ac80SJin Zhengxiong 177942e3143SRob Herring int ahci_init(u32 base); 178942e3143SRob Herring 1794782ac80SJin Zhengxiong #endif 180