1 /*
2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
4 * Syed Mohammed Khasim <khasim@ti.com>
5 *
6 * Referred to Linux Kernel DSS driver files for OMAP3 by
7 * Tomi Valkeinen from drivers/video/omap2/dss/
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation's version 2 and any
15 * later version the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <asm/arch/dss.h>
31 #include <video_fb.h>
32
33 /* Configure VENC for a given Mode (NTSC / PAL) */
omap3_dss_venc_config(const struct venc_regs * venc_cfg,u32 height,u32 width)34 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
35 u32 height, u32 width)
36 {
37 struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
38 struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
39 struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
40
41 writel(venc_cfg->status, &venc->status);
42 writel(venc_cfg->f_control, &venc->f_control);
43 writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
44 writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
45 writel(venc_cfg->llen, &venc->llen);
46 writel(venc_cfg->flens, &venc->flens);
47 writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
48 writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
49 writel(venc_cfg->c_phase, &venc->c_phase);
50 writel(venc_cfg->gain_u, &venc->gain_u);
51 writel(venc_cfg->gain_v, &venc->gain_v);
52 writel(venc_cfg->gain_y, &venc->gain_y);
53 writel(venc_cfg->black_level, &venc->black_level);
54 writel(venc_cfg->blank_level, &venc->blank_level);
55 writel(venc_cfg->x_color, &venc->x_color);
56 writel(venc_cfg->m_control, &venc->m_control);
57 writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
58 writel(venc_cfg->s_carr, &venc->s_carr);
59 writel(venc_cfg->line21, &venc->line21);
60 writel(venc_cfg->ln_sel, &venc->ln_sel);
61 writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
62 writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
63 writel(venc_cfg->savid__eavid, &venc->savid__eavid);
64 writel(venc_cfg->flen__fal, &venc->flen__fal);
65 writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
66 writel(venc_cfg->hs_int_start_stop_x, &venc->hs_int_start_stop_x);
67 writel(venc_cfg->hs_ext_start_stop_x, &venc->hs_ext_start_stop_x);
68 writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
69 writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
70 &venc->vs_int_stop_x__vs_int_start_y);
71 writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
72 &venc->vs_int_stop_y__vs_ext_start_x);
73 writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
74 &venc->vs_ext_stop_x__vs_ext_start_y);
75 writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
76 writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
77 writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);
78 writel(venc_cfg->fid_int_start_x__fid_int_start_y,
79 &venc->fid_int_start_x__fid_int_start_y);
80 writel(venc_cfg->fid_int_offset_y__fid_ext_start_x,
81 &venc->fid_int_offset_y__fid_ext_start_x);
82 writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,
83 &venc->fid_ext_start_y__fid_ext_offset_y);
84 writel(venc_cfg->tvdetgp_int_start_stop_x,
85 &venc->tvdetgp_int_start_stop_x);
86 writel(venc_cfg->tvdetgp_int_start_stop_y,
87 &venc->tvdetgp_int_start_stop_y);
88 writel(venc_cfg->gen_ctrl, &venc->gen_ctrl);
89 writel(venc_cfg->output_control, &venc->output_control);
90 writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
91
92 /* Configure DSS for VENC Settings */
93 writel(VENC_CLK_ENABLE | DAC_DEMEN | DAC_POWERDN | VENC_OUT_SEL,
94 &dss->control);
95
96 /* Configure height and width for Digital out */
97 writel(height << DIG_LPP_SHIFT | width, &dispc->size_dig);
98 }
99
100 /* Configure Panel Specific Parameters */
omap3_dss_panel_config(const struct panel_config * panel_cfg)101 void omap3_dss_panel_config(const struct panel_config *panel_cfg)
102 {
103 struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
104 struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
105
106 writel(DSS_SOFTRESET, &dss->sysconfig);
107 while (!(readl(&dss->sysstatus) & DSS_RESETDONE))
108 ;
109
110 writel(panel_cfg->timing_h, &dispc->timing_h);
111 writel(panel_cfg->timing_v, &dispc->timing_v);
112 writel(panel_cfg->pol_freq, &dispc->pol_freq);
113 writel(panel_cfg->divisor, &dispc->divisor);
114 writel(panel_cfg->lcd_size, &dispc->size_lcd);
115 writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
116 writel(panel_cfg->panel_type << TFTSTN_SHIFT |
117 panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control);
118 writel(panel_cfg->panel_color, &dispc->default_color0);
119 writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0);
120
121 if (!panel_cfg->frame_buffer)
122 return;
123
124 writel(panel_cfg->gfx_format | GFX_ENABLE, &dispc->gfx_attributes);
125 writel(1, &dispc->gfx_row_inc);
126 writel(1, &dispc->gfx_pixel_inc);
127 writel(panel_cfg->lcd_size, &dispc->gfx_size);
128 }
129
130 /* Enable LCD and DIGITAL OUT in DSS */
omap3_dss_enable(void)131 void omap3_dss_enable(void)
132 {
133 struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
134 u32 l;
135
136 l = readl(&dispc->control);
137 l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1;
138 writel(l, &dispc->control);
139 }
140
141 #ifdef CONFIG_CFB_CONSOLE
__board_video_init(void)142 int __board_video_init(void)
143 {
144 return -1;
145 }
146
147 int board_video_init(void)
148 __attribute__((weak, alias("__board_video_init")));
149
video_hw_init(void)150 void *video_hw_init(void)
151 {
152 static GraphicDevice dssfb;
153 GraphicDevice *pGD = &dssfb;
154 struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
155
156 if (board_video_init() || !readl(&dispc->gfx_ba0))
157 return NULL;
158
159 pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1;
160 pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1;
161 pGD->gdfBytesPP = 4;
162 pGD->gdfIndex = GDF_32BIT_X888RGB;
163 pGD->frameAdrs = readl(&dispc->gfx_ba0);
164
165 return pGD;
166 }
167 #endif
168