1menu "SPI Support" 2 3config DM_SPI 4 bool "Enable Driver Model for SPI drivers" 5 depends on DM 6 help 7 Enable driver model for SPI. The SPI slave interface 8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by 9 the SPI uclass. Drivers provide methods to access the SPI 10 buses that they control. The uclass interface is defined in 11 include/spi.h. The existing spi_slave structure is attached 12 as 'parent data' to every slave on each bus. Slaves 13 typically use driver-private data instead of extending the 14 spi_slave structure. 15 16if DM_SPI 17 18config CADENCE_QSPI 19 bool "Cadence QSPI driver" 20 help 21 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be 22 used to access the SPI NOR flash on platforms embedding this 23 Cadence IP core. 24 25config DESIGNWARE_SPI 26 bool "Designware SPI driver" 27 help 28 Enable the Designware SPI driver. This driver can be used to 29 access the SPI NOR flash on platforms embedding this Designware 30 IP core. 31 32config EXYNOS_SPI 33 bool "Samsung Exynos SPI driver" 34 help 35 Enable the Samsung Exynos SPI driver. This driver can be used to 36 access the SPI NOR flash on platforms embedding this Samsung 37 Exynos IP core. 38 39config FSL_DSPI 40 bool "Freescale DSPI driver" 41 help 42 Enable the Freescale DSPI driver. This driver can be used to 43 access the SPI NOR flash and SPI Data flash on platforms embedding 44 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms 45 use this driver. 46 47config FSL_QSPI 48 bool "Freescale QSPI driver" 49 help 50 Enable the Freescale Quad-SPI (QSPI) driver. This driver can be 51 used to access the SPI NOR flash on platforms embedding this 52 Freescale IP core. 53 54config ICH_SPI 55 bool "Intel ICH SPI driver" 56 help 57 Enable the Intel ICH SPI driver. This driver can be used to 58 access the SPI NOR flash on platforms embedding this Intel 59 ICH IP core. 60 61config SANDBOX_SPI 62 bool "Sandbox SPI driver" 63 depends on SANDBOX && DM 64 help 65 Enable SPI support for sandbox. This is an emulation of a real SPI 66 bus. Devices can be attached to the bus using the device tree 67 which specifies the driver to use. As an example, see this device 68 tree fragment from sandbox.dts. It shows that the SPI bus has a 69 single flash device on chip select 0 which is emulated by the driver 70 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c. 71 72 spi@0 { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 reg = <0>; 76 compatible = "sandbox,spi"; 77 cs-gpios = <0>, <&gpio_a 0>; 78 flash@0 { 79 reg = <0>; 80 compatible = "spansion,m25p16", "sandbox,spi-flash"; 81 spi-max-frequency = <40000000>; 82 sandbox,filename = "spi.bin"; 83 }; 84 }; 85 86config TEGRA114_SPI 87 bool "nVidia Tegra114 SPI driver" 88 help 89 Enable the nVidia Tegra114 SPI driver. This driver can be used to 90 access the SPI NOR flash on platforms embedding this nVidia Tegra114 91 IP core. 92 93 This controller is different than the older SoCs SPI controller and 94 also register interface get changed with this controller. 95 96config TEGRA20_SFLASH 97 bool "nVidia Tegra20 Serial Flash controller driver" 98 help 99 Enable the nVidia Tegra20 Serial Flash controller driver. This driver 100 can be used to access the SPI NOR flash on platforms embedding this 101 nVidia Tegra20 IP core. 102 103config TEGRA20_SLINK 104 bool "nVidia Tegra20/Tegra30 SLINK driver" 105 help 106 Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can 107 be used to access the SPI NOR flash on platforms embedding this 108 nVidia Tegra20/Tegra30 IP cores. 109 110config XILINX_SPI 111 bool "Xilinx SPI driver" 112 help 113 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI 114 controller support 8 bit SPI transfers only, with or w/o FIFO. 115 For more info on Xilinx SPI Register Definitions and Overview 116 see driver file - drivers/spi/xilinx_spi.c 117 118config ZYNQ_SPI 119 bool "Zynq SPI driver" 120 depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP 121 help 122 Enable the Zynq SPI driver. This driver can be used to 123 access the SPI NOR flash on platforms embedding this Zynq 124 SPI IP core. 125 126endif # if DM_SPI 127 128config FSL_ESPI 129 bool "Freescale eSPI driver" 130 help 131 Enable the Freescale eSPI driver. This driver can be used to 132 access the SPI interface and SPI NOR flash on platforms embedding 133 this Freescale eSPI IP core. 134 135config TI_QSPI 136 bool "TI QSPI driver" 137 help 138 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. 139 This driver support spi flash single, quad and memory reads. 140 141endmenu # menu "SPI Support" 142