xref: /openbmc/u-boot/drivers/spi/Kconfig (revision c6e18144)
1menu "SPI Support"
2
3config DM_SPI
4	bool "Enable Driver Model for SPI drivers"
5	depends on DM
6	help
7	  Enable driver model for SPI. The SPI slave interface
8	  (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
9	  the SPI uclass. Drivers provide methods to access the SPI
10	  buses that they control. The uclass interface is defined in
11	  include/spi.h. The existing spi_slave structure is attached
12	  as 'parent data' to every slave on each bus. Slaves
13	  typically use driver-private data instead of extending the
14	  spi_slave structure.
15
16if DM_SPI
17
18config ALTERA_SPI
19	bool "Altera SPI driver"
20	help
21	  Enable the Altera SPI driver. This driver can be used to
22	  access the SPI NOR flash on platforms embedding this Altera
23	  IP core. Please find details on the "Embedded Peripherals IP
24	  User Guide" of Altera.
25
26config CADENCE_QSPI
27	bool "Cadence QSPI driver"
28	help
29	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
30	  used to access the SPI NOR flash on platforms embedding this
31	  Cadence IP core.
32
33config DESIGNWARE_SPI
34	bool "Designware SPI driver"
35	help
36	  Enable the Designware SPI driver. This driver can be used to
37	  access the SPI NOR flash on platforms embedding this Designware
38	  IP core.
39
40config EXYNOS_SPI
41	bool "Samsung Exynos SPI driver"
42	help
43	  Enable the Samsung Exynos SPI driver. This driver can be used to
44	  access the SPI NOR flash on platforms embedding this Samsung
45	  Exynos IP core.
46
47config FSL_DSPI
48	bool "Freescale DSPI driver"
49	help
50	  Enable the Freescale DSPI driver. This driver can be used to
51	  access the SPI NOR flash and SPI Data flash on platforms embedding
52	  this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
53	  use this driver.
54
55config FSL_QSPI
56	bool "Freescale QSPI driver"
57	help
58	  Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
59	  used to access the SPI NOR flash on platforms embedding this
60	  Freescale IP core.
61
62config ICH_SPI
63	bool "Intel ICH SPI driver"
64	help
65	  Enable the Intel ICH SPI driver. This driver can be used to
66	  access the SPI NOR flash on platforms embedding this Intel
67	  ICH IP core.
68
69config ROCKCHIP_SPI
70	bool "Rockchip SPI driver"
71	help
72	  Enable the Rockchip SPI driver, used to access SPI NOR flash and
73	  other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
74	  This uses driver model and requires a device tree binding to
75	  operate.
76
77config SANDBOX_SPI
78	bool "Sandbox SPI driver"
79	depends on SANDBOX && DM
80	help
81	  Enable SPI support for sandbox. This is an emulation of a real SPI
82	  bus. Devices can be attached to the bus using the device tree
83	  which specifies the driver to use. As an example, see this device
84	  tree fragment from sandbox.dts. It shows that the SPI bus has a
85	  single flash device on chip select 0 which is emulated by the driver
86	  for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
87
88	  spi@0 {
89		#address-cells = <1>;
90		#size-cells = <0>;
91		reg = <0>;
92		compatible = "sandbox,spi";
93		cs-gpios = <0>, <&gpio_a 0>;
94		flash@0 {
95			reg = <0>;
96			compatible = "spansion,m25p16", "sandbox,spi-flash";
97			spi-max-frequency = <40000000>;
98			sandbox,filename = "spi.bin";
99		};
100	  };
101
102config TEGRA114_SPI
103	bool "nVidia Tegra114 SPI driver"
104	help
105	  Enable the nVidia Tegra114 SPI driver. This driver can be used to
106	  access the SPI NOR flash on platforms embedding this nVidia Tegra114
107	  IP core.
108
109	  This controller is different than the older SoCs SPI controller and
110	  also register interface get changed with this controller.
111
112config TEGRA20_SFLASH
113	bool "nVidia Tegra20 Serial Flash controller driver"
114	help
115	  Enable the nVidia Tegra20 Serial Flash controller driver. This driver
116	  can be used to access the SPI NOR flash on platforms embedding this
117	  nVidia Tegra20 IP core.
118
119config TEGRA20_SLINK
120	bool "nVidia Tegra20/Tegra30 SLINK driver"
121	help
122	  Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
123	  be used to access the SPI NOR flash on platforms embedding this
124	  nVidia Tegra20/Tegra30 IP cores.
125
126config TEGRA210_QSPI
127	bool "nVidia Tegra210 QSPI driver"
128	help
129	  Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
130	  be used to access SPI chips on platforms embedding this
131	  NVIDIA Tegra210 IP core.
132
133config XILINX_SPI
134	bool "Xilinx SPI driver"
135	help
136	  Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
137	  controller support 8 bit SPI transfers only, with or w/o FIFO.
138	  For more info on Xilinx SPI Register Definitions and Overview
139	  see driver file - drivers/spi/xilinx_spi.c
140
141config ZYNQ_SPI
142	bool "Zynq SPI driver"
143	depends on ARCH_ZYNQ || ARCH_ZYNQMP
144	help
145	  Enable the Zynq SPI driver. This driver can be used to
146	  access the SPI NOR flash on platforms embedding this Zynq
147	  SPI IP core.
148
149config ZYNQ_QSPI
150	bool "Zynq QSPI driver"
151	depends on ARCH_ZYNQ
152	help
153	  Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
154	  used to access the SPI NOR flash on platforms embedding this
155	  Zynq QSPI IP core. This IP is used to connect the flash in
156	  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
157
158endif # if DM_SPI
159
160config FSL_ESPI
161	bool "Freescale eSPI driver"
162	help
163	  Enable the Freescale eSPI driver. This driver can be used to
164	  access the SPI interface and SPI NOR flash on platforms embedding
165	  this Freescale eSPI IP core.
166
167config TI_QSPI
168	bool "TI QSPI driver"
169	help
170	  Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
171	  This driver support spi flash single, quad and memory reads.
172
173endmenu # menu "SPI Support"
174