xref: /openbmc/u-boot/drivers/spi/Kconfig (revision c3d89140)
1menu "SPI Support"
2
3config DM_SPI
4	bool "Enable Driver Model for SPI drivers"
5	depends on DM
6	help
7	  Enable driver model for SPI. The SPI slave interface
8	  (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
9	  the SPI uclass. Drivers provide methods to access the SPI
10	  buses that they control. The uclass interface is defined in
11	  include/spi.h. The existing spi_slave structure is attached
12	  as 'parent data' to every slave on each bus. Slaves
13	  typically use driver-private data instead of extending the
14	  spi_slave structure.
15
16if DM_SPI
17
18config CADENCE_QSPI
19	bool "Cadence QSPI driver"
20	help
21	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
22	  used to access the SPI NOR flash on platforms embedding this
23	  Cadence IP core.
24
25config DESIGNWARE_SPI
26	bool "Designware SPI driver"
27	help
28	  Enable the Designware SPI driver. This driver can be used to
29	  access the SPI NOR flash on platforms embedding this Designware
30	  IP core.
31
32config EXYNOS_SPI
33	bool "Samsung Exynos SPI driver"
34	help
35	  Enable the Samsung Exynos SPI driver. This driver can be used to
36	  access the SPI NOR flash on platforms embedding this Samsung
37	  Exynos IP core.
38
39config FSL_DSPI
40	bool "Freescale DSPI driver"
41	help
42	  Enable the Freescale DSPI driver. This driver can be used to
43	  access the SPI NOR flash and SPI Data flash on platforms embedding
44	  this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
45	  use this driver.
46
47config FSL_QSPI
48	bool "Freescale QSPI driver"
49	help
50	  Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
51	  used to access the SPI NOR flash on platforms embedding this
52	  Freescale IP core.
53
54config ICH_SPI
55	bool "Intel ICH SPI driver"
56	help
57	  Enable the Intel ICH SPI driver. This driver can be used to
58	  access the SPI NOR flash on platforms embedding this Intel
59	  ICH IP core.
60
61config ROCKCHIP_SPI
62	bool "Rockchip SPI driver"
63	help
64	  Enable the Rockchip SPI driver, used to access SPI NOR flash and
65	  other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
66	  This uses driver model and requires a device tree binding to
67	  operate.
68
69config SANDBOX_SPI
70	bool "Sandbox SPI driver"
71	depends on SANDBOX && DM
72	help
73	  Enable SPI support for sandbox. This is an emulation of a real SPI
74	  bus. Devices can be attached to the bus using the device tree
75	  which specifies the driver to use. As an example, see this device
76	  tree fragment from sandbox.dts. It shows that the SPI bus has a
77	  single flash device on chip select 0 which is emulated by the driver
78	  for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
79
80	  spi@0 {
81		#address-cells = <1>;
82		#size-cells = <0>;
83		reg = <0>;
84		compatible = "sandbox,spi";
85		cs-gpios = <0>, <&gpio_a 0>;
86		flash@0 {
87			reg = <0>;
88			compatible = "spansion,m25p16", "sandbox,spi-flash";
89			spi-max-frequency = <40000000>;
90			sandbox,filename = "spi.bin";
91		};
92	  };
93
94config TEGRA114_SPI
95	bool "nVidia Tegra114 SPI driver"
96	help
97	  Enable the nVidia Tegra114 SPI driver. This driver can be used to
98	  access the SPI NOR flash on platforms embedding this nVidia Tegra114
99	  IP core.
100
101	  This controller is different than the older SoCs SPI controller and
102	  also register interface get changed with this controller.
103
104config TEGRA20_SFLASH
105	bool "nVidia Tegra20 Serial Flash controller driver"
106	help
107	  Enable the nVidia Tegra20 Serial Flash controller driver. This driver
108	  can be used to access the SPI NOR flash on platforms embedding this
109	  nVidia Tegra20 IP core.
110
111config TEGRA20_SLINK
112	bool "nVidia Tegra20/Tegra30 SLINK driver"
113	help
114	  Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
115	  be used to access the SPI NOR flash on platforms embedding this
116	  nVidia Tegra20/Tegra30 IP cores.
117
118config XILINX_SPI
119	bool "Xilinx SPI driver"
120	help
121	  Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
122	  controller support 8 bit SPI transfers only, with or w/o FIFO.
123	  For more info on Xilinx SPI Register Definitions and Overview
124	  see driver file - drivers/spi/xilinx_spi.c
125
126config ZYNQ_SPI
127	bool "Zynq SPI driver"
128	depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
129	help
130	  Enable the Zynq SPI driver. This driver can be used to
131	  access the SPI NOR flash on platforms embedding this Zynq
132	  SPI IP core.
133
134endif # if DM_SPI
135
136config FSL_ESPI
137	bool "Freescale eSPI driver"
138	help
139	  Enable the Freescale eSPI driver. This driver can be used to
140	  access the SPI interface and SPI NOR flash on platforms embedding
141	  this Freescale eSPI IP core.
142
143config TI_QSPI
144	bool "TI QSPI driver"
145	help
146	  Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
147	  This driver support spi flash single, quad and memory reads.
148
149endmenu # menu "SPI Support"
150