xref: /openbmc/u-boot/drivers/spi/Kconfig (revision 9038cd53)
1config DM_SPI
2	bool "Enable Driver Model for SPI drivers"
3	depends on DM
4	help
5	  Enable driver model for SPI. The SPI slave interface
6	  (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
7	  the SPI uclass. Drivers provide methods to access the SPI
8	  buses that they control. The uclass interface is defined in
9	  include/spi.h. The existing spi_slave structure is attached
10	  as 'parent data' to every slave on each bus. Slaves
11	  typically use driver-private data instead of extending the
12	  spi_slave structure.
13
14config SANDBOX_SPI
15	bool "Sandbox SPI driver"
16	depends on SANDBOX && DM
17	help
18	  Enable SPI support for sandbox. This is an emulation of a real SPI
19	  bus. Devices can be attached to the bus using the device tree
20	  which specifies the driver to use. As an example, see this device
21	  tree fragment from sandbox.dts. It shows that the SPI bus has a
22	  single flash device on chip select 0 which is emulated by the driver
23	  for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
24
25	  spi@0 {
26		#address-cells = <1>;
27		#size-cells = <0>;
28		reg = <0>;
29		compatible = "sandbox,spi";
30		cs-gpios = <0>, <&gpio_a 0>;
31		flash@0 {
32			reg = <0>;
33			compatible = "spansion,m25p16", "sandbox,spi-flash";
34			spi-max-frequency = <40000000>;
35			sandbox,filename = "spi.bin";
36		};
37	};
38
39config DESIGNWARE_SPI
40	bool "Designware SPI driver"
41	depends on DM_SPI
42	help
43	  Enable the Designware SPI driver. This driver can be used to
44	  access the SPI NOR flash on platforms embedding this Designware
45	  IP core.
46
47config CADENCE_QSPI
48	bool "Cadence QSPI driver"
49	depends on DM_SPI
50	help
51	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
52	  used to access the SPI NOR flash on platforms embedding this
53	  Cadence IP core.
54