1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012-2020 ASPEED Technology Inc. 4 * 5 * Copyright 2016 Google, Inc 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <ram.h> 13 #include <regmap.h> 14 #include <reset.h> 15 #include <asm/io.h> 16 #include <asm/arch/scu_ast2500.h> 17 #include <asm/arch/sdram_ast2500.h> 18 #include <linux/err.h> 19 #include <linux/kernel.h> 20 #include <dt-bindings/clock/ast2500-clock.h> 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2500_SDRAMMC_MANUAL_CLK 25 26 /* bit-field of m_pll_param */ 27 #define SCU_MPLL_FREQ_MASK (SCU_MPLL_DENUM_MASK | SCU_MPLL_NUM_MASK | SCU_MPLL_POST_MASK) 28 #define SCU_MPLL_FREQ_400M 0x93002400 29 #define SCU_MPLL_FREQ_360M 0x930023A0 30 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_360M 31 32 #define SCU_MPLL_TURN_OFF BIT(19) 33 #define SCU_MPLL_BYPASS BIT(20) 34 #define SCU_MPLL_RESET BIT(21) 35 36 /* These configuration parameters are taken from Aspeed SDK */ 37 #define DDR4_MR46_MODE 0x08000000 38 #define DDR4_MR5_MODE 0x400 39 #define DDR4_MR13_MODE 0x101 40 #define DDR4_MR02_MODE 0x410 41 #define DDR4_TRFC 0x45457188 42 43 #define PHY_CFG_SIZE 15 44 45 static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000}; 46 static const struct { 47 u32 index[PHY_CFG_SIZE]; 48 u32 value[PHY_CFG_SIZE]; 49 } ddr4_phy_config = { 50 .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50}, 51 .value = { 52 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24, 53 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607, 54 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e, 55 }, 56 }; 57 58 /* supported SDRAM size */ 59 #define SDRAM_SIZE_1KB (1024U) 60 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 61 #define SDRAM_MIN_SIZE (128 * SDRAM_SIZE_1MB) 62 #define SDRAM_MAX_SIZE (1024 * SDRAM_SIZE_1MB) 63 64 DECLARE_GLOBAL_DATA_PTR; 65 66 /* 67 * Bandwidth configuration parameters for different SDRAM requests. 68 * These are hardcoded settings taken from Aspeed SDK. 69 */ 70 static const u32 ddr_max_grant_params[4] = { 71 0x88448844, 0x24422288, 0x22222222, 0x22222222 72 }; 73 74 /* 75 * These registers are not documented by Aspeed at all. 76 * All writes and reads are taken pretty much as is from SDK. 77 */ 78 struct ast2500_ddr_phy { 79 u32 phy[117]; 80 }; 81 82 struct dram_info { 83 struct ram_info info; 84 struct clk ddr_clk; 85 struct ast2500_sdrammc_regs *regs; 86 struct ast2500_scu *scu; 87 struct ast2500_ddr_phy *phy; 88 ulong clock_rate; 89 }; 90 91 static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy) 92 { 93 writel(0, &phy->phy[2]); 94 writel(0, &phy->phy[6]); 95 writel(0, &phy->phy[8]); 96 writel(0, &phy->phy[10]); 97 writel(0, &phy->phy[12]); 98 writel(0, &phy->phy[42]); 99 writel(0, &phy->phy[44]); 100 101 writel(0x86000000, &phy->phy[16]); 102 writel(0x00008600, &phy->phy[17]); 103 writel(0x80000000, &phy->phy[18]); 104 writel(0x80808080, &phy->phy[19]); 105 106 return 0; 107 } 108 109 static void ast2500_ddr_phy_init_process(struct dram_info *info) 110 { 111 struct ast2500_sdrammc_regs *regs = info->regs; 112 113 writel(0, ®s->phy_ctrl[0]); 114 writel(0x4040, &info->phy->phy[51]); 115 116 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 117 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) 118 ; 119 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE, 120 ®s->phy_ctrl[0]); 121 } 122 123 static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref) 124 { 125 writel(0, &info->regs->phy_ctrl[0]); 126 writel((vref << 8) | 0x6, &info->phy->phy[48]); 127 ast2500_ddr_phy_init_process(info); 128 } 129 130 static int ast2500_ddr_cbr_test(struct dram_info *info) 131 { 132 struct ast2500_sdrammc_regs *regs = info->regs; 133 int i; 134 const u32 test_params = SDRAM_TEST_EN 135 | SDRAM_TEST_ERRSTOP 136 | SDRAM_TEST_TWO_MODES; 137 int ret = 0; 138 139 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) | 140 (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing); 141 writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); 142 writel(0xff00ff00, ®s->test_init_val); 143 writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) | 144 SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl); 145 146 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) 147 ; 148 149 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { 150 ret = -EIO; 151 } else { 152 for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) { 153 writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params, 154 ®s->ecc_test_ctrl); 155 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) 156 ; 157 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { 158 ret = -EIO; 159 break; 160 } 161 } 162 } 163 164 writel(0, ®s->refresh_timing); 165 writel(0, ®s->ecc_test_ctrl); 166 167 return ret; 168 } 169 170 static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info) 171 { 172 int i; 173 int vref_min = 0xff; 174 int vref_max = 0; 175 int range_size = 0; 176 177 for (i = 1; i < 0x40; ++i) { 178 int res; 179 180 ast2500_sdrammc_set_vref(info, i); 181 res = ast2500_ddr_cbr_test(info); 182 if (res < 0) { 183 if (range_size > 0) 184 break; 185 } else { 186 ++range_size; 187 vref_min = min(vref_min, i); 188 vref_max = max(vref_max, i); 189 } 190 } 191 192 /* Pick average setting */ 193 ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2); 194 195 return 0; 196 } 197 198 static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info) 199 { 200 size_t vga_mem_size_base = 8 * 1024 * 1024; 201 u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK) 202 >> SCU_HWSTRAP_VGAMEM_SHIFT; 203 204 return vga_mem_size_base << vga_hwconf; 205 } 206 207 /* 208 * Find out RAM size and save it in dram_info 209 * 210 * The procedure is taken from Aspeed SDK 211 */ 212 static void ast2500_sdrammc_calc_size(struct dram_info *info) 213 { 214 /* The controller supports 128/256/512/1024 MB ram */ 215 size_t ram_size = SDRAM_MIN_SIZE; 216 const int write_test_offset = 0x100000; 217 u32 test_pattern = 0xdeadbeef; 218 u32 cap_param = SDRAM_CONF_CAP_1024M; 219 u32 refresh_timing_param = DDR4_TRFC; 220 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 221 222 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 223 ram_size >>= 1) { 224 writel(test_pattern, write_addr_base + (ram_size >> 1)); 225 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 226 } 227 228 /* One last write to overwrite all wrapped values */ 229 writel(test_pattern, write_addr_base); 230 231 /* Reset the pattern and see which value was really written */ 232 test_pattern = 0xdeadbeef; 233 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 234 ram_size >>= 1) { 235 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 236 break; 237 238 --cap_param; 239 refresh_timing_param >>= 8; 240 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 241 } 242 243 clrsetbits_le32(&info->regs->ac_timing[1], 244 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 245 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 246 << SDRAM_AC_TRFC_SHIFT)); 247 248 info->info.base = CONFIG_SYS_SDRAM_BASE; 249 info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); 250 clrsetbits_le32(&info->regs->config, 251 (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), 252 ((cap_param & SDRAM_CONF_CAP_MASK) 253 << SDRAM_CONF_CAP_SHIFT)); 254 } 255 256 #ifdef CONFIG_ASPEED_ECC 257 static void ast2500_sdrammc_ecc_enable(struct dram_info *info) 258 { 259 struct ast2500_sdrammc_regs *regs = info->regs; 260 size_t conf_size; 261 u32 reg; 262 263 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 264 if (conf_size > info->info.size) { 265 printf("warning: ECC configured %dMB but actual size is %dMB\n", 266 CONFIG_ASPEED_ECC_SIZE, 267 info->info.size / SDRAM_SIZE_1MB); 268 conf_size = info->info.size; 269 } else if (conf_size == 0) { 270 conf_size = info->info.size; 271 } 272 273 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 274 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 275 reg = readl(®s->config) | 276 (SDRAM_CONF_ECC_EN | SDRAM_CONF_CACHE_ADDR_CTRL); 277 writel(reg, ®s->config); 278 279 writel(0, ®s->test_init_val); 280 writel(0, ®s->test_addr); 281 writel(0x221, ®s->ecc_test_ctrl); 282 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 283 ; 284 writel(0, ®s->ecc_test_ctrl); 285 writel(BIT(31), ®s->intr_ctrl); 286 writel(0, ®s->intr_ctrl); 287 288 writel(0x400, ®s->ecc_test_ctrl); 289 printf("ECC enable, "); 290 } 291 #endif 292 293 static int ast2500_sdrammc_init_ddr4(struct dram_info *info) 294 { 295 int i; 296 const u32 power_control = SDRAM_PCR_CKE_EN 297 | (1 << SDRAM_PCR_CKE_DELAY_SHIFT) 298 | (2 << SDRAM_PCR_TCKE_PW_SHIFT) 299 | SDRAM_PCR_RESETN_DIS 300 | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN; 301 const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT) 302 #ifdef CONFIG_DUALX8_RAM 303 | SDRAM_CONF_DUALX8 304 #endif 305 | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4; 306 int ret; 307 308 writel(conf, &info->regs->config); 309 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 310 writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]); 311 312 writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting); 313 writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting); 314 writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting); 315 writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting); 316 317 for (i = 0; i < PHY_CFG_SIZE; ++i) { 318 writel(ddr4_phy_config.value[i], 319 &info->phy->phy[ddr4_phy_config.index[i]]); 320 } 321 322 writel(power_control, &info->regs->power_control); 323 324 ast2500_ddr_phy_init_process(info); 325 326 ret = ast2500_sdrammc_ddr4_calibrate_vref(info); 327 if (ret < 0) { 328 debug("Vref calibration failed!\n"); 329 return ret; 330 } 331 332 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) 333 | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT), 334 &info->regs->refresh_timing); 335 336 setbits_le32(&info->regs->power_control, 337 SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON); 338 339 ast2500_sdrammc_calc_size(info); 340 341 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN); 342 while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE)) 343 ; 344 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN); 345 346 writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control); 347 348 #ifdef CONFIG_ASPEED_ECC 349 ast2500_sdrammc_ecc_enable(info); 350 #endif 351 /* Enable all requests except video & display */ 352 writel(SDRAM_REQ_USB20_EHCI1 353 | SDRAM_REQ_USB20_EHCI2 354 | SDRAM_REQ_CPU 355 | SDRAM_REQ_AHB2 356 | SDRAM_REQ_AHB 357 | SDRAM_REQ_MAC0 358 | SDRAM_REQ_MAC1 359 | SDRAM_REQ_PCIE 360 | SDRAM_REQ_XDMA 361 | SDRAM_REQ_ENCRYPTION 362 | SDRAM_REQ_VIDEO_FLAG 363 | SDRAM_REQ_VIDEO_LOW_PRI_WRITE 364 | SDRAM_REQ_2D_RW 365 | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask); 366 367 return 0; 368 } 369 370 static void ast2500_sdrammc_unlock(struct dram_info *info) 371 { 372 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 373 while (!readl(&info->regs->protection_key)) 374 ; 375 } 376 377 static void ast2500_sdrammc_lock(struct dram_info *info) 378 { 379 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 380 while (readl(&info->regs->protection_key)) 381 ; 382 } 383 384 static int ast2500_sdrammc_probe(struct udevice *dev) 385 { 386 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 387 struct ast2500_sdrammc_regs *regs = priv->regs; 388 struct udevice *clk_dev; 389 int i; 390 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 391 uint32_t reg; 392 393 if (ret) { 394 debug("DDR:No CLK\n"); 395 return ret; 396 } 397 398 /* find the SCU base address from the aspeed clock device */ 399 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 400 &clk_dev); 401 if (ret) { 402 debug("clock device not defined\n"); 403 return ret; 404 } 405 priv->scu = devfdt_get_addr_ptr(clk_dev); 406 407 if (IS_ERR(priv->scu)) { 408 debug("%s(): can't get SCU\n", __func__); 409 return PTR_ERR(priv->scu); 410 } 411 412 if (readl(&priv->scu->vga_handshake[0]) & (0x1 << 6)) { 413 printf("already initialized, "); 414 ast2500_sdrammc_calc_size(priv); 415 416 setbits_le32(&priv->regs->config, SDRAM_CONF_CACHE_INIT_EN); 417 while ( 418 !(readl(&priv->regs->config) & SDRAM_CONF_CACHE_INIT_DONE)) 419 ; 420 setbits_le32(&priv->regs->config, SDRAM_CONF_CACHE_EN); 421 422 writel(SDRAM_MISC_DDR4_TREFRESH, &priv->regs->misc_control); 423 424 #ifdef CONFIG_ASPEED_ECC 425 ast2500_sdrammc_ecc_enable(priv); 426 #endif 427 return 0; 428 } 429 430 #ifdef AST2500_SDRAMMC_MANUAL_CLK 431 reg = readl(&priv->scu->m_pll_param); 432 reg |= (SCU_MPLL_RESET | SCU_MPLL_TURN_OFF); 433 writel(reg, &priv->scu->m_pll_param); 434 reg &= ~(SCU_MPLL_RESET | SCU_MPLL_TURN_OFF| SCU_MPLL_FREQ_MASK); 435 reg |= SCU_MPLL_FREQ_CFG; 436 writel(reg, &priv->scu->m_pll_param); 437 #else 438 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 439 #endif 440 441 ast2500_sdrammc_unlock(priv); 442 443 writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS, 444 ®s->power_control); 445 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 446 447 /* Mask all requests except CPU and AHB during PHY init */ 448 writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask); 449 450 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 451 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 452 453 setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); 454 455 ast2500_sdrammc_init_phy(priv->phy); 456 if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) { 457 ast2500_sdrammc_init_ddr4(priv); 458 } else { 459 debug("Unsupported DRAM3\n"); 460 return -EINVAL; 461 } 462 463 clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); 464 ast2500_sdrammc_lock(priv); 465 466 return 0; 467 } 468 469 static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev) 470 { 471 struct dram_info *priv = dev_get_priv(dev); 472 473 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 474 priv->phy = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 475 476 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 477 "clock-frequency", 0); 478 if (!priv->clock_rate) { 479 debug("DDR Clock Rate not defined\n"); 480 return -EINVAL; 481 } 482 483 return 0; 484 } 485 486 static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 487 { 488 struct dram_info *priv = dev_get_priv(dev); 489 490 *info = priv->info; 491 492 return 0; 493 } 494 495 static struct ram_ops ast2500_sdrammc_ops = { 496 .get_info = ast2500_sdrammc_get_info, 497 }; 498 499 static const struct udevice_id ast2500_sdrammc_ids[] = { 500 { .compatible = "aspeed,ast2500-sdrammc" }, 501 { } 502 }; 503 504 U_BOOT_DRIVER(sdrammc_ast2500) = { 505 .name = "aspeed_ast2500_sdrammc", 506 .id = UCLASS_RAM, 507 .of_match = ast2500_sdrammc_ids, 508 .ops = &ast2500_sdrammc_ops, 509 .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata, 510 .probe = ast2500_sdrammc_probe, 511 .priv_auto_alloc_size = sizeof(struct dram_info), 512 }; 513