183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23335786aSStefan Roese /* 33335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 43335786aSStefan Roese */ 53335786aSStefan Roese 63335786aSStefan Roese #ifndef _COMPHY_HPIPE_H_ 73335786aSStefan Roese #define _COMPHY_HPIPE_H_ 83335786aSStefan Roese 93335786aSStefan Roese /* SerDes IP register */ 103335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_REG 0 113335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 123335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ 133335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) 143335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 153335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ 163335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 173335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 183335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ 193335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 203335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 213335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ 223335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) 233335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 243335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ 253335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) 263335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 273335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ 283335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) 293335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 303335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ 313335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) 323335786aSStefan Roese 333335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_REG 0x4 343335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 353335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ 363335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 373335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 383335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ 393335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 403335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 413335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ 423335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 433335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 443335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ 453335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 463335786aSStefan Roese 473335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_REG 0x8 483335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 493335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ 503335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) 51c01f9fe8SIgal Liberman #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 52c01f9fe8SIgal Liberman #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ 53c01f9fe8SIgal Liberman (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) 543335786aSStefan Roese 553335786aSStefan Roese #define SD_EXTERNAL_STATUS0_REG 0x18 563335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 573335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ 583335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) 593335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 603335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ 613335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) 623335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 633335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ 643335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) 653335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6 663335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ 673335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) 683335786aSStefan Roese 693335786aSStefan Roese /* HPIPE register */ 703335786aSStefan Roese #define HPIPE_PWR_PLL_REG 0x4 713335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 723335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_MASK \ 733335786aSStefan Roese (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) 743335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 753335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_MASK \ 763335786aSStefan Roese (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) 773335786aSStefan Roese 783335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_REG 0x8 793335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 803335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \ 813335786aSStefan Roese (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) 823335786aSStefan Roese 83c0132f60SStefan Roese #define HPIPE_CAL_REG1_REG 0xc 84c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 85c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ 86c0132f60SStefan Roese (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) 87c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 88c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ 89c0132f60SStefan Roese (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) 90c0132f60SStefan Roese 913335786aSStefan Roese #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 923335786aSStefan Roese 933335786aSStefan Roese #define HPIPE_DFE_REG0 0x01C 943335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_OFFSET 15 953335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_MASK \ 963335786aSStefan Roese (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) 973335786aSStefan Roese 983335786aSStefan Roese #define HPIPE_DFE_F3_F5_REG 0x028 993335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 1003335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_MASK \ 1013335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) 1023335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 1033335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ 1043335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) 1053335786aSStefan Roese 1063335786aSStefan Roese #define HPIPE_G1_SET_0_REG 0x034 107c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 108c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ 109c0132f60SStefan Roese (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) 110c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 111c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ 112c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) 1133335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 1143335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ 1153335786aSStefan Roese (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) 116c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 117c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ 118c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) 1193335786aSStefan Roese 1203335786aSStefan Roese #define HPIPE_G1_SET_1_REG 0x038 1213335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 1223335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ 1233335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) 1243335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 1253335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ 1263335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) 127c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 128c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ 129c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) 130c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 131c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ 132c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) 1333335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 1343335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ 1353335786aSStefan Roese (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) 1363335786aSStefan Roese 137c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 138c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ 139c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) 1403335786aSStefan Roese 141c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_REG 0x3c 142c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 143c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ 144c01f9fe8SIgal Liberman (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) 145c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 146c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ 147c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) 148c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 149c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ 150c01f9fe8SIgal Liberman (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) 151c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 152c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ 153c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) 154c01f9fe8SIgal Liberman 155c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_REG 0x040 156c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 157c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ 158c01f9fe8SIgal Liberman (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) 159c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 160c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ 161c01f9fe8SIgal Liberman (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) 162c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 163c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ 164c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) 165c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 166c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ 167c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) 168c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 169c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ 170c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) 171c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 172c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ 173c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) 174c01f9fe8SIgal Liberman 175c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_REG 0x44 176c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 177c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ 178c01f9fe8SIgal Liberman (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) 179c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 180c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ 181c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) 182c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 183c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ 184c01f9fe8SIgal Liberman (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) 185c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 186c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ 187c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) 188c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 189c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ 190c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) 191c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 192c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ 193c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) 194c01f9fe8SIgal Liberman 195c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_REG 0x048 196c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 197c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ 198c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) 199c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 200c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ 201c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) 202c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 203c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ 204c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) 205c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 206c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ 207c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) 208c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 209c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ 210c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) 211c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 212c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ 213c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) 214c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 215c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ 216c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) 2173335786aSStefan Roese 2183335786aSStefan Roese #define HPIPE_LOOPBACK_REG 0x08c 2193335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_OFFSET 1 2203335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_MASK \ 2213335786aSStefan Roese (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) 2223335786aSStefan Roese 2233335786aSStefan Roese #define HPIPE_SYNC_PATTERN_REG 0x090 224*d13b740cSRabeeh Khoury #define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10 225*d13b740cSRabeeh Khoury #define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \ 226*d13b740cSRabeeh Khoury (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET) 227*d13b740cSRabeeh Khoury #define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11 228*d13b740cSRabeeh Khoury #define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \ 229*d13b740cSRabeeh Khoury (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET) 2303335786aSStefan Roese 2313335786aSStefan Roese #define HPIPE_INTERFACE_REG 0x94 2323335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 2333335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_MASK \ 2343335786aSStefan Roese (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) 235ae07a70aSIgal Liberman #define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 236ae07a70aSIgal Liberman #define HPIPE_INTERFACE_DET_BYPASS_MASK \ 237ae07a70aSIgal Liberman (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) 2383335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 2393335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ 2403335786aSStefan Roese (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) 2413335786aSStefan Roese 2423335786aSStefan Roese #define HPIPE_ISOLATE_MODE_REG 0x98 2433335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 2443335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \ 2453335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) 2463335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 2473335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \ 2483335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) 2493335786aSStefan Roese 250c0132f60SStefan Roese #define HPIPE_G1_SET_2_REG 0xf4 251c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 252c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ 253c0132f60SStefan Roese (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) 254c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 255c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ 256c0132f60SStefan Roese (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK) 257c0132f60SStefan Roese 2583335786aSStefan Roese #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 2593335786aSStefan Roese 260c01f9fe8SIgal Liberman #define HPIPE_VDD_CAL_CTRL_REG 0x114 261c01f9fe8SIgal Liberman #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 262c01f9fe8SIgal Liberman #define HPIPE_EXT_SELLV_RXSAMPL_MASK \ 263c01f9fe8SIgal Liberman (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) 264c01f9fe8SIgal Liberman 265781ea0abSIgal Liberman #define HPIPE_VDD_CAL_0_REG 0x108 266781ea0abSIgal Liberman #define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 267781ea0abSIgal Liberman #define HPIPE_CAL_VDD_CONT_MODE_MASK \ 268781ea0abSIgal Liberman (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) 269781ea0abSIgal Liberman 2703335786aSStefan Roese #define HPIPE_PCIE_REG0 0x120 2713335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 2723335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_MASK \ 2733335786aSStefan Roese (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) 2743335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_OFFSET 13 2753335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_MASK \ 2763335786aSStefan Roese (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) 2773335786aSStefan Roese 2783335786aSStefan Roese #define HPIPE_LANE_ALIGN_REG 0x124 2793335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 2803335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_MASK \ 2813335786aSStefan Roese (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) 2823335786aSStefan Roese 2833335786aSStefan Roese #define HPIPE_MISC_REG 0x13C 2843335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_OFFSET 4 2853335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_MASK \ 2863335786aSStefan Roese (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) 287c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_OFFSET 5 288c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_MASK \ 289c0132f60SStefan Roese (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) 2903335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 2913335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_MASK \ 2923335786aSStefan Roese (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) 2933335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_OFFSET 7 2943335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_MASK \ 2953335786aSStefan Roese (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) 2963335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 2973335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_MASK \ 2983335786aSStefan Roese (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) 2993335786aSStefan Roese 3003335786aSStefan Roese #define HPIPE_RX_CONTROL_1_REG 0x140 3013335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 3023335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ 3033335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) 3043335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 3053335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ 3063335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) 3073335786aSStefan Roese 3083335786aSStefan Roese #define HPIPE_PWR_CTR_REG 0x148 3093335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 3103335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_MASK \ 3113335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) 3123335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 3133335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_MASK \ 3143335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) 3153335786aSStefan Roese 316b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_REG 0x154 317781ea0abSIgal Liberman #define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 318781ea0abSIgal Liberman #define HPIPE_TXDIGCK_DIV_FORCE_MASK \ 319781ea0abSIgal Liberman (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) 320b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 321b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ 322b617a0d7SIgal Liberman (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) 323b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 324b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \ 325b617a0d7SIgal Liberman (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) 326b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 327b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \ 328b617a0d7SIgal Liberman (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) 329b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 330b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \ 331b617a0d7SIgal Liberman (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) 332b617a0d7SIgal Liberman 3333335786aSStefan Roese #define HPIPE_PLLINTP_REG1 0x150 3343335786aSStefan Roese 3353335786aSStefan Roese #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C 336781ea0abSIgal Liberman #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 337781ea0abSIgal Liberman #define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ 338781ea0abSIgal Liberman (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) 3393335786aSStefan Roese #define HPIPE_SMAPLER_OFFSET 12 3403335786aSStefan Roese #define HPIPE_SMAPLER_MASK \ 3413335786aSStefan Roese (0x1 << HPIPE_SMAPLER_OFFSET) 3423335786aSStefan Roese 343c0132f60SStefan Roese #define HPIPE_TX_REG1_REG 0x174 344c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 345c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ 346c0132f60SStefan Roese (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) 347c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 348c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_MASK \ 349c0132f60SStefan Roese (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) 350c0132f60SStefan Roese 3513335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_REG 0x184 352c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 353c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ 354c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) 355c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 356c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ 357c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) 3583335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 3593335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ 3603335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) 361c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 362c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ 363c01f9fe8SIgal Liberman (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) 364c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 365c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ 366c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) 367c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 368c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ 369c01f9fe8SIgal Liberman (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) 370c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 371c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ 372c01f9fe8SIgal Liberman (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) 3733335786aSStefan Roese 374c01f9fe8SIgal Liberman #define HPIPE_PHASE_CONTROL_REG 0x188 375c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_OFFSET 0 376c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_MASK \ 377c01f9fe8SIgal Liberman (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) 378c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 379c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_FORCE_MASK \ 380c01f9fe8SIgal Liberman (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) 381c01f9fe8SIgal Liberman #define HPIPE_OS_PH_VALID_OFFSET 8 382c01f9fe8SIgal Liberman #define HPIPE_OS_PH_VALID_MASK \ 383c01f9fe8SIgal Liberman (0x1 << HPIPE_OS_PH_VALID_OFFSET) 3843335786aSStefan Roese 385781ea0abSIgal Liberman #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 386781ea0abSIgal Liberman #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 387781ea0abSIgal Liberman #define HPIPE_TRAIN_PAT_NUM_MASK \ 388781ea0abSIgal Liberman (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) 389781ea0abSIgal Liberman 390781ea0abSIgal Liberman #define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 391781ea0abSIgal Liberman #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 392781ea0abSIgal Liberman #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ 393781ea0abSIgal Liberman (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) 394781ea0abSIgal Liberman 395781ea0abSIgal Liberman #define HPIPE_DME_REG 0x228 396781ea0abSIgal Liberman #define HPIPE_DME_ETHERNET_MODE_OFFSET 7 397781ea0abSIgal Liberman #define HPIPE_DME_ETHERNET_MODE_MASK \ 398781ea0abSIgal Liberman (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) 399781ea0abSIgal Liberman 4003335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 4013335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 4023335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ 4033335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) 4043335786aSStefan Roese 4053335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_REG 0x26C 4063335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 4073335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_MASK \ 4083335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) 4093335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 4103335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ 4113335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) 4123335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 4133335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_MASK \ 4143335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) 4153335786aSStefan Roese 4163335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 4173335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 4183335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_MASK \ 4193335786aSStefan Roese (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) 4203335786aSStefan Roese 4213335786aSStefan Roese #define HPIPE_PCIE_REG1 0x288 4223335786aSStefan Roese #define HPIPE_PCIE_REG3 0x290 4233335786aSStefan Roese 4243335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 425781ea0abSIgal Liberman #define HPIPE_RX_TRAIN_TIMER_OFFSET 0 426781ea0abSIgal Liberman #define HPIPE_RX_TRAIN_TIMER_MASK \ 427781ea0abSIgal Liberman (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) 4283335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 4293335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ 4303335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) 4313335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 4323335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ 4333335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) 4343335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 4353335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ 4363335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) 4373335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 4383335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ 4393335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) 4403335786aSStefan Roese 4413335786aSStefan Roese #define HPIPE_TX_TRAIN_REG 0x31C 4423335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 4433335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_MASK \ 4443335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) 4453335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 4463335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ 4473335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) 448781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 449781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ 450781ea0abSIgal Liberman (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) 451781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 452781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_PAT_SEL_MASK \ 453781ea0abSIgal Liberman (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) 4543335786aSStefan Roese 455ae07a70aSIgal Liberman #define HPIPE_CDR_CONTROL_REG 0x418 456ae07a70aSIgal Liberman #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 457ae07a70aSIgal Liberman #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ 458ae07a70aSIgal Liberman (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) 459ae07a70aSIgal Liberman #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 460ae07a70aSIgal Liberman #define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ 461ae07a70aSIgal Liberman (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) 462ae07a70aSIgal Liberman #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 463ae07a70aSIgal Liberman #define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ 464ae07a70aSIgal Liberman (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) 465ae07a70aSIgal Liberman 4663335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 4673335786aSStefan Roese #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 4683335786aSStefan Roese #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ 4693335786aSStefan Roese (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) 4703335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 4713335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_MASK \ 4723335786aSStefan Roese (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) 4733335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 4743335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ 4753335786aSStefan Roese (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) 4763335786aSStefan Roese 4773335786aSStefan Roese #define HPIPE_G1_SETTINGS_3_REG 0x440 478c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 479c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ 480c01f9fe8SIgal Liberman (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) 481c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 482c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ 483c01f9fe8SIgal Liberman (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) 484c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 485c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ 486c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) 487c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 488c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ 489c0132f60SStefan Roese (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) 490c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 491c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ 492c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) 493c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 494c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ 495c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) 4963335786aSStefan Roese 4973335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_REG 0x444 4983335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 4993335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ 5003335786aSStefan Roese (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) 5013335786aSStefan Roese 5023335786aSStefan Roese #define HPIPE_G2_SETTINGS_3_REG 0x448 503ae07a70aSIgal Liberman 504ae07a70aSIgal Liberman #define HPIPE_G2_SETTINGS_4_REG 0x44c 505ae07a70aSIgal Liberman #define HPIPE_G2_DFE_RES_OFFSET 8 506ae07a70aSIgal Liberman #define HPIPE_G2_DFE_RES_MASK \ 507ae07a70aSIgal Liberman (0x3 << HPIPE_G2_DFE_RES_OFFSET) 5083335786aSStefan Roese 5093335786aSStefan Roese #define HPIPE_G3_SETTING_3_REG 0x450 510c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 511c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_CAP_SEL_MASK \ 512c01f9fe8SIgal Liberman (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) 513c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 514c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_RES_SEL_MASK \ 515c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) 516c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 517c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_SETTING_FORCE_MASK \ 518c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) 5193335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 5203335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ 5213335786aSStefan Roese (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) 5223335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 5233335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ 5243335786aSStefan Roese (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) 5253335786aSStefan Roese 5263335786aSStefan Roese #define HPIPE_G3_SETTING_4_REG 0x454 5273335786aSStefan Roese #define HPIPE_G3_DFE_RES_OFFSET 8 5283335786aSStefan Roese #define HPIPE_G3_DFE_RES_MASK \ 5293335786aSStefan Roese (0x3 << HPIPE_G3_DFE_RES_OFFSET) 5303335786aSStefan Roese 531781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_REG 0x468 532781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_OFFSET 0 533781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_MASK \ 534781ea0abSIgal Liberman (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) 535781ea0abSIgal Liberman 536ae07a70aSIgal Liberman #define HPIPE_DFE_CONTROL_REG 0x470 537ae07a70aSIgal Liberman #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 538ae07a70aSIgal Liberman #define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ 539ae07a70aSIgal Liberman (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) 540ae07a70aSIgal Liberman 5413335786aSStefan Roese #define HPIPE_DFE_CTRL_28_REG 0x49C 5423335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 5433335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ 5443335786aSStefan Roese (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) 5453335786aSStefan Roese 546c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_REG 0x538 547c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 548c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_MASK \ 549c0132f60SStefan Roese (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) 550c0132f60SStefan Roese 551ae07a70aSIgal Liberman #define HPIPE_G3_SETTING_5_REG 0x548 552ae07a70aSIgal Liberman #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 553ae07a70aSIgal Liberman #define HPIPE_G3_SETTING_5_G3_ICP_MASK \ 554ae07a70aSIgal Liberman (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) 555ae07a70aSIgal Liberman 5563335786aSStefan Roese #define HPIPE_LANE_CONFIG0_REG 0x600 5573335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 5583335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ 5593335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) 5603335786aSStefan Roese 5613335786aSStefan Roese #define HPIPE_LANE_CONFIG1_REG 0x604 5623335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9 5633335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \ 5643335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET) 5653335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10 5663335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \ 5673335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET) 5683335786aSStefan Roese 5693335786aSStefan Roese #define HPIPE_LANE_STATUS1_REG 0x60C 5703335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 5713335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ 5723335786aSStefan Roese (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) 5733335786aSStefan Roese 5743335786aSStefan Roese #define HPIPE_LANE_CFG4_REG 0x620 5753335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 5763335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ 5773335786aSStefan Roese (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) 578ae07a70aSIgal Liberman #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 579ae07a70aSIgal Liberman #define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ 580ae07a70aSIgal Liberman (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) 5813335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 5823335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_MASK \ 5833335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) 5843335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 5853335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ 5863335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) 5873335786aSStefan Roese 5883335786aSStefan Roese #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C 5893335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 5903335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_MASK \ 5913335786aSStefan Roese (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) 5923335786aSStefan Roese 5933335786aSStefan Roese #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 5943335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 5953335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_MASK \ 5963335786aSStefan Roese (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) 5973335786aSStefan Roese 598ae07a70aSIgal Liberman #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 599ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 600ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ 601ae07a70aSIgal Liberman (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) 602ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 603ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ 604ae07a70aSIgal Liberman (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) 605ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 606ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ 607ae07a70aSIgal Liberman (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) 608ae07a70aSIgal Liberman 6093335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_REG 0x704 6103335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 6113335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ 6123335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) 6133335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 6143335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ 6153335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) 6163335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 6173335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ 6183335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) 6193335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 6203335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ 6213335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) 6223335786aSStefan Roese 6233335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_REG 0x708 6243335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 6253335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ 6263335786aSStefan Roese (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) 6273335786aSStefan Roese 6283335786aSStefan Roese #define HPIPE_CLK_SRC_LO_REG 0x70c 6293335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 6303335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ 6313335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) 6323335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 6333335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ 6343335786aSStefan Roese (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) 6353335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 6363335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ 6373335786aSStefan Roese (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) 6383335786aSStefan Roese 6393335786aSStefan Roese #define HPIPE_CLK_SRC_HI_REG 0x710 6403335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 6413335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ 6423335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) 6433335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 6443335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ 6453335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) 6463335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 6473335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ 6483335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) 6493335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 6503335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ 6513335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) 6523335786aSStefan Roese 6533335786aSStefan Roese #define HPIPE_GLOBAL_MISC_CTRL 0x718 6543335786aSStefan Roese #define HPIPE_GLOBAL_PM_CTRL 0x740 6553335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 6563335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ 6573335786aSStefan Roese (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) 6583335786aSStefan Roese 6593335786aSStefan Roese #endif /* _COMPHY_HPIPE_H_ */ 6603335786aSStefan Roese 661