13335786aSStefan Roese /* 23335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 33335786aSStefan Roese * 43335786aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 53335786aSStefan Roese */ 63335786aSStefan Roese 73335786aSStefan Roese #ifndef _COMPHY_HPIPE_H_ 83335786aSStefan Roese #define _COMPHY_HPIPE_H_ 93335786aSStefan Roese 103335786aSStefan Roese /* SerDes IP register */ 113335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_REG 0 123335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 133335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ 143335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) 153335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 163335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ 173335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 183335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 193335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ 203335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 213335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 223335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ 233335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) 243335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 253335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ 263335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) 273335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 283335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ 293335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) 303335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 313335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ 323335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) 333335786aSStefan Roese 343335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_REG 0x4 353335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 363335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ 373335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 383335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 393335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ 403335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 413335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 423335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ 433335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 443335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 453335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ 463335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 473335786aSStefan Roese 483335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_REG 0x8 493335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 503335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ 513335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) 52*c01f9fe8SIgal Liberman #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 53*c01f9fe8SIgal Liberman #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ 54*c01f9fe8SIgal Liberman (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) 553335786aSStefan Roese 563335786aSStefan Roese #define SD_EXTERNAL_STATUS0_REG 0x18 573335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 583335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ 593335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) 603335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 613335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ 623335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) 633335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 643335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ 653335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) 663335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6 673335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ 683335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) 693335786aSStefan Roese 703335786aSStefan Roese /* HPIPE register */ 713335786aSStefan Roese #define HPIPE_PWR_PLL_REG 0x4 723335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 733335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_MASK \ 743335786aSStefan Roese (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) 753335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 763335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_MASK \ 773335786aSStefan Roese (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) 783335786aSStefan Roese 793335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_REG 0x8 803335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 813335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \ 823335786aSStefan Roese (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) 833335786aSStefan Roese 84c0132f60SStefan Roese #define HPIPE_CAL_REG1_REG 0xc 85c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 86c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ 87c0132f60SStefan Roese (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) 88c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 89c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ 90c0132f60SStefan Roese (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) 91c0132f60SStefan Roese 923335786aSStefan Roese #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 933335786aSStefan Roese 943335786aSStefan Roese #define HPIPE_DFE_REG0 0x01C 953335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_OFFSET 15 963335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_MASK \ 973335786aSStefan Roese (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) 983335786aSStefan Roese 993335786aSStefan Roese #define HPIPE_DFE_F3_F5_REG 0x028 1003335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 1013335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_MASK \ 1023335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) 1033335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 1043335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ 1053335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) 1063335786aSStefan Roese 1073335786aSStefan Roese #define HPIPE_G1_SET_0_REG 0x034 108c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 109c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ 110c0132f60SStefan Roese (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) 111*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 112*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ 113*c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) 1143335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 1153335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ 1163335786aSStefan Roese (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) 117*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 118*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ 119*c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) 1203335786aSStefan Roese 1213335786aSStefan Roese #define HPIPE_G1_SET_1_REG 0x038 1223335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 1233335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ 1243335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) 1253335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 1263335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ 1273335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) 128*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 129*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ 130*c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) 131*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 132*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ 133*c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) 1343335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 1353335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ 1363335786aSStefan Roese (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) 1373335786aSStefan Roese 138*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 139*c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ 140*c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) 1413335786aSStefan Roese 142*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_REG 0x3c 143*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 144*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ 145*c01f9fe8SIgal Liberman (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) 146*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 147*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ 148*c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) 149*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 150*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ 151*c01f9fe8SIgal Liberman (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) 152*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 153*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ 154*c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) 155*c01f9fe8SIgal Liberman 156*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_REG 0x040 157*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 158*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ 159*c01f9fe8SIgal Liberman (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) 160*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 161*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ 162*c01f9fe8SIgal Liberman (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) 163*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 164*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ 165*c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) 166*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 167*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ 168*c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) 169*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 170*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ 171*c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) 172*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 173*c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ 174*c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) 175*c01f9fe8SIgal Liberman 176*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_REG 0x44 177*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 178*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ 179*c01f9fe8SIgal Liberman (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) 180*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 181*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ 182*c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) 183*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 184*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ 185*c01f9fe8SIgal Liberman (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) 186*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 187*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ 188*c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) 189*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 190*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ 191*c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) 192*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 193*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ 194*c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) 195*c01f9fe8SIgal Liberman 196*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_REG 0x048 197*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 198*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ 199*c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) 200*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 201*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ 202*c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) 203*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 204*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ 205*c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) 206*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 207*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ 208*c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) 209*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 210*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ 211*c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) 212*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 213*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ 214*c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) 215*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 216*c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ 217*c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) 2183335786aSStefan Roese 2193335786aSStefan Roese #define HPIPE_LOOPBACK_REG 0x08c 2203335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_OFFSET 1 2213335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_MASK \ 2223335786aSStefan Roese (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) 2233335786aSStefan Roese 2243335786aSStefan Roese #define HPIPE_SYNC_PATTERN_REG 0x090 2253335786aSStefan Roese 2263335786aSStefan Roese #define HPIPE_INTERFACE_REG 0x94 2273335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 2283335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_MASK \ 2293335786aSStefan Roese (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) 2303335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 2313335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ 2323335786aSStefan Roese (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) 2333335786aSStefan Roese 2343335786aSStefan Roese #define HPIPE_ISOLATE_MODE_REG 0x98 2353335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 2363335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \ 2373335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) 2383335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 2393335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \ 2403335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) 2413335786aSStefan Roese 242c0132f60SStefan Roese #define HPIPE_G1_SET_2_REG 0xf4 243c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 244c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ 245c0132f60SStefan Roese (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) 246c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 247c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ 248c0132f60SStefan Roese (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK) 249c0132f60SStefan Roese 2503335786aSStefan Roese #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 2513335786aSStefan Roese 252*c01f9fe8SIgal Liberman #define HPIPE_VDD_CAL_CTRL_REG 0x114 253*c01f9fe8SIgal Liberman #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 254*c01f9fe8SIgal Liberman #define HPIPE_EXT_SELLV_RXSAMPL_MASK \ 255*c01f9fe8SIgal Liberman (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) 256*c01f9fe8SIgal Liberman 2573335786aSStefan Roese #define HPIPE_PCIE_REG0 0x120 2583335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 2593335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_MASK \ 2603335786aSStefan Roese (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) 2613335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_OFFSET 13 2623335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_MASK \ 2633335786aSStefan Roese (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) 2643335786aSStefan Roese 2653335786aSStefan Roese #define HPIPE_LANE_ALIGN_REG 0x124 2663335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 2673335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_MASK \ 2683335786aSStefan Roese (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) 2693335786aSStefan Roese 2703335786aSStefan Roese #define HPIPE_MISC_REG 0x13C 2713335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_OFFSET 4 2723335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_MASK \ 2733335786aSStefan Roese (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) 274c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_OFFSET 5 275c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_MASK \ 276c0132f60SStefan Roese (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) 2773335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 2783335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_MASK \ 2793335786aSStefan Roese (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) 2803335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_OFFSET 7 2813335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_MASK \ 2823335786aSStefan Roese (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) 2833335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 2843335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_MASK \ 2853335786aSStefan Roese (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) 2863335786aSStefan Roese 2873335786aSStefan Roese #define HPIPE_RX_CONTROL_1_REG 0x140 2883335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 2893335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ 2903335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) 2913335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 2923335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ 2933335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) 2943335786aSStefan Roese 2953335786aSStefan Roese #define HPIPE_PWR_CTR_REG 0x148 2963335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 2973335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_MASK \ 2983335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) 2993335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 3003335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_MASK \ 3013335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) 3023335786aSStefan Roese 3033335786aSStefan Roese #define HPIPE_PLLINTP_REG1 0x150 3043335786aSStefan Roese 3053335786aSStefan Roese #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C 3063335786aSStefan Roese #define HPIPE_SMAPLER_OFFSET 12 3073335786aSStefan Roese #define HPIPE_SMAPLER_MASK \ 3083335786aSStefan Roese (0x1 << HPIPE_SMAPLER_OFFSET) 3093335786aSStefan Roese 310c0132f60SStefan Roese #define HPIPE_TX_REG1_REG 0x174 311c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 312c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ 313c0132f60SStefan Roese (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) 314c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 315c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_MASK \ 316c0132f60SStefan Roese (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) 317c0132f60SStefan Roese 3183335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_REG 0x184 319*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 320*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ 321*c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) 322*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 323*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ 324*c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) 3253335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 3263335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ 3273335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) 328*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 329*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ 330*c01f9fe8SIgal Liberman (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) 331*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 332*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ 333*c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) 334*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 335*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ 336*c01f9fe8SIgal Liberman (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) 337*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 338*c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ 339*c01f9fe8SIgal Liberman (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) 3403335786aSStefan Roese 341*c01f9fe8SIgal Liberman #define HPIPE_PHASE_CONTROL_REG 0x188 342*c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_OFFSET 0 343*c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_MASK \ 344*c01f9fe8SIgal Liberman (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) 345*c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 346*c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_FORCE_MASK \ 347*c01f9fe8SIgal Liberman (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) 348*c01f9fe8SIgal Liberman #define HPIPE_OS_PH_VALID_OFFSET 8 349*c01f9fe8SIgal Liberman #define HPIPE_OS_PH_VALID_MASK \ 350*c01f9fe8SIgal Liberman (0x1 << HPIPE_OS_PH_VALID_OFFSET) 3513335786aSStefan Roese 3523335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 3533335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 3543335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ 3553335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) 3563335786aSStefan Roese 3573335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_REG 0x26C 3583335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 3593335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_MASK \ 3603335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) 3613335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 3623335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ 3633335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) 3643335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 3653335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_MASK \ 3663335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) 3673335786aSStefan Roese 3683335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 3693335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 3703335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_MASK \ 3713335786aSStefan Roese (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) 3723335786aSStefan Roese 3733335786aSStefan Roese #define HPIPE_PCIE_REG1 0x288 3743335786aSStefan Roese #define HPIPE_PCIE_REG3 0x290 3753335786aSStefan Roese 3763335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 3773335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 3783335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ 3793335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) 3803335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 3813335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ 3823335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) 3833335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 3843335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ 3853335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) 3863335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 3873335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ 3883335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) 3893335786aSStefan Roese 3903335786aSStefan Roese #define HPIPE_TX_TRAIN_REG 0x31C 3913335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 3923335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_MASK \ 3933335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) 3943335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 3953335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ 3963335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) 3973335786aSStefan Roese 3983335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 3993335786aSStefan Roese #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 4003335786aSStefan Roese #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ 4013335786aSStefan Roese (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) 4023335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 4033335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_MASK \ 4043335786aSStefan Roese (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) 4053335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 4063335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ 4073335786aSStefan Roese (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) 4083335786aSStefan Roese 4093335786aSStefan Roese #define HPIPE_G1_SETTINGS_3_REG 0x440 410*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 411*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ 412*c01f9fe8SIgal Liberman (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) 413*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 414*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ 415*c01f9fe8SIgal Liberman (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) 416*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 417*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ 418*c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) 419c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 420c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ 421c0132f60SStefan Roese (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) 422*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 423*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ 424*c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) 425*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 426*c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ 427*c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) 4283335786aSStefan Roese 4293335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_REG 0x444 4303335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 4313335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ 4323335786aSStefan Roese (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) 4333335786aSStefan Roese 4343335786aSStefan Roese #define HPIPE_G2_SETTINGS_3_REG 0x448 4353335786aSStefan Roese #define HPIPE_G2_SETTINGS_4_REG 0x44C 4363335786aSStefan Roese 4373335786aSStefan Roese #define HPIPE_G3_SETTING_3_REG 0x450 438*c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 439*c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_CAP_SEL_MASK \ 440*c01f9fe8SIgal Liberman (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) 441*c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 442*c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_RES_SEL_MASK \ 443*c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) 444*c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 445*c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_SETTING_FORCE_MASK \ 446*c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) 4473335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 4483335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ 4493335786aSStefan Roese (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) 4503335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 4513335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ 4523335786aSStefan Roese (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) 4533335786aSStefan Roese 4543335786aSStefan Roese #define HPIPE_G3_SETTING_4_REG 0x454 4553335786aSStefan Roese #define HPIPE_G3_DFE_RES_OFFSET 8 4563335786aSStefan Roese #define HPIPE_G3_DFE_RES_MASK \ 4573335786aSStefan Roese (0x3 << HPIPE_G3_DFE_RES_OFFSET) 4583335786aSStefan Roese 4593335786aSStefan Roese #define HPIPE_DFE_CTRL_28_REG 0x49C 4603335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 4613335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ 4623335786aSStefan Roese (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) 4633335786aSStefan Roese 464c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_REG 0x538 465c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 466c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_MASK \ 467c0132f60SStefan Roese (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) 468c0132f60SStefan Roese 4693335786aSStefan Roese #define HPIPE_LANE_CONFIG0_REG 0x600 4703335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 4713335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ 4723335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) 4733335786aSStefan Roese 4743335786aSStefan Roese #define HPIPE_LANE_CONFIG1_REG 0x604 4753335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9 4763335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \ 4773335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET) 4783335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10 4793335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \ 4803335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET) 4813335786aSStefan Roese 4823335786aSStefan Roese #define HPIPE_LANE_STATUS1_REG 0x60C 4833335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 4843335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ 4853335786aSStefan Roese (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) 4863335786aSStefan Roese 4873335786aSStefan Roese #define HPIPE_LANE_CFG4_REG 0x620 4883335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 4893335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ 4903335786aSStefan Roese (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) 4913335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 4923335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_MASK \ 4933335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) 4943335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 4953335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ 4963335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) 4973335786aSStefan Roese 4983335786aSStefan Roese #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C 4993335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 5003335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_MASK \ 5013335786aSStefan Roese (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) 5023335786aSStefan Roese 5033335786aSStefan Roese #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 5043335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 5053335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_MASK \ 5063335786aSStefan Roese (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) 5073335786aSStefan Roese 5083335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_REG 0x704 5093335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 5103335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ 5113335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) 5123335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 5133335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ 5143335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) 5153335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 5163335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ 5173335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) 5183335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 5193335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ 5203335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) 5213335786aSStefan Roese 5223335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_REG 0x708 5233335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 5243335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ 5253335786aSStefan Roese (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) 5263335786aSStefan Roese 5273335786aSStefan Roese #define HPIPE_CLK_SRC_LO_REG 0x70c 5283335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 5293335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ 5303335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) 5313335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 5323335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ 5333335786aSStefan Roese (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) 5343335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 5353335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ 5363335786aSStefan Roese (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) 5373335786aSStefan Roese 5383335786aSStefan Roese #define HPIPE_CLK_SRC_HI_REG 0x710 5393335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 5403335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ 5413335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) 5423335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 5433335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ 5443335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) 5453335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 5463335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ 5473335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) 5483335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 5493335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ 5503335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) 5513335786aSStefan Roese 5523335786aSStefan Roese #define HPIPE_GLOBAL_MISC_CTRL 0x718 5533335786aSStefan Roese #define HPIPE_GLOBAL_PM_CTRL 0x740 5543335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 5553335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ 5563335786aSStefan Roese (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) 5573335786aSStefan Roese 5583335786aSStefan Roese #endif /* _COMPHY_HPIPE_H_ */ 5593335786aSStefan Roese 560