13335786aSStefan Roese /* 23335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 33335786aSStefan Roese * 43335786aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 53335786aSStefan Roese */ 63335786aSStefan Roese 73335786aSStefan Roese #ifndef _COMPHY_HPIPE_H_ 83335786aSStefan Roese #define _COMPHY_HPIPE_H_ 93335786aSStefan Roese 103335786aSStefan Roese /* SerDes IP register */ 113335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_REG 0 123335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 133335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ 143335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) 153335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 163335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ 173335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 183335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 193335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ 203335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 213335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 223335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ 233335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) 243335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 253335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ 263335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) 273335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 283335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ 293335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) 303335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 313335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ 323335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) 333335786aSStefan Roese 343335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_REG 0x4 353335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 363335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ 373335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 383335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 393335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ 403335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 413335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 423335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ 433335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 443335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 453335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ 463335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 473335786aSStefan Roese 483335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_REG 0x8 493335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 503335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ 513335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) 523335786aSStefan Roese 533335786aSStefan Roese #define SD_EXTERNAL_STATUS0_REG 0x18 543335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 553335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ 563335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) 573335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 583335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ 593335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) 603335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 613335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ 623335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) 633335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6 643335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ 653335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) 663335786aSStefan Roese 673335786aSStefan Roese /* HPIPE register */ 683335786aSStefan Roese #define HPIPE_PWR_PLL_REG 0x4 693335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 703335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_MASK \ 713335786aSStefan Roese (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) 723335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 733335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_MASK \ 743335786aSStefan Roese (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) 753335786aSStefan Roese 763335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_REG 0x8 773335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 783335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \ 793335786aSStefan Roese (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) 803335786aSStefan Roese 81*c0132f60SStefan Roese #define HPIPE_CAL_REG1_REG 0xc 82*c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 83*c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ 84*c0132f60SStefan Roese (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) 85*c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 86*c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ 87*c0132f60SStefan Roese (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) 88*c0132f60SStefan Roese 893335786aSStefan Roese #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 903335786aSStefan Roese 913335786aSStefan Roese #define HPIPE_DFE_REG0 0x01C 923335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_OFFSET 15 933335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_MASK \ 943335786aSStefan Roese (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) 953335786aSStefan Roese 963335786aSStefan Roese #define HPIPE_DFE_F3_F5_REG 0x028 973335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 983335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_MASK \ 993335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) 1003335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 1013335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ 1023335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) 1033335786aSStefan Roese 1043335786aSStefan Roese #define HPIPE_G1_SET_0_REG 0x034 105*c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 106*c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ 107*c0132f60SStefan Roese (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) 1083335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 1093335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ 1103335786aSStefan Roese (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) 1113335786aSStefan Roese 1123335786aSStefan Roese #define HPIPE_G1_SET_1_REG 0x038 1133335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 1143335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ 1153335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) 1163335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 1173335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ 1183335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) 1193335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 1203335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ 1213335786aSStefan Roese (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) 1223335786aSStefan Roese 1233335786aSStefan Roese #define HPIPE_G2_SETTINGS_1_REG 0x040 1243335786aSStefan Roese 1253335786aSStefan Roese #define HPIPE_G3_SETTINGS_1_REG 0x048 1263335786aSStefan Roese #define HPIPE_G3_RX_SELMUPI_OFFSET 0 1273335786aSStefan Roese #define HPIPE_G3_RX_SELMUPI_MASK \ 1283335786aSStefan Roese (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) 1293335786aSStefan Roese #define HPIPE_G3_RX_SELMUPF_OFFSET 3 1303335786aSStefan Roese #define HPIPE_G3_RX_SELMUPF_MASK \ 1313335786aSStefan Roese (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) 1323335786aSStefan Roese #define HPIPE_G3_SETTING_BIT_OFFSET 13 1333335786aSStefan Roese #define HPIPE_G3_SETTING_BIT_MASK \ 1343335786aSStefan Roese (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) 1353335786aSStefan Roese 1363335786aSStefan Roese #define HPIPE_LOOPBACK_REG 0x08c 1373335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_OFFSET 1 1383335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_MASK \ 1393335786aSStefan Roese (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) 1403335786aSStefan Roese 1413335786aSStefan Roese #define HPIPE_SYNC_PATTERN_REG 0x090 1423335786aSStefan Roese 1433335786aSStefan Roese #define HPIPE_INTERFACE_REG 0x94 1443335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 1453335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_MASK \ 1463335786aSStefan Roese (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) 1473335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 1483335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ 1493335786aSStefan Roese (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) 1503335786aSStefan Roese 1513335786aSStefan Roese #define HPIPE_ISOLATE_MODE_REG 0x98 1523335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 1533335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \ 1543335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) 1553335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 1563335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \ 1573335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) 1583335786aSStefan Roese 159*c0132f60SStefan Roese #define HPIPE_G1_SET_2_REG 0xf4 160*c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 161*c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ 162*c0132f60SStefan Roese (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) 163*c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 164*c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ 165*c0132f60SStefan Roese (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK) 166*c0132f60SStefan Roese 1673335786aSStefan Roese #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 1683335786aSStefan Roese 1693335786aSStefan Roese #define HPIPE_PCIE_REG0 0x120 1703335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 1713335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_MASK \ 1723335786aSStefan Roese (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) 1733335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_OFFSET 13 1743335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_MASK \ 1753335786aSStefan Roese (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) 1763335786aSStefan Roese 1773335786aSStefan Roese #define HPIPE_LANE_ALIGN_REG 0x124 1783335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 1793335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_MASK \ 1803335786aSStefan Roese (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) 1813335786aSStefan Roese 1823335786aSStefan Roese #define HPIPE_MISC_REG 0x13C 1833335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_OFFSET 4 1843335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_MASK \ 1853335786aSStefan Roese (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) 186*c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_OFFSET 5 187*c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_MASK \ 188*c0132f60SStefan Roese (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) 1893335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 1903335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_MASK \ 1913335786aSStefan Roese (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) 1923335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_OFFSET 7 1933335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_MASK \ 1943335786aSStefan Roese (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) 1953335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 1963335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_MASK \ 1973335786aSStefan Roese (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) 1983335786aSStefan Roese 1993335786aSStefan Roese #define HPIPE_RX_CONTROL_1_REG 0x140 2003335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 2013335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ 2023335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) 2033335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 2043335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ 2053335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) 2063335786aSStefan Roese 2073335786aSStefan Roese #define HPIPE_PWR_CTR_REG 0x148 2083335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 2093335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_MASK \ 2103335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) 2113335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 2123335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_MASK \ 2133335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) 2143335786aSStefan Roese 2153335786aSStefan Roese #define HPIPE_PLLINTP_REG1 0x150 2163335786aSStefan Roese 2173335786aSStefan Roese #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C 2183335786aSStefan Roese #define HPIPE_SMAPLER_OFFSET 12 2193335786aSStefan Roese #define HPIPE_SMAPLER_MASK \ 2203335786aSStefan Roese (0x1 << HPIPE_SMAPLER_OFFSET) 2213335786aSStefan Roese 222*c0132f60SStefan Roese #define HPIPE_TX_REG1_REG 0x174 223*c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 224*c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ 225*c0132f60SStefan Roese (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) 226*c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 227*c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_MASK \ 228*c0132f60SStefan Roese (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) 229*c0132f60SStefan Roese 2303335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_REG 0x184 2313335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 2323335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ 2333335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) 2343335786aSStefan Roese 2353335786aSStefan Roese #define HPIPE_RX_REG3 0x188 2363335786aSStefan Roese 2373335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 2383335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 2393335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ 2403335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) 2413335786aSStefan Roese 2423335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_REG 0x26C 2433335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 2443335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_MASK \ 2453335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) 2463335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 2473335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ 2483335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) 2493335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 2503335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_MASK \ 2513335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) 2523335786aSStefan Roese 2533335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 2543335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 2553335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_MASK \ 2563335786aSStefan Roese (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) 2573335786aSStefan Roese 2583335786aSStefan Roese #define HPIPE_PCIE_REG1 0x288 2593335786aSStefan Roese #define HPIPE_PCIE_REG3 0x290 2603335786aSStefan Roese 2613335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 2623335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 2633335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ 2643335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) 2653335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 2663335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ 2673335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) 2683335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 2693335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ 2703335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) 2713335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 2723335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ 2733335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) 2743335786aSStefan Roese 2753335786aSStefan Roese #define HPIPE_TX_TRAIN_REG 0x31C 2763335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 2773335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_MASK \ 2783335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) 2793335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 2803335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ 2813335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) 2823335786aSStefan Roese 2833335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 2843335786aSStefan Roese #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 2853335786aSStefan Roese #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ 2863335786aSStefan Roese (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) 2873335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 2883335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_MASK \ 2893335786aSStefan Roese (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) 2903335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 2913335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ 2923335786aSStefan Roese (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) 2933335786aSStefan Roese 2943335786aSStefan Roese #define HPIPE_G1_SETTINGS_3_REG 0x440 295*c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 296*c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ 297*c0132f60SStefan Roese (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) 2983335786aSStefan Roese 2993335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_REG 0x444 3003335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 3013335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ 3023335786aSStefan Roese (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) 3033335786aSStefan Roese 3043335786aSStefan Roese #define HPIPE_G2_SETTINGS_3_REG 0x448 3053335786aSStefan Roese #define HPIPE_G2_SETTINGS_4_REG 0x44C 3063335786aSStefan Roese 3073335786aSStefan Roese #define HPIPE_G3_SETTING_3_REG 0x450 3083335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 3093335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ 3103335786aSStefan Roese (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) 3113335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 3123335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ 3133335786aSStefan Roese (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) 3143335786aSStefan Roese 3153335786aSStefan Roese #define HPIPE_G3_SETTING_4_REG 0x454 3163335786aSStefan Roese #define HPIPE_G3_DFE_RES_OFFSET 8 3173335786aSStefan Roese #define HPIPE_G3_DFE_RES_MASK \ 3183335786aSStefan Roese (0x3 << HPIPE_G3_DFE_RES_OFFSET) 3193335786aSStefan Roese 3203335786aSStefan Roese #define HPIPE_DFE_CTRL_28_REG 0x49C 3213335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 3223335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ 3233335786aSStefan Roese (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) 3243335786aSStefan Roese 325*c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_REG 0x538 326*c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 327*c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_MASK \ 328*c0132f60SStefan Roese (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) 329*c0132f60SStefan Roese 3303335786aSStefan Roese #define HPIPE_LANE_CONFIG0_REG 0x600 3313335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 3323335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ 3333335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) 3343335786aSStefan Roese 3353335786aSStefan Roese #define HPIPE_LANE_CONFIG1_REG 0x604 3363335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9 3373335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \ 3383335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET) 3393335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10 3403335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \ 3413335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET) 3423335786aSStefan Roese 3433335786aSStefan Roese #define HPIPE_LANE_STATUS1_REG 0x60C 3443335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 3453335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ 3463335786aSStefan Roese (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) 3473335786aSStefan Roese 3483335786aSStefan Roese #define HPIPE_LANE_CFG4_REG 0x620 3493335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 3503335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ 3513335786aSStefan Roese (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) 3523335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 3533335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_MASK \ 3543335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) 3553335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 3563335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ 3573335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) 3583335786aSStefan Roese 3593335786aSStefan Roese #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C 3603335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 3613335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_MASK \ 3623335786aSStefan Roese (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) 3633335786aSStefan Roese 3643335786aSStefan Roese #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 3653335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 3663335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_MASK \ 3673335786aSStefan Roese (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) 3683335786aSStefan Roese 3693335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_REG 0x704 3703335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 3713335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ 3723335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) 3733335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 3743335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ 3753335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) 3763335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 3773335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ 3783335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) 3793335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 3803335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ 3813335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) 3823335786aSStefan Roese 3833335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_REG 0x708 3843335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 3853335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ 3863335786aSStefan Roese (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) 3873335786aSStefan Roese 3883335786aSStefan Roese #define HPIPE_CLK_SRC_LO_REG 0x70c 3893335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 3903335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ 3913335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) 3923335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 3933335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ 3943335786aSStefan Roese (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) 3953335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 3963335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ 3973335786aSStefan Roese (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) 3983335786aSStefan Roese 3993335786aSStefan Roese #define HPIPE_CLK_SRC_HI_REG 0x710 4003335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 4013335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ 4023335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) 4033335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 4043335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ 4053335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) 4063335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 4073335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ 4083335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) 4093335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 4103335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ 4113335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) 4123335786aSStefan Roese 4133335786aSStefan Roese #define HPIPE_GLOBAL_MISC_CTRL 0x718 4143335786aSStefan Roese #define HPIPE_GLOBAL_PM_CTRL 0x740 4153335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 4163335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ 4173335786aSStefan Roese (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) 4183335786aSStefan Roese 4193335786aSStefan Roese #endif /* _COMPHY_HPIPE_H_ */ 4203335786aSStefan Roese 421