13335786aSStefan Roese /* 23335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 33335786aSStefan Roese * 43335786aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 53335786aSStefan Roese */ 63335786aSStefan Roese 73335786aSStefan Roese #ifndef _COMPHY_HPIPE_H_ 83335786aSStefan Roese #define _COMPHY_HPIPE_H_ 93335786aSStefan Roese 103335786aSStefan Roese /* SerDes IP register */ 113335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_REG 0 123335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 133335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ 143335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) 153335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 163335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ 173335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 183335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 193335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ 203335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 213335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 223335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ 233335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) 243335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 253335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ 263335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) 273335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 283335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ 293335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) 303335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 313335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ 323335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) 333335786aSStefan Roese 343335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_REG 0x4 353335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 363335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ 373335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 383335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 393335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ 403335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 413335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 423335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ 433335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 443335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 453335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ 463335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 473335786aSStefan Roese 483335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_REG 0x8 493335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 503335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ 513335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) 52c01f9fe8SIgal Liberman #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 53c01f9fe8SIgal Liberman #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ 54c01f9fe8SIgal Liberman (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) 553335786aSStefan Roese 563335786aSStefan Roese #define SD_EXTERNAL_STATUS0_REG 0x18 573335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 583335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ 593335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) 603335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 613335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ 623335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) 633335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 643335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ 653335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) 663335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6 673335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ 683335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) 693335786aSStefan Roese 703335786aSStefan Roese /* HPIPE register */ 713335786aSStefan Roese #define HPIPE_PWR_PLL_REG 0x4 723335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 733335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_MASK \ 743335786aSStefan Roese (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) 753335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 763335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_MASK \ 773335786aSStefan Roese (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) 783335786aSStefan Roese 793335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_REG 0x8 803335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 813335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \ 823335786aSStefan Roese (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) 833335786aSStefan Roese 84c0132f60SStefan Roese #define HPIPE_CAL_REG1_REG 0xc 85c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 86c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ 87c0132f60SStefan Roese (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) 88c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 89c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ 90c0132f60SStefan Roese (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) 91c0132f60SStefan Roese 923335786aSStefan Roese #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 933335786aSStefan Roese 943335786aSStefan Roese #define HPIPE_DFE_REG0 0x01C 953335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_OFFSET 15 963335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_MASK \ 973335786aSStefan Roese (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) 983335786aSStefan Roese 993335786aSStefan Roese #define HPIPE_DFE_F3_F5_REG 0x028 1003335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 1013335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_MASK \ 1023335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) 1033335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 1043335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ 1053335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) 1063335786aSStefan Roese 1073335786aSStefan Roese #define HPIPE_G1_SET_0_REG 0x034 108c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 109c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ 110c0132f60SStefan Roese (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) 111c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 112c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ 113c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) 1143335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 1153335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ 1163335786aSStefan Roese (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) 117c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 118c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ 119c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) 1203335786aSStefan Roese 1213335786aSStefan Roese #define HPIPE_G1_SET_1_REG 0x038 1223335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 1233335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ 1243335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) 1253335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 1263335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ 1273335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) 128c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 129c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ 130c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) 131c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 132c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ 133c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) 1343335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 1353335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ 1363335786aSStefan Roese (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) 1373335786aSStefan Roese 138c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 139c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ 140c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) 1413335786aSStefan Roese 142c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_REG 0x3c 143c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 144c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ 145c01f9fe8SIgal Liberman (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) 146c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 147c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ 148c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) 149c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 150c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ 151c01f9fe8SIgal Liberman (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) 152c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 153c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ 154c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) 155c01f9fe8SIgal Liberman 156c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_REG 0x040 157c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 158c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ 159c01f9fe8SIgal Liberman (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) 160c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 161c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ 162c01f9fe8SIgal Liberman (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) 163c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 164c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ 165c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) 166c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 167c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ 168c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) 169c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 170c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ 171c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) 172c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 173c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ 174c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) 175c01f9fe8SIgal Liberman 176c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_REG 0x44 177c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 178c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ 179c01f9fe8SIgal Liberman (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) 180c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 181c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ 182c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) 183c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 184c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ 185c01f9fe8SIgal Liberman (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) 186c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 187c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ 188c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) 189c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 190c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ 191c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) 192c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 193c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ 194c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) 195c01f9fe8SIgal Liberman 196c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_REG 0x048 197c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 198c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ 199c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) 200c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 201c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ 202c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) 203c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 204c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ 205c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) 206c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 207c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ 208c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) 209c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 210c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ 211c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) 212c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 213c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ 214c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) 215c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 216c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ 217c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) 2183335786aSStefan Roese 2193335786aSStefan Roese #define HPIPE_LOOPBACK_REG 0x08c 2203335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_OFFSET 1 2213335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_MASK \ 2223335786aSStefan Roese (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) 2233335786aSStefan Roese 2243335786aSStefan Roese #define HPIPE_SYNC_PATTERN_REG 0x090 2253335786aSStefan Roese 2263335786aSStefan Roese #define HPIPE_INTERFACE_REG 0x94 2273335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 2283335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_MASK \ 2293335786aSStefan Roese (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) 230*ae07a70aSIgal Liberman #define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 231*ae07a70aSIgal Liberman #define HPIPE_INTERFACE_DET_BYPASS_MASK \ 232*ae07a70aSIgal Liberman (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) 2333335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 2343335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ 2353335786aSStefan Roese (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) 2363335786aSStefan Roese 2373335786aSStefan Roese #define HPIPE_ISOLATE_MODE_REG 0x98 2383335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 2393335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \ 2403335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) 2413335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 2423335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \ 2433335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) 2443335786aSStefan Roese 245c0132f60SStefan Roese #define HPIPE_G1_SET_2_REG 0xf4 246c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 247c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ 248c0132f60SStefan Roese (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) 249c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 250c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ 251c0132f60SStefan Roese (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK) 252c0132f60SStefan Roese 2533335786aSStefan Roese #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 2543335786aSStefan Roese 255c01f9fe8SIgal Liberman #define HPIPE_VDD_CAL_CTRL_REG 0x114 256c01f9fe8SIgal Liberman #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 257c01f9fe8SIgal Liberman #define HPIPE_EXT_SELLV_RXSAMPL_MASK \ 258c01f9fe8SIgal Liberman (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) 259c01f9fe8SIgal Liberman 260781ea0abSIgal Liberman #define HPIPE_VDD_CAL_0_REG 0x108 261781ea0abSIgal Liberman #define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 262781ea0abSIgal Liberman #define HPIPE_CAL_VDD_CONT_MODE_MASK \ 263781ea0abSIgal Liberman (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) 264781ea0abSIgal Liberman 2653335786aSStefan Roese #define HPIPE_PCIE_REG0 0x120 2663335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 2673335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_MASK \ 2683335786aSStefan Roese (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) 2693335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_OFFSET 13 2703335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_MASK \ 2713335786aSStefan Roese (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) 2723335786aSStefan Roese 2733335786aSStefan Roese #define HPIPE_LANE_ALIGN_REG 0x124 2743335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 2753335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_MASK \ 2763335786aSStefan Roese (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) 2773335786aSStefan Roese 2783335786aSStefan Roese #define HPIPE_MISC_REG 0x13C 2793335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_OFFSET 4 2803335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_MASK \ 2813335786aSStefan Roese (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) 282c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_OFFSET 5 283c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_MASK \ 284c0132f60SStefan Roese (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) 2853335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 2863335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_MASK \ 2873335786aSStefan Roese (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) 2883335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_OFFSET 7 2893335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_MASK \ 2903335786aSStefan Roese (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) 2913335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 2923335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_MASK \ 2933335786aSStefan Roese (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) 2943335786aSStefan Roese 2953335786aSStefan Roese #define HPIPE_RX_CONTROL_1_REG 0x140 2963335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 2973335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ 2983335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) 2993335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 3003335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ 3013335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) 3023335786aSStefan Roese 3033335786aSStefan Roese #define HPIPE_PWR_CTR_REG 0x148 3043335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 3053335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_MASK \ 3063335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) 3073335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 3083335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_MASK \ 3093335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) 3103335786aSStefan Roese 311b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_REG 0x154 312781ea0abSIgal Liberman #define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 313781ea0abSIgal Liberman #define HPIPE_TXDIGCK_DIV_FORCE_MASK \ 314781ea0abSIgal Liberman (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) 315b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 316b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ 317b617a0d7SIgal Liberman (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) 318b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 319b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \ 320b617a0d7SIgal Liberman (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) 321b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 322b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \ 323b617a0d7SIgal Liberman (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) 324b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 325b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \ 326b617a0d7SIgal Liberman (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) 327b617a0d7SIgal Liberman 3283335786aSStefan Roese #define HPIPE_PLLINTP_REG1 0x150 3293335786aSStefan Roese 3303335786aSStefan Roese #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C 331781ea0abSIgal Liberman #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 332781ea0abSIgal Liberman #define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ 333781ea0abSIgal Liberman (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) 3343335786aSStefan Roese #define HPIPE_SMAPLER_OFFSET 12 3353335786aSStefan Roese #define HPIPE_SMAPLER_MASK \ 3363335786aSStefan Roese (0x1 << HPIPE_SMAPLER_OFFSET) 3373335786aSStefan Roese 338c0132f60SStefan Roese #define HPIPE_TX_REG1_REG 0x174 339c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 340c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ 341c0132f60SStefan Roese (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) 342c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 343c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_MASK \ 344c0132f60SStefan Roese (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) 345c0132f60SStefan Roese 3463335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_REG 0x184 347c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 348c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ 349c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) 350c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 351c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ 352c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) 3533335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 3543335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ 3553335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) 356c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 357c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ 358c01f9fe8SIgal Liberman (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) 359c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 360c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ 361c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) 362c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 363c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ 364c01f9fe8SIgal Liberman (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) 365c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 366c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ 367c01f9fe8SIgal Liberman (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) 3683335786aSStefan Roese 369c01f9fe8SIgal Liberman #define HPIPE_PHASE_CONTROL_REG 0x188 370c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_OFFSET 0 371c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_MASK \ 372c01f9fe8SIgal Liberman (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) 373c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 374c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_FORCE_MASK \ 375c01f9fe8SIgal Liberman (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) 376c01f9fe8SIgal Liberman #define HPIPE_OS_PH_VALID_OFFSET 8 377c01f9fe8SIgal Liberman #define HPIPE_OS_PH_VALID_MASK \ 378c01f9fe8SIgal Liberman (0x1 << HPIPE_OS_PH_VALID_OFFSET) 3793335786aSStefan Roese 380781ea0abSIgal Liberman #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 381781ea0abSIgal Liberman #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 382781ea0abSIgal Liberman #define HPIPE_TRAIN_PAT_NUM_MASK \ 383781ea0abSIgal Liberman (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) 384781ea0abSIgal Liberman 385781ea0abSIgal Liberman #define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 386781ea0abSIgal Liberman #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 387781ea0abSIgal Liberman #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ 388781ea0abSIgal Liberman (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) 389781ea0abSIgal Liberman 390781ea0abSIgal Liberman #define HPIPE_DME_REG 0x228 391781ea0abSIgal Liberman #define HPIPE_DME_ETHERNET_MODE_OFFSET 7 392781ea0abSIgal Liberman #define HPIPE_DME_ETHERNET_MODE_MASK \ 393781ea0abSIgal Liberman (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) 394781ea0abSIgal Liberman 3953335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 3963335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 3973335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ 3983335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) 3993335786aSStefan Roese 4003335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_REG 0x26C 4013335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 4023335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_MASK \ 4033335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) 4043335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 4053335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ 4063335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) 4073335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 4083335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_MASK \ 4093335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) 4103335786aSStefan Roese 4113335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 4123335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 4133335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_MASK \ 4143335786aSStefan Roese (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) 4153335786aSStefan Roese 4163335786aSStefan Roese #define HPIPE_PCIE_REG1 0x288 4173335786aSStefan Roese #define HPIPE_PCIE_REG3 0x290 4183335786aSStefan Roese 4193335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 420781ea0abSIgal Liberman #define HPIPE_RX_TRAIN_TIMER_OFFSET 0 421781ea0abSIgal Liberman #define HPIPE_RX_TRAIN_TIMER_MASK \ 422781ea0abSIgal Liberman (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) 4233335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 4243335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ 4253335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) 4263335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 4273335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ 4283335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) 4293335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 4303335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ 4313335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) 4323335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 4333335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ 4343335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) 4353335786aSStefan Roese 4363335786aSStefan Roese #define HPIPE_TX_TRAIN_REG 0x31C 4373335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 4383335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_MASK \ 4393335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) 4403335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 4413335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ 4423335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) 443781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 444781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ 445781ea0abSIgal Liberman (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) 446781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 447781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_PAT_SEL_MASK \ 448781ea0abSIgal Liberman (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) 4493335786aSStefan Roese 450*ae07a70aSIgal Liberman #define HPIPE_CDR_CONTROL_REG 0x418 451*ae07a70aSIgal Liberman #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 452*ae07a70aSIgal Liberman #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ 453*ae07a70aSIgal Liberman (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) 454*ae07a70aSIgal Liberman #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 455*ae07a70aSIgal Liberman #define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ 456*ae07a70aSIgal Liberman (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) 457*ae07a70aSIgal Liberman #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 458*ae07a70aSIgal Liberman #define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ 459*ae07a70aSIgal Liberman (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) 460*ae07a70aSIgal Liberman 4613335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 4623335786aSStefan Roese #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 4633335786aSStefan Roese #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ 4643335786aSStefan Roese (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) 4653335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 4663335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_MASK \ 4673335786aSStefan Roese (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) 4683335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 4693335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ 4703335786aSStefan Roese (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) 4713335786aSStefan Roese 4723335786aSStefan Roese #define HPIPE_G1_SETTINGS_3_REG 0x440 473c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 474c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ 475c01f9fe8SIgal Liberman (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) 476c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 477c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ 478c01f9fe8SIgal Liberman (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) 479c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 480c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ 481c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) 482c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 483c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ 484c0132f60SStefan Roese (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) 485c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 486c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ 487c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) 488c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 489c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ 490c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) 4913335786aSStefan Roese 4923335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_REG 0x444 4933335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 4943335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ 4953335786aSStefan Roese (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) 4963335786aSStefan Roese 4973335786aSStefan Roese #define HPIPE_G2_SETTINGS_3_REG 0x448 498*ae07a70aSIgal Liberman 499*ae07a70aSIgal Liberman #define HPIPE_G2_SETTINGS_4_REG 0x44c 500*ae07a70aSIgal Liberman #define HPIPE_G2_DFE_RES_OFFSET 8 501*ae07a70aSIgal Liberman #define HPIPE_G2_DFE_RES_MASK \ 502*ae07a70aSIgal Liberman (0x3 << HPIPE_G2_DFE_RES_OFFSET) 5033335786aSStefan Roese 5043335786aSStefan Roese #define HPIPE_G3_SETTING_3_REG 0x450 505c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 506c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_CAP_SEL_MASK \ 507c01f9fe8SIgal Liberman (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) 508c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 509c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_RES_SEL_MASK \ 510c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) 511c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 512c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_SETTING_FORCE_MASK \ 513c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) 5143335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 5153335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ 5163335786aSStefan Roese (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) 5173335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 5183335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ 5193335786aSStefan Roese (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) 5203335786aSStefan Roese 5213335786aSStefan Roese #define HPIPE_G3_SETTING_4_REG 0x454 5223335786aSStefan Roese #define HPIPE_G3_DFE_RES_OFFSET 8 5233335786aSStefan Roese #define HPIPE_G3_DFE_RES_MASK \ 5243335786aSStefan Roese (0x3 << HPIPE_G3_DFE_RES_OFFSET) 5253335786aSStefan Roese 526781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_REG 0x468 527781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_OFFSET 0 528781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_MASK \ 529781ea0abSIgal Liberman (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) 530781ea0abSIgal Liberman 531*ae07a70aSIgal Liberman #define HPIPE_DFE_CONTROL_REG 0x470 532*ae07a70aSIgal Liberman #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 533*ae07a70aSIgal Liberman #define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ 534*ae07a70aSIgal Liberman (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) 535*ae07a70aSIgal Liberman 5363335786aSStefan Roese #define HPIPE_DFE_CTRL_28_REG 0x49C 5373335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 5383335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ 5393335786aSStefan Roese (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) 5403335786aSStefan Roese 541c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_REG 0x538 542c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 543c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_MASK \ 544c0132f60SStefan Roese (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) 545c0132f60SStefan Roese 546*ae07a70aSIgal Liberman #define HPIPE_G3_SETTING_5_REG 0x548 547*ae07a70aSIgal Liberman #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 548*ae07a70aSIgal Liberman #define HPIPE_G3_SETTING_5_G3_ICP_MASK \ 549*ae07a70aSIgal Liberman (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) 550*ae07a70aSIgal Liberman 5513335786aSStefan Roese #define HPIPE_LANE_CONFIG0_REG 0x600 5523335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 5533335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ 5543335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) 5553335786aSStefan Roese 5563335786aSStefan Roese #define HPIPE_LANE_CONFIG1_REG 0x604 5573335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9 5583335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \ 5593335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET) 5603335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10 5613335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \ 5623335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET) 5633335786aSStefan Roese 5643335786aSStefan Roese #define HPIPE_LANE_STATUS1_REG 0x60C 5653335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 5663335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ 5673335786aSStefan Roese (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) 5683335786aSStefan Roese 5693335786aSStefan Roese #define HPIPE_LANE_CFG4_REG 0x620 5703335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 5713335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ 5723335786aSStefan Roese (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) 573*ae07a70aSIgal Liberman #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 574*ae07a70aSIgal Liberman #define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ 575*ae07a70aSIgal Liberman (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) 5763335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 5773335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_MASK \ 5783335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) 5793335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 5803335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ 5813335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) 5823335786aSStefan Roese 5833335786aSStefan Roese #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C 5843335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 5853335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_MASK \ 5863335786aSStefan Roese (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) 5873335786aSStefan Roese 5883335786aSStefan Roese #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 5893335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 5903335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_MASK \ 5913335786aSStefan Roese (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) 5923335786aSStefan Roese 593*ae07a70aSIgal Liberman #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 594*ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 595*ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ 596*ae07a70aSIgal Liberman (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) 597*ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 598*ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ 599*ae07a70aSIgal Liberman (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) 600*ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 601*ae07a70aSIgal Liberman #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ 602*ae07a70aSIgal Liberman (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) 603*ae07a70aSIgal Liberman 6043335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_REG 0x704 6053335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 6063335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ 6073335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) 6083335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 6093335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ 6103335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) 6113335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 6123335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ 6133335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) 6143335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 6153335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ 6163335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) 6173335786aSStefan Roese 6183335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_REG 0x708 6193335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 6203335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ 6213335786aSStefan Roese (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) 6223335786aSStefan Roese 6233335786aSStefan Roese #define HPIPE_CLK_SRC_LO_REG 0x70c 6243335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 6253335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ 6263335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) 6273335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 6283335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ 6293335786aSStefan Roese (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) 6303335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 6313335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ 6323335786aSStefan Roese (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) 6333335786aSStefan Roese 6343335786aSStefan Roese #define HPIPE_CLK_SRC_HI_REG 0x710 6353335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 6363335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ 6373335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) 6383335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 6393335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ 6403335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) 6413335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 6423335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ 6433335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) 6443335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 6453335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ 6463335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) 6473335786aSStefan Roese 6483335786aSStefan Roese #define HPIPE_GLOBAL_MISC_CTRL 0x718 6493335786aSStefan Roese #define HPIPE_GLOBAL_PM_CTRL 0x740 6503335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 6513335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ 6523335786aSStefan Roese (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) 6533335786aSStefan Roese 6543335786aSStefan Roese #endif /* _COMPHY_HPIPE_H_ */ 6553335786aSStefan Roese 656