13335786aSStefan Roese /* 23335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 33335786aSStefan Roese * 43335786aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 53335786aSStefan Roese */ 63335786aSStefan Roese 73335786aSStefan Roese #ifndef _COMPHY_HPIPE_H_ 83335786aSStefan Roese #define _COMPHY_HPIPE_H_ 93335786aSStefan Roese 103335786aSStefan Roese /* SerDes IP register */ 113335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_REG 0 123335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 133335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ 143335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) 153335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 163335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ 173335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 183335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 193335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ 203335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 213335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 223335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ 233335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) 243335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 253335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ 263335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) 273335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 283335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ 293335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) 303335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 313335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ 323335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) 333335786aSStefan Roese 343335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_REG 0x4 353335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 363335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ 373335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 383335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 393335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ 403335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 413335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 423335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ 433335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 443335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 453335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ 463335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 473335786aSStefan Roese 483335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_REG 0x8 493335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 503335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ 513335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) 52c01f9fe8SIgal Liberman #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 53c01f9fe8SIgal Liberman #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ 54c01f9fe8SIgal Liberman (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) 553335786aSStefan Roese 563335786aSStefan Roese #define SD_EXTERNAL_STATUS0_REG 0x18 573335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 583335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ 593335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) 603335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 613335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ 623335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) 633335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 643335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ 653335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) 663335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6 673335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ 683335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) 693335786aSStefan Roese 703335786aSStefan Roese /* HPIPE register */ 713335786aSStefan Roese #define HPIPE_PWR_PLL_REG 0x4 723335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 733335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_MASK \ 743335786aSStefan Roese (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) 753335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 763335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_MASK \ 773335786aSStefan Roese (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) 783335786aSStefan Roese 793335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_REG 0x8 803335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 813335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \ 823335786aSStefan Roese (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) 833335786aSStefan Roese 84c0132f60SStefan Roese #define HPIPE_CAL_REG1_REG 0xc 85c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 86c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ 87c0132f60SStefan Roese (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) 88c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 89c0132f60SStefan Roese #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ 90c0132f60SStefan Roese (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) 91c0132f60SStefan Roese 923335786aSStefan Roese #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 933335786aSStefan Roese 943335786aSStefan Roese #define HPIPE_DFE_REG0 0x01C 953335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_OFFSET 15 963335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_MASK \ 973335786aSStefan Roese (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) 983335786aSStefan Roese 993335786aSStefan Roese #define HPIPE_DFE_F3_F5_REG 0x028 1003335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 1013335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_MASK \ 1023335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) 1033335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 1043335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ 1053335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) 1063335786aSStefan Roese 1073335786aSStefan Roese #define HPIPE_G1_SET_0_REG 0x034 108c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 109c0132f60SStefan Roese #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ 110c0132f60SStefan Roese (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) 111c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 112c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ 113c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) 1143335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 1153335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ 1163335786aSStefan Roese (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) 117c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 118c01f9fe8SIgal Liberman #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ 119c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) 1203335786aSStefan Roese 1213335786aSStefan Roese #define HPIPE_G1_SET_1_REG 0x038 1223335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 1233335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ 1243335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) 1253335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 1263335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ 1273335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) 128c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 129c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ 130c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) 131c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 132c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ 133c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) 1343335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 1353335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ 1363335786aSStefan Roese (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) 1373335786aSStefan Roese 138c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 139c01f9fe8SIgal Liberman #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ 140c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) 1413335786aSStefan Roese 142c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_REG 0x3c 143c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 144c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ 145c01f9fe8SIgal Liberman (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) 146c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 147c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ 148c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) 149c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 150c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ 151c01f9fe8SIgal Liberman (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) 152c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 153c01f9fe8SIgal Liberman #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ 154c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) 155c01f9fe8SIgal Liberman 156c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_REG 0x040 157c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 158c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ 159c01f9fe8SIgal Liberman (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) 160c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 161c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ 162c01f9fe8SIgal Liberman (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) 163c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 164c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ 165c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) 166c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 167c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ 168c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) 169c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 170c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ 171c01f9fe8SIgal Liberman (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) 172c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 173c01f9fe8SIgal Liberman #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ 174c01f9fe8SIgal Liberman (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) 175c01f9fe8SIgal Liberman 176c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_REG 0x44 177c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 178c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ 179c01f9fe8SIgal Liberman (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) 180c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 181c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ 182c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) 183c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 184c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ 185c01f9fe8SIgal Liberman (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) 186c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 187c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ 188c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) 189c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 190c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ 191c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) 192c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 193c01f9fe8SIgal Liberman #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ 194c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) 195c01f9fe8SIgal Liberman 196c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_REG 0x048 197c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 198c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ 199c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) 200c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 201c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ 202c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) 203c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 204c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ 205c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) 206c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 207c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ 208c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) 209c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 210c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ 211c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) 212c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 213c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ 214c01f9fe8SIgal Liberman (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) 215c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 216c01f9fe8SIgal Liberman #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ 217c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) 2183335786aSStefan Roese 2193335786aSStefan Roese #define HPIPE_LOOPBACK_REG 0x08c 2203335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_OFFSET 1 2213335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_MASK \ 2223335786aSStefan Roese (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) 2233335786aSStefan Roese 2243335786aSStefan Roese #define HPIPE_SYNC_PATTERN_REG 0x090 2253335786aSStefan Roese 2263335786aSStefan Roese #define HPIPE_INTERFACE_REG 0x94 2273335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 2283335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_MASK \ 2293335786aSStefan Roese (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) 2303335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 2313335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ 2323335786aSStefan Roese (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) 2333335786aSStefan Roese 2343335786aSStefan Roese #define HPIPE_ISOLATE_MODE_REG 0x98 2353335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 2363335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \ 2373335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) 2383335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 2393335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \ 2403335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) 2413335786aSStefan Roese 242c0132f60SStefan Roese #define HPIPE_G1_SET_2_REG 0xf4 243c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 244c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ 245c0132f60SStefan Roese (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) 246c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 247c0132f60SStefan Roese #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ 248c0132f60SStefan Roese (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK) 249c0132f60SStefan Roese 2503335786aSStefan Roese #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 2513335786aSStefan Roese 252c01f9fe8SIgal Liberman #define HPIPE_VDD_CAL_CTRL_REG 0x114 253c01f9fe8SIgal Liberman #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 254c01f9fe8SIgal Liberman #define HPIPE_EXT_SELLV_RXSAMPL_MASK \ 255c01f9fe8SIgal Liberman (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) 256c01f9fe8SIgal Liberman 257*781ea0abSIgal Liberman #define HPIPE_VDD_CAL_0_REG 0x108 258*781ea0abSIgal Liberman #define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 259*781ea0abSIgal Liberman #define HPIPE_CAL_VDD_CONT_MODE_MASK \ 260*781ea0abSIgal Liberman (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) 261*781ea0abSIgal Liberman 2623335786aSStefan Roese #define HPIPE_PCIE_REG0 0x120 2633335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 2643335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_MASK \ 2653335786aSStefan Roese (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) 2663335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_OFFSET 13 2673335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_MASK \ 2683335786aSStefan Roese (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) 2693335786aSStefan Roese 2703335786aSStefan Roese #define HPIPE_LANE_ALIGN_REG 0x124 2713335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 2723335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_MASK \ 2733335786aSStefan Roese (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) 2743335786aSStefan Roese 2753335786aSStefan Roese #define HPIPE_MISC_REG 0x13C 2763335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_OFFSET 4 2773335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_MASK \ 2783335786aSStefan Roese (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) 279c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_OFFSET 5 280c0132f60SStefan Roese #define HPIPE_MISC_ICP_FORCE_MASK \ 281c0132f60SStefan Roese (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) 2823335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 2833335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_MASK \ 2843335786aSStefan Roese (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) 2853335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_OFFSET 7 2863335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_MASK \ 2873335786aSStefan Roese (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) 2883335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 2893335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_MASK \ 2903335786aSStefan Roese (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) 2913335786aSStefan Roese 2923335786aSStefan Roese #define HPIPE_RX_CONTROL_1_REG 0x140 2933335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 2943335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ 2953335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) 2963335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 2973335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ 2983335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) 2993335786aSStefan Roese 3003335786aSStefan Roese #define HPIPE_PWR_CTR_REG 0x148 3013335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 3023335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_MASK \ 3033335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) 3043335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 3053335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_MASK \ 3063335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) 3073335786aSStefan Roese 308b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_REG 0x154 309*781ea0abSIgal Liberman #define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 310*781ea0abSIgal Liberman #define HPIPE_TXDIGCK_DIV_FORCE_MASK \ 311*781ea0abSIgal Liberman (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) 312b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 313b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ 314b617a0d7SIgal Liberman (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) 315b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 316b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \ 317b617a0d7SIgal Liberman (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) 318b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 319b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \ 320b617a0d7SIgal Liberman (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) 321b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 322b617a0d7SIgal Liberman #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \ 323b617a0d7SIgal Liberman (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) 324b617a0d7SIgal Liberman 3253335786aSStefan Roese #define HPIPE_PLLINTP_REG1 0x150 3263335786aSStefan Roese 3273335786aSStefan Roese #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C 328*781ea0abSIgal Liberman #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 329*781ea0abSIgal Liberman #define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ 330*781ea0abSIgal Liberman (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) 3313335786aSStefan Roese #define HPIPE_SMAPLER_OFFSET 12 3323335786aSStefan Roese #define HPIPE_SMAPLER_MASK \ 3333335786aSStefan Roese (0x1 << HPIPE_SMAPLER_OFFSET) 3343335786aSStefan Roese 335c0132f60SStefan Roese #define HPIPE_TX_REG1_REG 0x174 336c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 337c0132f60SStefan Roese #define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ 338c0132f60SStefan Roese (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) 339c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 340c0132f60SStefan Roese #define HPIPE_TX_REG1_SLC_EN_MASK \ 341c0132f60SStefan Roese (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) 342c0132f60SStefan Roese 3433335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_REG 0x184 344c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 345c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ 346c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) 347c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 348c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ 349c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) 3503335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 3513335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ 3523335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) 353c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 354c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ 355c01f9fe8SIgal Liberman (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) 356c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 357c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ 358c01f9fe8SIgal Liberman (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) 359c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 360c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ 361c01f9fe8SIgal Liberman (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) 362c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 363c01f9fe8SIgal Liberman #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ 364c01f9fe8SIgal Liberman (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) 3653335786aSStefan Roese 366c01f9fe8SIgal Liberman #define HPIPE_PHASE_CONTROL_REG 0x188 367c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_OFFSET 0 368c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_MASK \ 369c01f9fe8SIgal Liberman (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) 370c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 371c01f9fe8SIgal Liberman #define HPIPE_OS_PH_OFFSET_FORCE_MASK \ 372c01f9fe8SIgal Liberman (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) 373c01f9fe8SIgal Liberman #define HPIPE_OS_PH_VALID_OFFSET 8 374c01f9fe8SIgal Liberman #define HPIPE_OS_PH_VALID_MASK \ 375c01f9fe8SIgal Liberman (0x1 << HPIPE_OS_PH_VALID_OFFSET) 3763335786aSStefan Roese 377*781ea0abSIgal Liberman #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 378*781ea0abSIgal Liberman #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 379*781ea0abSIgal Liberman #define HPIPE_TRAIN_PAT_NUM_MASK \ 380*781ea0abSIgal Liberman (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) 381*781ea0abSIgal Liberman 382*781ea0abSIgal Liberman #define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 383*781ea0abSIgal Liberman #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 384*781ea0abSIgal Liberman #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ 385*781ea0abSIgal Liberman (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) 386*781ea0abSIgal Liberman 387*781ea0abSIgal Liberman #define HPIPE_DME_REG 0x228 388*781ea0abSIgal Liberman #define HPIPE_DME_ETHERNET_MODE_OFFSET 7 389*781ea0abSIgal Liberman #define HPIPE_DME_ETHERNET_MODE_MASK \ 390*781ea0abSIgal Liberman (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) 391*781ea0abSIgal Liberman 3923335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 3933335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 3943335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ 3953335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) 3963335786aSStefan Roese 3973335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_REG 0x26C 3983335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 3993335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_MASK \ 4003335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) 4013335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 4023335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ 4033335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) 4043335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 4053335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_MASK \ 4063335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) 4073335786aSStefan Roese 4083335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 4093335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 4103335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_MASK \ 4113335786aSStefan Roese (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) 4123335786aSStefan Roese 4133335786aSStefan Roese #define HPIPE_PCIE_REG1 0x288 4143335786aSStefan Roese #define HPIPE_PCIE_REG3 0x290 4153335786aSStefan Roese 4163335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 417*781ea0abSIgal Liberman #define HPIPE_RX_TRAIN_TIMER_OFFSET 0 418*781ea0abSIgal Liberman #define HPIPE_RX_TRAIN_TIMER_MASK \ 419*781ea0abSIgal Liberman (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) 4203335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 4213335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ 4223335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) 4233335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 4243335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ 4253335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) 4263335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 4273335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ 4283335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) 4293335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 4303335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ 4313335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) 4323335786aSStefan Roese 4333335786aSStefan Roese #define HPIPE_TX_TRAIN_REG 0x31C 4343335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 4353335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_MASK \ 4363335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) 4373335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 4383335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ 4393335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) 440*781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 441*781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ 442*781ea0abSIgal Liberman (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) 443*781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 444*781ea0abSIgal Liberman #define HPIPE_TX_TRAIN_PAT_SEL_MASK \ 445*781ea0abSIgal Liberman (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) 4463335786aSStefan Roese 4473335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 4483335786aSStefan Roese #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 4493335786aSStefan Roese #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ 4503335786aSStefan Roese (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) 4513335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 4523335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_MASK \ 4533335786aSStefan Roese (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) 4543335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 4553335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ 4563335786aSStefan Roese (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) 4573335786aSStefan Roese 4583335786aSStefan Roese #define HPIPE_G1_SETTINGS_3_REG 0x440 459c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 460c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ 461c01f9fe8SIgal Liberman (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) 462c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 463c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ 464c01f9fe8SIgal Liberman (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) 465c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 466c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ 467c01f9fe8SIgal Liberman (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) 468c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 469c0132f60SStefan Roese #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ 470c0132f60SStefan Roese (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) 471c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 472c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ 473c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) 474c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 475c01f9fe8SIgal Liberman #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ 476c01f9fe8SIgal Liberman (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) 4773335786aSStefan Roese 4783335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_REG 0x444 4793335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 4803335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ 4813335786aSStefan Roese (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) 4823335786aSStefan Roese 4833335786aSStefan Roese #define HPIPE_G2_SETTINGS_3_REG 0x448 4843335786aSStefan Roese #define HPIPE_G2_SETTINGS_4_REG 0x44C 4853335786aSStefan Roese 4863335786aSStefan Roese #define HPIPE_G3_SETTING_3_REG 0x450 487c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 488c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_CAP_SEL_MASK \ 489c01f9fe8SIgal Liberman (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) 490c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 491c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_RES_SEL_MASK \ 492c01f9fe8SIgal Liberman (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) 493c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 494c01f9fe8SIgal Liberman #define HPIPE_G3_FFE_SETTING_FORCE_MASK \ 495c01f9fe8SIgal Liberman (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) 4963335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 4973335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ 4983335786aSStefan Roese (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) 4993335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 5003335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ 5013335786aSStefan Roese (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) 5023335786aSStefan Roese 5033335786aSStefan Roese #define HPIPE_G3_SETTING_4_REG 0x454 5043335786aSStefan Roese #define HPIPE_G3_DFE_RES_OFFSET 8 5053335786aSStefan Roese #define HPIPE_G3_DFE_RES_MASK \ 5063335786aSStefan Roese (0x3 << HPIPE_G3_DFE_RES_OFFSET) 5073335786aSStefan Roese 508*781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_REG 0x468 509*781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_OFFSET 0 510*781ea0abSIgal Liberman #define HPIPE_TX_PRESET_INDEX_MASK \ 511*781ea0abSIgal Liberman (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) 512*781ea0abSIgal Liberman 5133335786aSStefan Roese #define HPIPE_DFE_CTRL_28_REG 0x49C 5143335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 5153335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ 5163335786aSStefan Roese (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) 5173335786aSStefan Roese 518c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_REG 0x538 519c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 520c0132f60SStefan Roese #define HPIPE_G1_SETTING_5_G1_ICP_MASK \ 521c0132f60SStefan Roese (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) 522c0132f60SStefan Roese 5233335786aSStefan Roese #define HPIPE_LANE_CONFIG0_REG 0x600 5243335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 5253335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ 5263335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) 5273335786aSStefan Roese 5283335786aSStefan Roese #define HPIPE_LANE_CONFIG1_REG 0x604 5293335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9 5303335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \ 5313335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET) 5323335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10 5333335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \ 5343335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET) 5353335786aSStefan Roese 5363335786aSStefan Roese #define HPIPE_LANE_STATUS1_REG 0x60C 5373335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 5383335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ 5393335786aSStefan Roese (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) 5403335786aSStefan Roese 5413335786aSStefan Roese #define HPIPE_LANE_CFG4_REG 0x620 5423335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 5433335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ 5443335786aSStefan Roese (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) 5453335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 5463335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_MASK \ 5473335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) 5483335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 5493335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ 5503335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) 5513335786aSStefan Roese 5523335786aSStefan Roese #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C 5533335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 5543335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_MASK \ 5553335786aSStefan Roese (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) 5563335786aSStefan Roese 5573335786aSStefan Roese #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 5583335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 5593335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_MASK \ 5603335786aSStefan Roese (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) 5613335786aSStefan Roese 5623335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_REG 0x704 5633335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 5643335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ 5653335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) 5663335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 5673335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ 5683335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) 5693335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 5703335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ 5713335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) 5723335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 5733335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ 5743335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) 5753335786aSStefan Roese 5763335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_REG 0x708 5773335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 5783335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ 5793335786aSStefan Roese (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) 5803335786aSStefan Roese 5813335786aSStefan Roese #define HPIPE_CLK_SRC_LO_REG 0x70c 5823335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 5833335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ 5843335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) 5853335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 5863335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ 5873335786aSStefan Roese (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) 5883335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 5893335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ 5903335786aSStefan Roese (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) 5913335786aSStefan Roese 5923335786aSStefan Roese #define HPIPE_CLK_SRC_HI_REG 0x710 5933335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 5943335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ 5953335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) 5963335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 5973335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ 5983335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) 5993335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 6003335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ 6013335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) 6023335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 6033335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ 6043335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) 6053335786aSStefan Roese 6063335786aSStefan Roese #define HPIPE_GLOBAL_MISC_CTRL 0x718 6073335786aSStefan Roese #define HPIPE_GLOBAL_PM_CTRL 0x740 6083335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 6093335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ 6103335786aSStefan Roese (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) 6113335786aSStefan Roese 6123335786aSStefan Roese #endif /* _COMPHY_HPIPE_H_ */ 6133335786aSStefan Roese 614