1*3335786aSStefan Roese /* 2*3335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 3*3335786aSStefan Roese * 4*3335786aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*3335786aSStefan Roese */ 6*3335786aSStefan Roese 7*3335786aSStefan Roese #ifndef _COMPHY_HPIPE_H_ 8*3335786aSStefan Roese #define _COMPHY_HPIPE_H_ 9*3335786aSStefan Roese 10*3335786aSStefan Roese /* SerDes IP register */ 11*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_REG 0 12*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 13*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ 14*3335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) 15*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 16*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ 17*3335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 18*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 19*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ 20*3335786aSStefan Roese (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 21*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 22*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ 23*3335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) 24*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 25*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ 26*3335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) 27*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 28*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ 29*3335786aSStefan Roese (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) 30*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 31*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ 32*3335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) 33*3335786aSStefan Roese 34*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_REG 0x4 35*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 36*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ 37*3335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 38*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 39*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ 40*3335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 41*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 42*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ 43*3335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 44*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 45*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ 46*3335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 47*3335786aSStefan Roese 48*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_REG 0x8 49*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 50*3335786aSStefan Roese #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ 51*3335786aSStefan Roese (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) 52*3335786aSStefan Roese 53*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_REG 0x18 54*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 55*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ 56*3335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) 57*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 58*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ 59*3335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) 60*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 61*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ 62*3335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) 63*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6 64*3335786aSStefan Roese #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ 65*3335786aSStefan Roese (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) 66*3335786aSStefan Roese 67*3335786aSStefan Roese /* HPIPE register */ 68*3335786aSStefan Roese #define HPIPE_PWR_PLL_REG 0x4 69*3335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 70*3335786aSStefan Roese #define HPIPE_PWR_PLL_REF_FREQ_MASK \ 71*3335786aSStefan Roese (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) 72*3335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 73*3335786aSStefan Roese #define HPIPE_PWR_PLL_PHY_MODE_MASK \ 74*3335786aSStefan Roese (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) 75*3335786aSStefan Roese 76*3335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_REG 0x8 77*3335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 78*3335786aSStefan Roese #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \ 79*3335786aSStefan Roese (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) 80*3335786aSStefan Roese 81*3335786aSStefan Roese #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 82*3335786aSStefan Roese 83*3335786aSStefan Roese #define HPIPE_DFE_REG0 0x01C 84*3335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_OFFSET 15 85*3335786aSStefan Roese #define HPIPE_DFE_RES_FORCE_MASK \ 86*3335786aSStefan Roese (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) 87*3335786aSStefan Roese 88*3335786aSStefan Roese #define HPIPE_DFE_F3_F5_REG 0x028 89*3335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 90*3335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_EN_MASK \ 91*3335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) 92*3335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 93*3335786aSStefan Roese #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ 94*3335786aSStefan Roese (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) 95*3335786aSStefan Roese 96*3335786aSStefan Roese #define HPIPE_G1_SET_0_REG 0x034 97*3335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 98*3335786aSStefan Roese #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ 99*3335786aSStefan Roese (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) 100*3335786aSStefan Roese 101*3335786aSStefan Roese #define HPIPE_G1_SET_1_REG 0x038 102*3335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 103*3335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ 104*3335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) 105*3335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 106*3335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ 107*3335786aSStefan Roese (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) 108*3335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 109*3335786aSStefan Roese #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ 110*3335786aSStefan Roese (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) 111*3335786aSStefan Roese 112*3335786aSStefan Roese #define HPIPE_G2_SETTINGS_1_REG 0x040 113*3335786aSStefan Roese 114*3335786aSStefan Roese #define HPIPE_G3_SETTINGS_1_REG 0x048 115*3335786aSStefan Roese #define HPIPE_G3_RX_SELMUPI_OFFSET 0 116*3335786aSStefan Roese #define HPIPE_G3_RX_SELMUPI_MASK \ 117*3335786aSStefan Roese (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) 118*3335786aSStefan Roese #define HPIPE_G3_RX_SELMUPF_OFFSET 3 119*3335786aSStefan Roese #define HPIPE_G3_RX_SELMUPF_MASK \ 120*3335786aSStefan Roese (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) 121*3335786aSStefan Roese #define HPIPE_G3_SETTING_BIT_OFFSET 13 122*3335786aSStefan Roese #define HPIPE_G3_SETTING_BIT_MASK \ 123*3335786aSStefan Roese (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) 124*3335786aSStefan Roese 125*3335786aSStefan Roese #define HPIPE_LOOPBACK_REG 0x08c 126*3335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_OFFSET 1 127*3335786aSStefan Roese #define HPIPE_LOOPBACK_SEL_MASK \ 128*3335786aSStefan Roese (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) 129*3335786aSStefan Roese 130*3335786aSStefan Roese #define HPIPE_SYNC_PATTERN_REG 0x090 131*3335786aSStefan Roese 132*3335786aSStefan Roese #define HPIPE_INTERFACE_REG 0x94 133*3335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 134*3335786aSStefan Roese #define HPIPE_INTERFACE_GEN_MAX_MASK \ 135*3335786aSStefan Roese (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) 136*3335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 137*3335786aSStefan Roese #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ 138*3335786aSStefan Roese (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) 139*3335786aSStefan Roese 140*3335786aSStefan Roese #define HPIPE_ISOLATE_MODE_REG 0x98 141*3335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 142*3335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \ 143*3335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) 144*3335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 145*3335786aSStefan Roese #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \ 146*3335786aSStefan Roese (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) 147*3335786aSStefan Roese 148*3335786aSStefan Roese #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 149*3335786aSStefan Roese 150*3335786aSStefan Roese #define HPIPE_PCIE_REG0 0x120 151*3335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 152*3335786aSStefan Roese #define HPIPE_PCIE_IDLE_SYNC_MASK \ 153*3335786aSStefan Roese (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) 154*3335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_OFFSET 13 155*3335786aSStefan Roese #define HPIPE_PCIE_SEL_BITS_MASK \ 156*3335786aSStefan Roese (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) 157*3335786aSStefan Roese 158*3335786aSStefan Roese #define HPIPE_LANE_ALIGN_REG 0x124 159*3335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 160*3335786aSStefan Roese #define HPIPE_LANE_ALIGN_OFF_MASK \ 161*3335786aSStefan Roese (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) 162*3335786aSStefan Roese 163*3335786aSStefan Roese #define HPIPE_MISC_REG 0x13C 164*3335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_OFFSET 4 165*3335786aSStefan Roese #define HPIPE_MISC_CLK100M_125M_MASK \ 166*3335786aSStefan Roese (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) 167*3335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 168*3335786aSStefan Roese #define HPIPE_MISC_TXDCLK_2X_MASK \ 169*3335786aSStefan Roese (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) 170*3335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_OFFSET 7 171*3335786aSStefan Roese #define HPIPE_MISC_CLK500_EN_MASK \ 172*3335786aSStefan Roese (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) 173*3335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 174*3335786aSStefan Roese #define HPIPE_MISC_REFCLK_SEL_MASK \ 175*3335786aSStefan Roese (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) 176*3335786aSStefan Roese 177*3335786aSStefan Roese #define HPIPE_RX_CONTROL_1_REG 0x140 178*3335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 179*3335786aSStefan Roese #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ 180*3335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) 181*3335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 182*3335786aSStefan Roese #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ 183*3335786aSStefan Roese (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) 184*3335786aSStefan Roese 185*3335786aSStefan Roese #define HPIPE_PWR_CTR_REG 0x148 186*3335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 187*3335786aSStefan Roese #define HPIPE_PWR_CTR_RST_DFE_MASK \ 188*3335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) 189*3335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 190*3335786aSStefan Roese #define HPIPE_PWR_CTR_SFT_RST_MASK \ 191*3335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) 192*3335786aSStefan Roese 193*3335786aSStefan Roese #define HPIPE_PLLINTP_REG1 0x150 194*3335786aSStefan Roese 195*3335786aSStefan Roese #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C 196*3335786aSStefan Roese #define HPIPE_SMAPLER_OFFSET 12 197*3335786aSStefan Roese #define HPIPE_SMAPLER_MASK \ 198*3335786aSStefan Roese (0x1 << HPIPE_SMAPLER_OFFSET) 199*3335786aSStefan Roese 200*3335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_REG 0x184 201*3335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 202*3335786aSStefan Roese #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ 203*3335786aSStefan Roese (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) 204*3335786aSStefan Roese 205*3335786aSStefan Roese #define HPIPE_RX_REG3 0x188 206*3335786aSStefan Roese 207*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 208*3335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 209*3335786aSStefan Roese #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ 210*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) 211*3335786aSStefan Roese 212*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_REG 0x26C 213*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 214*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G1_MASK \ 215*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) 216*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 217*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ 218*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) 219*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 220*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_G0_MASK \ 221*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) 222*3335786aSStefan Roese 223*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 224*3335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 225*3335786aSStefan Roese #define HPIPE_TRX_TRAIN_TIMER_MASK \ 226*3335786aSStefan Roese (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) 227*3335786aSStefan Roese 228*3335786aSStefan Roese #define HPIPE_PCIE_REG1 0x288 229*3335786aSStefan Roese #define HPIPE_PCIE_REG3 0x290 230*3335786aSStefan Roese 231*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 232*3335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 233*3335786aSStefan Roese #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ 234*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) 235*3335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 236*3335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ 237*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) 238*3335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 239*3335786aSStefan Roese #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ 240*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) 241*3335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 242*3335786aSStefan Roese #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ 243*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) 244*3335786aSStefan Roese 245*3335786aSStefan Roese #define HPIPE_TX_TRAIN_REG 0x31C 246*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 247*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CHK_INIT_MASK \ 248*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) 249*3335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 250*3335786aSStefan Roese #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ 251*3335786aSStefan Roese (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) 252*3335786aSStefan Roese 253*3335786aSStefan Roese #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 254*3335786aSStefan Roese #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 255*3335786aSStefan Roese #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ 256*3335786aSStefan Roese (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) 257*3335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 258*3335786aSStefan Roese #define HPIPE_TX_NUM_OF_PRESET_MASK \ 259*3335786aSStefan Roese (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) 260*3335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 261*3335786aSStefan Roese #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ 262*3335786aSStefan Roese (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) 263*3335786aSStefan Roese 264*3335786aSStefan Roese #define HPIPE_G1_SETTINGS_3_REG 0x440 265*3335786aSStefan Roese 266*3335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_REG 0x444 267*3335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 268*3335786aSStefan Roese #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ 269*3335786aSStefan Roese (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) 270*3335786aSStefan Roese 271*3335786aSStefan Roese #define HPIPE_G2_SETTINGS_3_REG 0x448 272*3335786aSStefan Roese #define HPIPE_G2_SETTINGS_4_REG 0x44C 273*3335786aSStefan Roese 274*3335786aSStefan Roese #define HPIPE_G3_SETTING_3_REG 0x450 275*3335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 276*3335786aSStefan Roese #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ 277*3335786aSStefan Roese (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) 278*3335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 279*3335786aSStefan Roese #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ 280*3335786aSStefan Roese (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) 281*3335786aSStefan Roese 282*3335786aSStefan Roese #define HPIPE_G3_SETTING_4_REG 0x454 283*3335786aSStefan Roese #define HPIPE_G3_DFE_RES_OFFSET 8 284*3335786aSStefan Roese #define HPIPE_G3_DFE_RES_MASK \ 285*3335786aSStefan Roese (0x3 << HPIPE_G3_DFE_RES_OFFSET) 286*3335786aSStefan Roese 287*3335786aSStefan Roese #define HPIPE_DFE_CTRL_28_REG 0x49C 288*3335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 289*3335786aSStefan Roese #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ 290*3335786aSStefan Roese (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) 291*3335786aSStefan Roese 292*3335786aSStefan Roese #define HPIPE_LANE_CONFIG0_REG 0x600 293*3335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 294*3335786aSStefan Roese #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ 295*3335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) 296*3335786aSStefan Roese 297*3335786aSStefan Roese #define HPIPE_LANE_CONFIG1_REG 0x604 298*3335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9 299*3335786aSStefan Roese #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \ 300*3335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET) 301*3335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10 302*3335786aSStefan Roese #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \ 303*3335786aSStefan Roese (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET) 304*3335786aSStefan Roese 305*3335786aSStefan Roese #define HPIPE_LANE_STATUS1_REG 0x60C 306*3335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 307*3335786aSStefan Roese #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ 308*3335786aSStefan Roese (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) 309*3335786aSStefan Roese 310*3335786aSStefan Roese #define HPIPE_LANE_CFG4_REG 0x620 311*3335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 312*3335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ 313*3335786aSStefan Roese (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) 314*3335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 315*3335786aSStefan Roese #define HPIPE_LANE_CFG4_DFE_OVER_MASK \ 316*3335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) 317*3335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 318*3335786aSStefan Roese #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ 319*3335786aSStefan Roese (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) 320*3335786aSStefan Roese 321*3335786aSStefan Roese #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C 322*3335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 323*3335786aSStefan Roese #define HPIPE_CFG_PHY_RC_EP_MASK \ 324*3335786aSStefan Roese (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) 325*3335786aSStefan Roese 326*3335786aSStefan Roese #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 327*3335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 328*3335786aSStefan Roese #define HPIPE_CFG_UPDATE_POLARITY_MASK \ 329*3335786aSStefan Roese (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) 330*3335786aSStefan Roese 331*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_REG 0x704 332*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 333*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ 334*3335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) 335*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 336*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ 337*3335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) 338*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 339*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ 340*3335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) 341*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 342*3335786aSStefan Roese #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ 343*3335786aSStefan Roese (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) 344*3335786aSStefan Roese 345*3335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_REG 0x708 346*3335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 347*3335786aSStefan Roese #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ 348*3335786aSStefan Roese (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) 349*3335786aSStefan Roese 350*3335786aSStefan Roese #define HPIPE_CLK_SRC_LO_REG 0x70c 351*3335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 352*3335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ 353*3335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) 354*3335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 355*3335786aSStefan Roese #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ 356*3335786aSStefan Roese (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) 357*3335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 358*3335786aSStefan Roese #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ 359*3335786aSStefan Roese (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) 360*3335786aSStefan Roese 361*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_REG 0x710 362*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 363*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ 364*3335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) 365*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 366*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ 367*3335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) 368*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 369*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ 370*3335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) 371*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 372*3335786aSStefan Roese #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ 373*3335786aSStefan Roese (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) 374*3335786aSStefan Roese 375*3335786aSStefan Roese #define HPIPE_GLOBAL_MISC_CTRL 0x718 376*3335786aSStefan Roese #define HPIPE_GLOBAL_PM_CTRL 0x740 377*3335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 378*3335786aSStefan Roese #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ 379*3335786aSStefan Roese (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) 380*3335786aSStefan Roese 381*3335786aSStefan Roese #endif /* _COMPHY_HPIPE_H_ */ 382*3335786aSStefan Roese 383