1 /* 2 * Copyright (C) 2015-2016 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "comphy_a3700.h" 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 struct sgmii_phy_init_data_fix { 18 u16 addr; 19 u16 value; 20 }; 21 22 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 23 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 24 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 25 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 26 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 27 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 28 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 29 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 30 {0x104, 0x0C10} 31 }; 32 33 /* 40M1G25 mode init data */ 34 static u16 sgmii_phy_init[512] = { 35 /* 0 1 2 3 4 5 6 7 */ 36 /*-----------------------------------------------------------*/ 37 /* 8 9 A B C D E F */ 38 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 39 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 40 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 41 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 42 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 43 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 44 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 45 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 46 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 47 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 48 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 49 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 50 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 51 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 52 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 53 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 54 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 55 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 56 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 57 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 58 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 59 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 60 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 61 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 62 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 63 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 64 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 65 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 66 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 67 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 68 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 69 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 70 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 71 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 72 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 73 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 74 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 75 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 77 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 78 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 79 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 80 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 81 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 82 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 83 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 84 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 85 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 86 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 88 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 90 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 101 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 102 }; 103 104 /* 105 * comphy_poll_reg 106 * 107 * return: 1 on success, 0 on timeout 108 */ 109 static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u32 timeout, 110 u8 op_type) 111 { 112 u32 rval = 0xDEAD; 113 114 for (; timeout > 0; timeout--) { 115 if (op_type == POLL_16B_REG) 116 rval = readw(addr); /* 16 bit */ 117 else 118 rval = readl(addr) ; /* 32 bit */ 119 120 if ((rval & mask) == val) 121 return 1; 122 123 udelay(10000); 124 } 125 126 debug("Time out waiting (%p = %#010x)\n", addr, rval); 127 return 0; 128 } 129 130 /* 131 * comphy_pcie_power_up 132 * 133 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 134 */ 135 static int comphy_pcie_power_up(u32 speed, u32 invert) 136 { 137 int ret; 138 139 debug_enter(); 140 141 /* 142 * 1. Enable max PLL. 143 */ 144 reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE), 145 bf_use_max_pll_rate, 0); 146 147 /* 148 * 2. Select 20 bit SERDES interface. 149 */ 150 reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE), 151 bf_cfg_sel_20b, 0); 152 153 /* 154 * 3. Force to use reg setting for PCIe mode 155 */ 156 reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE), 157 bf_sel_bits_pcie_force, 0); 158 159 /* 160 * 4. Change RX wait 161 */ 162 reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF); 163 164 /* 165 * 5. Enable idle sync 166 */ 167 reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE), 168 0x60 | rb_idle_sync_en, 0xFFFF); 169 170 /* 171 * 6. Enable the output of 100M/125M/500M clock 172 */ 173 reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE), 174 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); 175 176 /* 177 * 7. Enable TX 178 */ 179 reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); 180 181 /* 182 * 8. Check crystal jumper setting and program the Power and PLL 183 * Control accordingly 184 */ 185 if (get_ref_clk() == 40) { 186 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), 187 0xFC63, 0xFFFF); /* 40 MHz */ 188 } else { 189 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), 190 0xFC62, 0xFFFF); /* 25 MHz */ 191 } 192 193 /* 194 * 9. Override Speed_PLL value and use MAC PLL 195 */ 196 reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE), 197 0x0040 | rb_use_max_pll_rate, 0xFFFF); 198 199 /* 200 * 10. Check the Polarity invert bit 201 */ 202 if (invert & PHY_POLARITY_TXD_INVERT) { 203 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), 204 phy_txd_inv, 0); 205 } 206 207 if (invert & PHY_POLARITY_RXD_INVERT) { 208 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), 209 phy_rxd_inv, 0); 210 } 211 212 /* 213 * 11. Release SW reset 214 */ 215 reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(PCIE), 216 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32, 217 bf_soft_rst | bf_mode_refdiv); 218 219 /* Wait for > 55 us to allow PCLK be enabled */ 220 udelay(PLL_SET_DELAY_US); 221 222 /* Assert PCLK enabled */ 223 ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(PCIE), /* address */ 224 rb_txdclk_pclk_en, /* value */ 225 rb_txdclk_pclk_en, /* mask */ 226 PLL_LOCK_TIMEOUT, /* timeout */ 227 POLL_16B_REG); /* 16bit */ 228 if (ret == 0) 229 printf("Failed to lock PCIe PLL\n"); 230 231 debug_exit(); 232 233 /* Return the status of the PLL */ 234 return ret; 235 } 236 237 /* 238 * comphy_sata_power_up 239 * 240 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 241 */ 242 static int comphy_sata_power_up(void) 243 { 244 int ret; 245 246 debug_enter(); 247 248 /* 249 * 0. Swap SATA TX lines 250 */ 251 reg_set((void __iomem *)rh_vsreg_addr, 252 vphy_sync_pattern_reg, 0xFFFFFFFF); 253 reg_set((void __iomem *)rh_vsreg_data, bs_txd_inv, bs_txd_inv); 254 255 /* 256 * 1. Select 40-bit data width width 257 */ 258 reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); 259 reg_set((void __iomem *)rh_vsreg_data, 0x800, bs_phyintf_40bit); 260 261 /* 262 * 2. Select reference clock and PHY mode (SATA) 263 */ 264 reg_set((void __iomem *)rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF); 265 if (get_ref_clk() == 40) { 266 reg_set((void __iomem *)rh_vsreg_data, 267 0x3, 0x00FF); /* 40 MHz */ 268 } else { 269 reg_set((void __iomem *)rh_vsreg_data, 270 0x1, 0x00FF); /* 25 MHz */ 271 } 272 273 /* 274 * 3. Use maximum PLL rate (no power save) 275 */ 276 reg_set((void __iomem *)rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF); 277 reg_set((void __iomem *)rh_vsreg_data, 278 bs_max_pll_rate, bs_max_pll_rate); 279 280 /* 281 * 4. Reset reserved bit (??) 282 */ 283 reg_set((void __iomem *)rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF); 284 reg_set((void __iomem *)rh_vsreg_data, 0, bs_phyctrl_frm_pin); 285 286 /* 287 * 5. Set vendor-specific configuration (??) 288 */ 289 reg_set((void __iomem *)rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); 290 reg_set((void __iomem *)rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); 291 292 /* Wait for > 55 us to allow PLL be enabled */ 293 udelay(PLL_SET_DELAY_US); 294 295 /* Assert SATA PLL enabled */ 296 reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); 297 ret = comphy_poll_reg((void *)rh_vsreg_data, /* address */ 298 bs_pll_ready_tx, /* value */ 299 bs_pll_ready_tx, /* mask */ 300 PLL_LOCK_TIMEOUT, /* timeout */ 301 POLL_32B_REG); /* 32bit */ 302 if (ret == 0) 303 printf("Failed to lock SATA PLL\n"); 304 305 debug_exit(); 306 307 return ret; 308 } 309 310 /* 311 * comphy_usb3_power_up 312 * 313 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 314 */ 315 static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) 316 { 317 int ret; 318 319 debug_enter(); 320 321 /* 322 * 1. Power up OTG module 323 */ 324 reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); 325 326 /* 327 * 2. Set counter for 100us pulse in USB3 Host and Device 328 * restore default burst size limit (Reference Clock 31:24) 329 */ 330 reg_set((void __iomem *)USB3_CTRPUL_VAL_REG, 331 0x8 << 24, rb_usb3_ctr_100ns); 332 333 334 /* 0xd005c300 = 0x1001 */ 335 /* set PRD_TXDEEMPH (3.5db de-emph) */ 336 reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF); 337 338 /* 339 * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in 340 * low impedance mode during electrical idle 341 */ 342 /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */ 343 /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */ 344 reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF); 345 346 347 /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ 348 reg_set16((void __iomem *)LANE_CFG4_ADDR(USB3), 349 bf_spread_spectrum_clock_en, 0x80); 350 351 /* 352 * set Override Margining Controls From the MAC: Use margining signals 353 * from lane configuration 354 */ 355 reg_set16((void __iomem *)TEST_MODE_CTRL_ADDR(USB3), 356 rb_mode_margin_override, 0xFFFF); 357 358 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ 359 /* set Mode Clock Source = PCLK is generated from REFCLK */ 360 reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF); 361 362 /* set G2 Spread Spectrum Clock Amplitude at 4K */ 363 reg_set16((void __iomem *)GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, 364 0xF000); 365 366 /* 367 * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register 368 * Master Current Select 369 */ 370 reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF); 371 372 /* 373 * 3. Check crystal jumper setting and program the Power and PLL 374 * Control accordingly 375 */ 376 if (get_ref_clk() == 40) { 377 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, 378 0xFFFF); /* 40 MHz */ 379 } else { 380 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, 381 0xFFFF); /* 25 MHz */ 382 } 383 384 /* 385 * 4. Change RX wait 386 */ 387 reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF); 388 389 /* 390 * 5. Enable idle sync 391 */ 392 reg_set16((void __iomem *)UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, 393 0xFFFF); 394 395 /* 396 * 6. Enable the output of 500M clock 397 */ 398 reg_set16((void __iomem *)MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, 399 0xFFFF); 400 401 /* 402 * 7. Set 20-bit data width 403 */ 404 reg_set16((void __iomem *)DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF); 405 406 /* 407 * 8. Override Speed_PLL value and use MAC PLL 408 */ 409 reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(USB3), 410 0x0040 | rb_use_max_pll_rate, 0xFFFF); 411 412 /* 413 * 9. Check the Polarity invert bit 414 */ 415 if (invert & PHY_POLARITY_TXD_INVERT) { 416 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), 417 phy_txd_inv, 0); 418 } 419 420 if (invert & PHY_POLARITY_RXD_INVERT) { 421 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), 422 phy_rxd_inv, 0); 423 } 424 425 /* 426 * 10. Release SW reset 427 */ 428 reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(USB3), 429 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20, 430 0xFFFF); 431 432 /* Wait for > 55 us to allow PCLK be enabled */ 433 udelay(PLL_SET_DELAY_US); 434 435 /* Assert PCLK enabled */ 436 ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(USB3), /* address */ 437 rb_txdclk_pclk_en, /* value */ 438 rb_txdclk_pclk_en, /* mask */ 439 PLL_LOCK_TIMEOUT, /* timeout */ 440 POLL_16B_REG); /* 16bit */ 441 if (ret == 0) 442 printf("Failed to lock USB3 PLL\n"); 443 444 /* 445 * Set Soft ID for Host mode (Device mode works with Hard ID 446 * detection) 447 */ 448 if (type == PHY_TYPE_USB3_HOST0) { 449 /* 450 * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) 451 * clear BIT1: set SOFT_ID = Host 452 * set BIT4: set INT_MODE = ID. Interrupt Mode: enable 453 * interrupt by ID instead of using both interrupts 454 * of HOST and Device ORed simultaneously 455 * INT_MODE=ID in order to avoid unexpected 456 * behaviour or both interrupts together 457 */ 458 reg_set((void __iomem *)USB32_CTRL_BASE, 459 usb32_ctrl_id_mode | usb32_ctrl_int_mode, 460 usb32_ctrl_id_mode | usb32_ctrl_soft_id | 461 usb32_ctrl_int_mode); 462 } 463 464 debug_exit(); 465 466 return ret; 467 } 468 469 /* 470 * comphy_usb2_power_up 471 * 472 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 473 */ 474 static int comphy_usb2_power_up(u8 usb32) 475 { 476 int ret; 477 478 debug_enter(); 479 480 if (usb32 != 0 && usb32 != 1) { 481 printf("invalid usb32 value: (%d), should be either 0 or 1\n", 482 usb32); 483 debug_exit(); 484 return 0; 485 } 486 487 /* 488 * 0. Setup PLL. 40MHz clock uses defaults. 489 * See "PLL Settings for Typical REFCLK" table 490 */ 491 if (get_ref_clk() == 25) { 492 reg_set((void __iomem *)USB2_PHY_BASE(usb32), 493 5 | (96 << 16), 0x3F | (0xFF << 16) | (0x3 << 28)); 494 } 495 496 /* 497 * 1. PHY pull up and disable USB2 suspend 498 */ 499 reg_set((void __iomem *)USB2_PHY_CTRL_ADDR(usb32), 500 RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0); 501 502 if (usb32 != 0) { 503 /* 504 * 2. Power up OTG module 505 */ 506 reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); 507 508 /* 509 * 3. Configure PHY charger detection 510 */ 511 reg_set((void __iomem *)USB2_PHY_CHRGR_DET_ADDR, 0, 512 rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto | 513 rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc); 514 } 515 516 /* Assert PLL calibration done */ 517 ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32), 518 rb_usb2phy_pllcal_done, /* value */ 519 rb_usb2phy_pllcal_done, /* mask */ 520 PLL_LOCK_TIMEOUT, /* timeout */ 521 POLL_32B_REG); /* 32bit */ 522 if (ret == 0) 523 printf("Failed to end USB2 PLL calibration\n"); 524 525 /* Assert impedance calibration done */ 526 ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32), 527 rb_usb2phy_impcal_done, /* value */ 528 rb_usb2phy_impcal_done, /* mask */ 529 PLL_LOCK_TIMEOUT, /* timeout */ 530 POLL_32B_REG); /* 32bit */ 531 if (ret == 0) 532 printf("Failed to end USB2 impedance calibration\n"); 533 534 /* Assert squetch calibration done */ 535 ret = comphy_poll_reg((void *)USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), 536 rb_usb2phy_sqcal_done, /* value */ 537 rb_usb2phy_sqcal_done, /* mask */ 538 PLL_LOCK_TIMEOUT, /* timeout */ 539 POLL_32B_REG); /* 32bit */ 540 if (ret == 0) 541 printf("Failed to end USB2 unknown calibration\n"); 542 543 /* Assert PLL is ready */ 544 ret = comphy_poll_reg((void *)USB2_PHY_PLL_CTRL0_ADDR(usb32), 545 rb_usb2phy_pll_ready, /* value */ 546 rb_usb2phy_pll_ready, /* mask */ 547 PLL_LOCK_TIMEOUT, /* timeout */ 548 POLL_32B_REG); /* 32bit */ 549 550 if (ret == 0) 551 printf("Failed to lock USB2 PLL\n"); 552 553 debug_exit(); 554 555 return ret; 556 } 557 558 /* 559 * comphy_emmc_power_up 560 * 561 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 562 */ 563 static int comphy_emmc_power_up(void) 564 { 565 debug_enter(); 566 567 /* 568 * 1. Bus power ON, Bus voltage 1.8V 569 */ 570 reg_set((void __iomem *)SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); 571 572 /* 573 * 2. Set FIFO parameters 574 */ 575 reg_set((void __iomem *)SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); 576 577 /* 578 * 3. Set Capabilities 1_2 579 */ 580 reg_set((void __iomem *)SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); 581 582 /* 583 * 4. Set Endian 584 */ 585 reg_set((void __iomem *)SDIO_ENDIAN_ADDR, 0x00c00000, 0); 586 587 /* 588 * 4. Init PHY 589 */ 590 reg_set((void __iomem *)SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); 591 reg_set((void __iomem *)SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 592 0xF0000000); 593 594 /* 595 * 5. DLL reset 596 */ 597 reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); 598 reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0x00010000, 0); 599 600 debug_exit(); 601 602 return 1; 603 } 604 605 /* 606 * comphy_sgmii_power_up 607 * 608 * return: 609 */ 610 static void comphy_sgmii_phy_init(u32 lane, u32 speed) 611 { 612 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 613 int addr, fix_idx; 614 u16 val; 615 616 fix_idx = 0; 617 for (addr = 0; addr < 512; addr++) { 618 /* 619 * All PHY register values are defined in full for 3.125Gbps 620 * SERDES speed. The values required for 1.25 Gbps are almost 621 * the same and only few registers should be "fixed" in 622 * comparison to 3.125 Gbps values. These register values are 623 * stored in "sgmii_phy_init_fix" array. 624 */ 625 if ((speed != PHY_SPEED_1_25G) && 626 (sgmii_phy_init_fix[fix_idx].addr == addr)) { 627 /* Use new value */ 628 val = sgmii_phy_init_fix[fix_idx].value; 629 if (fix_idx < fix_arr_sz) 630 fix_idx++; 631 } else { 632 val = sgmii_phy_init[addr]; 633 } 634 635 phy_write16(lane, addr, val, 0xFFFF); 636 } 637 } 638 639 /* 640 * comphy_sgmii_power_up 641 * 642 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 643 */ 644 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) 645 { 646 int ret; 647 648 debug_enter(); 649 650 /* 651 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 652 */ 653 reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); 654 655 /* 656 * 2. Reset PHY by setting PHY input port PIN_RESET=1. 657 * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 658 * PHY TXP/TXN output to idle state during PHY initialization 659 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 660 */ 661 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 662 rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref, 663 rb_pin_reset_core | rb_pin_pu_pll | 664 rb_pin_pu_rx | rb_pin_pu_tx); 665 666 /* 667 * 5. Release reset to the PHY by setting PIN_RESET=0. 668 */ 669 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 670 0, rb_pin_reset_comphy); 671 672 /* 673 * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide 674 * COMPHY bit rate 675 */ 676 if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ 677 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 678 (0x8 << rf_gen_rx_sel_shift) | 679 (0x8 << rf_gen_tx_sel_shift), 680 rf_gen_rx_select | rf_gen_tx_select); 681 682 } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ 683 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 684 (0x6 << rf_gen_rx_sel_shift) | 685 (0x6 << rf_gen_tx_sel_shift), 686 rf_gen_rx_select | rf_gen_tx_select); 687 } else { 688 printf("Unsupported COMPHY speed!\n"); 689 return 0; 690 } 691 692 /* 693 * 8. Wait 1mS for bandgap and reference clocks to stabilize; 694 * then start SW programming. 695 */ 696 mdelay(10); 697 698 /* 9. Program COMPHY register PHY_MODE */ 699 phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, 700 PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); 701 702 /* 703 * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK 704 * source 705 */ 706 phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel); 707 708 /* 709 * 11. Set correct reference clock frequency in COMPHY register 710 * REF_FREF_SEL. 711 */ 712 if (get_ref_clk() == 40) { 713 phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, 714 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); 715 } else { 716 /* 25MHz */ 717 phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, 718 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); 719 } 720 721 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ 722 /* 723 * This step is mentioned in the flow received from verification team. 724 * However the PHY_GEN_MAX value is only meaningful for other 725 * interfaces (not SGMII). For instance, it selects SATA speed 726 * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps 727 */ 728 729 /* 730 * 13. Program COMPHY register SEL_BITS to set correct parallel data 731 * bus width 732 */ 733 /* 10bit */ 734 phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask); 735 736 /* 737 * 14. As long as DFE function needs to be enabled in any mode, 738 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 739 * for real chip during COMPHY power on. 740 */ 741 /* 742 * The step 14 exists (and empty) in the original initialization flow 743 * obtained from the verification team. According to the functional 744 * specification DFE_UPDATE_EN already has the default value 0x3F 745 */ 746 747 /* 748 * 15. Program COMPHY GEN registers. 749 * These registers should be programmed based on the lab testing 750 * result to achieve optimal performance. Please contact the CEA 751 * group to get the related GEN table during real chip bring-up. 752 * We only requred to run though the entire registers programming 753 * flow defined by "comphy_sgmii_phy_init" when the REF clock is 754 * 40 MHz. For REF clock 25 MHz the default values stored in PHY 755 * registers are OK. 756 */ 757 debug("Running C-DPI phy init %s mode\n", 758 speed == PHY_SPEED_3_125G ? "2G5" : "1G"); 759 if (get_ref_clk() == 40) 760 comphy_sgmii_phy_init(lane, speed); 761 762 /* 763 * 16. [Simulation Only] should not be used for real chip. 764 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 765 * (R02h[9]) to 1 to shorten COMPHY simulation time. 766 */ 767 /* 768 * 17. [Simulation Only: should not be used for real chip] 769 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX 770 * training simulation time. 771 */ 772 773 /* 774 * 18. Check the PHY Polarity invert bit 775 */ 776 if (invert & PHY_POLARITY_TXD_INVERT) 777 phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0); 778 779 if (invert & PHY_POLARITY_RXD_INVERT) 780 phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0); 781 782 /* 783 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 784 * to start PHY power up sequence. All the PHY register 785 * programming should be done before PIN_PU_PLL=1. There should be 786 * no register programming for normal PHY operation from this point. 787 */ 788 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 789 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx, 790 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx); 791 792 /* 793 * 20. Wait for PHY power up sequence to finish by checking output ports 794 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 795 */ 796 ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */ 797 rb_pll_ready_tx | rb_pll_ready_rx, /* value */ 798 rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ 799 PLL_LOCK_TIMEOUT, /* timeout */ 800 POLL_32B_REG); /* 32bit */ 801 if (ret == 0) 802 printf("Failed to lock PLL for SGMII PHY %d\n", lane); 803 804 /* 805 * 21. Set COMPHY input port PIN_TX_IDLE=0 806 */ 807 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 808 0x0, rb_pin_tx_idle); 809 810 /* 811 * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. 812 * to start RX initialization. PIN_RX_INIT_DONE will be cleared to 813 * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE 814 * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after 815 * PIN_RX_INIT_DONE= 1. 816 * Please refer to RX initialization part for details. 817 */ 818 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 819 0x0); 820 821 ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */ 822 rb_rx_init_done, /* value */ 823 rb_rx_init_done, /* mask */ 824 PLL_LOCK_TIMEOUT, /* timeout */ 825 POLL_32B_REG); /* 32bit */ 826 if (ret == 0) 827 printf("Failed to init RX of SGMII PHY %d\n", lane); 828 829 debug_exit(); 830 831 return ret; 832 } 833 834 void comphy_dedicated_phys_init(void) 835 { 836 int node, usb32, ret = 1; 837 const void *blob = gd->fdt_blob; 838 839 debug_enter(); 840 841 for (usb32 = 0; usb32 <= 1; usb32++) { 842 /* 843 * There are 2 UTMI PHYs in this SOC. 844 * One is independendent and one is paired with USB3 port (OTG) 845 */ 846 if (usb32 == 0) { 847 node = fdt_node_offset_by_compatible( 848 blob, -1, "marvell,armada-3700-ehci"); 849 } else { 850 node = fdt_node_offset_by_compatible( 851 blob, -1, "marvell,armada3700-xhci"); 852 } 853 854 if (node > 0) { 855 if (fdtdec_get_is_enabled(blob, node)) { 856 ret = comphy_usb2_power_up(usb32); 857 if (ret == 0) 858 printf("Failed to initialize UTMI PHY\n"); 859 else 860 debug("UTMI PHY init succeed\n"); 861 } else { 862 debug("USB%d node is disabled\n", 863 usb32 == 0 ? 2 : 3); 864 } 865 } else { 866 debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3); 867 } 868 } 869 870 node = fdt_node_offset_by_compatible(blob, -1, 871 "marvell,armada-3700-ahci"); 872 if (node > 0) { 873 if (fdtdec_get_is_enabled(blob, node)) { 874 ret = comphy_sata_power_up(); 875 if (ret == 0) 876 printf("Failed to initialize SATA PHY\n"); 877 else 878 debug("SATA PHY init succeed\n"); 879 } else { 880 debug("SATA node is disabled\n"); 881 } 882 } else { 883 debug("No SATA node in DT\n"); 884 } 885 886 node = fdt_node_offset_by_compatible(blob, -1, 887 "marvell,armada-8k-sdhci"); 888 if (node <= 0) { 889 node = fdt_node_offset_by_compatible( 890 blob, -1, "marvell,armada-3700-sdhci"); 891 } 892 893 if (node > 0) { 894 if (fdtdec_get_is_enabled(blob, node)) { 895 ret = comphy_emmc_power_up(); 896 if (ret == 0) 897 printf("Failed to initialize SDIO/eMMC PHY\n"); 898 else 899 debug("SDIO/eMMC PHY init succeed\n"); 900 } else { 901 debug("SDIO/eMMC node is disabled\n"); 902 } 903 } else { 904 debug("No SDIO/eMMC node in DT\n"); 905 } 906 907 debug_exit(); 908 } 909 910 int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, 911 struct comphy_map *serdes_map) 912 { 913 struct comphy_map *comphy_map; 914 u32 comphy_max_count = chip_cfg->comphy_lanes_count; 915 u32 lane, ret = 0; 916 917 debug_enter(); 918 919 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; 920 lane++, comphy_map++) { 921 debug("Initialize serdes number %d\n", lane); 922 debug("Serdes type = 0x%x invert=%d\n", 923 comphy_map->type, comphy_map->invert); 924 925 switch (comphy_map->type) { 926 case PHY_TYPE_UNCONNECTED: 927 continue; 928 break; 929 930 case PHY_TYPE_PEX0: 931 ret = comphy_pcie_power_up(comphy_map->speed, 932 comphy_map->invert); 933 break; 934 935 case PHY_TYPE_USB3_HOST0: 936 case PHY_TYPE_USB3_DEVICE: 937 ret = comphy_usb3_power_up(comphy_map->type, 938 comphy_map->speed, 939 comphy_map->invert); 940 break; 941 942 case PHY_TYPE_SGMII0: 943 case PHY_TYPE_SGMII1: 944 ret = comphy_sgmii_power_up(lane, comphy_map->speed, 945 comphy_map->invert); 946 break; 947 948 default: 949 debug("Unknown SerDes type, skip initialize SerDes %d\n", 950 lane); 951 ret = 1; 952 break; 953 } 954 if (ret == 0) 955 printf("PLL is not locked - Failed to initialize lane %d\n", 956 lane); 957 } 958 959 debug_exit(); 960 return ret; 961 } 962