1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015-2016 Marvell International Ltd. 4 */ 5 6 #include <common.h> 7 #include <fdtdec.h> 8 #include <asm/io.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/soc.h> 11 12 #include "comphy_a3700.h" 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 struct sgmii_phy_init_data_fix { 17 u16 addr; 18 u16 value; 19 }; 20 21 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 22 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { 23 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, 24 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, 25 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, 26 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, 27 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, 28 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, 29 {0x104, 0x0C10} 30 }; 31 32 /* 40M1G25 mode init data */ 33 static u16 sgmii_phy_init[512] = { 34 /* 0 1 2 3 4 5 6 7 */ 35 /*-----------------------------------------------------------*/ 36 /* 8 9 A B C D E F */ 37 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 38 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 39 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 40 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 41 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 42 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 43 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 44 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 45 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 46 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 47 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 48 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 49 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 50 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 51 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 52 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 53 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 54 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 55 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 56 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 57 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 58 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 59 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 60 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 61 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 62 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 63 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 64 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 65 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 66 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 67 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 68 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 69 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 70 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 71 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 72 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 73 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 74 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 75 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 77 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 78 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 79 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 80 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 81 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 82 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 83 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 84 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 85 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 86 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 88 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 90 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 101 }; 102 103 /* 104 * comphy_poll_reg 105 * 106 * return: 1 on success, 0 on timeout 107 */ 108 static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u32 timeout, 109 u8 op_type) 110 { 111 u32 rval = 0xDEAD; 112 113 for (; timeout > 0; timeout--) { 114 if (op_type == POLL_16B_REG) 115 rval = readw(addr); /* 16 bit */ 116 else 117 rval = readl(addr) ; /* 32 bit */ 118 119 if ((rval & mask) == val) 120 return 1; 121 122 udelay(10000); 123 } 124 125 debug("Time out waiting (%p = %#010x)\n", addr, rval); 126 return 0; 127 } 128 129 /* 130 * comphy_pcie_power_up 131 * 132 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 133 */ 134 static int comphy_pcie_power_up(u32 speed, u32 invert) 135 { 136 int ret; 137 138 debug_enter(); 139 140 /* 141 * 1. Enable max PLL. 142 */ 143 reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE), 144 bf_use_max_pll_rate, 0); 145 146 /* 147 * 2. Select 20 bit SERDES interface. 148 */ 149 reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE), 150 bf_cfg_sel_20b, 0); 151 152 /* 153 * 3. Force to use reg setting for PCIe mode 154 */ 155 reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE), 156 bf_sel_bits_pcie_force, 0); 157 158 /* 159 * 4. Change RX wait 160 */ 161 reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF); 162 163 /* 164 * 5. Enable idle sync 165 */ 166 reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE), 167 0x60 | rb_idle_sync_en, 0xFFFF); 168 169 /* 170 * 6. Enable the output of 100M/125M/500M clock 171 */ 172 reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE), 173 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); 174 175 /* 176 * 7. Enable TX 177 */ 178 reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); 179 180 /* 181 * 8. Check crystal jumper setting and program the Power and PLL 182 * Control accordingly 183 */ 184 if (get_ref_clk() == 40) { 185 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), 186 0xFC63, 0xFFFF); /* 40 MHz */ 187 } else { 188 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), 189 0xFC62, 0xFFFF); /* 25 MHz */ 190 } 191 192 /* 193 * 9. Override Speed_PLL value and use MAC PLL 194 */ 195 reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE), 196 0x0040 | rb_use_max_pll_rate, 0xFFFF); 197 198 /* 199 * 10. Check the Polarity invert bit 200 */ 201 if (invert & PHY_POLARITY_TXD_INVERT) { 202 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), 203 phy_txd_inv, 0); 204 } 205 206 if (invert & PHY_POLARITY_RXD_INVERT) { 207 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), 208 phy_rxd_inv, 0); 209 } 210 211 /* 212 * 11. Release SW reset 213 */ 214 reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(PCIE), 215 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32, 216 bf_soft_rst | bf_mode_refdiv); 217 218 /* Wait for > 55 us to allow PCLK be enabled */ 219 udelay(PLL_SET_DELAY_US); 220 221 /* Assert PCLK enabled */ 222 ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(PCIE), /* address */ 223 rb_txdclk_pclk_en, /* value */ 224 rb_txdclk_pclk_en, /* mask */ 225 PLL_LOCK_TIMEOUT, /* timeout */ 226 POLL_16B_REG); /* 16bit */ 227 if (ret == 0) 228 printf("Failed to lock PCIe PLL\n"); 229 230 debug_exit(); 231 232 /* Return the status of the PLL */ 233 return ret; 234 } 235 236 /* 237 * comphy_sata_power_up 238 * 239 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 240 */ 241 static int comphy_sata_power_up(void) 242 { 243 int ret; 244 245 debug_enter(); 246 247 /* 248 * 0. Swap SATA TX lines 249 */ 250 reg_set((void __iomem *)rh_vsreg_addr, 251 vphy_sync_pattern_reg, 0xFFFFFFFF); 252 reg_set((void __iomem *)rh_vsreg_data, bs_txd_inv, bs_txd_inv); 253 254 /* 255 * 1. Select 40-bit data width width 256 */ 257 reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); 258 reg_set((void __iomem *)rh_vsreg_data, 0x800, bs_phyintf_40bit); 259 260 /* 261 * 2. Select reference clock and PHY mode (SATA) 262 */ 263 reg_set((void __iomem *)rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF); 264 if (get_ref_clk() == 40) { 265 reg_set((void __iomem *)rh_vsreg_data, 266 0x3, 0x00FF); /* 40 MHz */ 267 } else { 268 reg_set((void __iomem *)rh_vsreg_data, 269 0x1, 0x00FF); /* 25 MHz */ 270 } 271 272 /* 273 * 3. Use maximum PLL rate (no power save) 274 */ 275 reg_set((void __iomem *)rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF); 276 reg_set((void __iomem *)rh_vsreg_data, 277 bs_max_pll_rate, bs_max_pll_rate); 278 279 /* 280 * 4. Reset reserved bit (??) 281 */ 282 reg_set((void __iomem *)rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF); 283 reg_set((void __iomem *)rh_vsreg_data, 0, bs_phyctrl_frm_pin); 284 285 /* 286 * 5. Set vendor-specific configuration (??) 287 */ 288 reg_set((void __iomem *)rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); 289 reg_set((void __iomem *)rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); 290 291 /* Wait for > 55 us to allow PLL be enabled */ 292 udelay(PLL_SET_DELAY_US); 293 294 /* Assert SATA PLL enabled */ 295 reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); 296 ret = comphy_poll_reg((void *)rh_vsreg_data, /* address */ 297 bs_pll_ready_tx, /* value */ 298 bs_pll_ready_tx, /* mask */ 299 PLL_LOCK_TIMEOUT, /* timeout */ 300 POLL_32B_REG); /* 32bit */ 301 if (ret == 0) 302 printf("Failed to lock SATA PLL\n"); 303 304 debug_exit(); 305 306 return ret; 307 } 308 309 /* 310 * comphy_usb3_power_up 311 * 312 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 313 */ 314 static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) 315 { 316 int ret; 317 318 debug_enter(); 319 320 /* 321 * 1. Power up OTG module 322 */ 323 reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); 324 325 /* 326 * 2. Set counter for 100us pulse in USB3 Host and Device 327 * restore default burst size limit (Reference Clock 31:24) 328 */ 329 reg_set((void __iomem *)USB3_CTRPUL_VAL_REG, 330 0x8 << 24, rb_usb3_ctr_100ns); 331 332 333 /* 0xd005c300 = 0x1001 */ 334 /* set PRD_TXDEEMPH (3.5db de-emph) */ 335 reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF); 336 337 /* 338 * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in 339 * low impedance mode during electrical idle 340 */ 341 /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */ 342 /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */ 343 reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF); 344 345 346 /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ 347 reg_set16((void __iomem *)LANE_CFG4_ADDR(USB3), 348 bf_spread_spectrum_clock_en, 0x80); 349 350 /* 351 * set Override Margining Controls From the MAC: Use margining signals 352 * from lane configuration 353 */ 354 reg_set16((void __iomem *)TEST_MODE_CTRL_ADDR(USB3), 355 rb_mode_margin_override, 0xFFFF); 356 357 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ 358 /* set Mode Clock Source = PCLK is generated from REFCLK */ 359 reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF); 360 361 /* set G2 Spread Spectrum Clock Amplitude at 4K */ 362 reg_set16((void __iomem *)GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, 363 0xF000); 364 365 /* 366 * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register 367 * Master Current Select 368 */ 369 reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF); 370 371 /* 372 * 3. Check crystal jumper setting and program the Power and PLL 373 * Control accordingly 374 */ 375 if (get_ref_clk() == 40) { 376 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, 377 0xFFFF); /* 40 MHz */ 378 } else { 379 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, 380 0xFFFF); /* 25 MHz */ 381 } 382 383 /* 384 * 4. Change RX wait 385 */ 386 reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF); 387 388 /* 389 * 5. Enable idle sync 390 */ 391 reg_set16((void __iomem *)UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, 392 0xFFFF); 393 394 /* 395 * 6. Enable the output of 500M clock 396 */ 397 reg_set16((void __iomem *)MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, 398 0xFFFF); 399 400 /* 401 * 7. Set 20-bit data width 402 */ 403 reg_set16((void __iomem *)DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF); 404 405 /* 406 * 8. Override Speed_PLL value and use MAC PLL 407 */ 408 reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(USB3), 409 0x0040 | rb_use_max_pll_rate, 0xFFFF); 410 411 /* 412 * 9. Check the Polarity invert bit 413 */ 414 if (invert & PHY_POLARITY_TXD_INVERT) { 415 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), 416 phy_txd_inv, 0); 417 } 418 419 if (invert & PHY_POLARITY_RXD_INVERT) { 420 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), 421 phy_rxd_inv, 0); 422 } 423 424 /* 425 * 10. Release SW reset 426 */ 427 reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(USB3), 428 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20, 429 0xFFFF); 430 431 /* Wait for > 55 us to allow PCLK be enabled */ 432 udelay(PLL_SET_DELAY_US); 433 434 /* Assert PCLK enabled */ 435 ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(USB3), /* address */ 436 rb_txdclk_pclk_en, /* value */ 437 rb_txdclk_pclk_en, /* mask */ 438 PLL_LOCK_TIMEOUT, /* timeout */ 439 POLL_16B_REG); /* 16bit */ 440 if (ret == 0) 441 printf("Failed to lock USB3 PLL\n"); 442 443 /* 444 * Set Soft ID for Host mode (Device mode works with Hard ID 445 * detection) 446 */ 447 if (type == PHY_TYPE_USB3_HOST0) { 448 /* 449 * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) 450 * clear BIT1: set SOFT_ID = Host 451 * set BIT4: set INT_MODE = ID. Interrupt Mode: enable 452 * interrupt by ID instead of using both interrupts 453 * of HOST and Device ORed simultaneously 454 * INT_MODE=ID in order to avoid unexpected 455 * behaviour or both interrupts together 456 */ 457 reg_set((void __iomem *)USB32_CTRL_BASE, 458 usb32_ctrl_id_mode | usb32_ctrl_int_mode, 459 usb32_ctrl_id_mode | usb32_ctrl_soft_id | 460 usb32_ctrl_int_mode); 461 } 462 463 debug_exit(); 464 465 return ret; 466 } 467 468 /* 469 * comphy_usb2_power_up 470 * 471 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 472 */ 473 static int comphy_usb2_power_up(u8 usb32) 474 { 475 int ret; 476 477 debug_enter(); 478 479 if (usb32 != 0 && usb32 != 1) { 480 printf("invalid usb32 value: (%d), should be either 0 or 1\n", 481 usb32); 482 debug_exit(); 483 return 0; 484 } 485 486 /* 487 * 0. Setup PLL. 40MHz clock uses defaults. 488 * See "PLL Settings for Typical REFCLK" table 489 */ 490 if (get_ref_clk() == 25) { 491 reg_set((void __iomem *)USB2_PHY_BASE(usb32), 492 5 | (96 << 16), 0x3F | (0xFF << 16) | (0x3 << 28)); 493 } 494 495 /* 496 * 1. PHY pull up and disable USB2 suspend 497 */ 498 reg_set((void __iomem *)USB2_PHY_CTRL_ADDR(usb32), 499 RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0); 500 501 if (usb32 != 0) { 502 /* 503 * 2. Power up OTG module 504 */ 505 reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); 506 507 /* 508 * 3. Configure PHY charger detection 509 */ 510 reg_set((void __iomem *)USB2_PHY_CHRGR_DET_ADDR, 0, 511 rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto | 512 rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc); 513 } 514 515 /* Assert PLL calibration done */ 516 ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32), 517 rb_usb2phy_pllcal_done, /* value */ 518 rb_usb2phy_pllcal_done, /* mask */ 519 PLL_LOCK_TIMEOUT, /* timeout */ 520 POLL_32B_REG); /* 32bit */ 521 if (ret == 0) 522 printf("Failed to end USB2 PLL calibration\n"); 523 524 /* Assert impedance calibration done */ 525 ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32), 526 rb_usb2phy_impcal_done, /* value */ 527 rb_usb2phy_impcal_done, /* mask */ 528 PLL_LOCK_TIMEOUT, /* timeout */ 529 POLL_32B_REG); /* 32bit */ 530 if (ret == 0) 531 printf("Failed to end USB2 impedance calibration\n"); 532 533 /* Assert squetch calibration done */ 534 ret = comphy_poll_reg((void *)USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), 535 rb_usb2phy_sqcal_done, /* value */ 536 rb_usb2phy_sqcal_done, /* mask */ 537 PLL_LOCK_TIMEOUT, /* timeout */ 538 POLL_32B_REG); /* 32bit */ 539 if (ret == 0) 540 printf("Failed to end USB2 unknown calibration\n"); 541 542 /* Assert PLL is ready */ 543 ret = comphy_poll_reg((void *)USB2_PHY_PLL_CTRL0_ADDR(usb32), 544 rb_usb2phy_pll_ready, /* value */ 545 rb_usb2phy_pll_ready, /* mask */ 546 PLL_LOCK_TIMEOUT, /* timeout */ 547 POLL_32B_REG); /* 32bit */ 548 549 if (ret == 0) 550 printf("Failed to lock USB2 PLL\n"); 551 552 debug_exit(); 553 554 return ret; 555 } 556 557 /* 558 * comphy_emmc_power_up 559 * 560 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 561 */ 562 static int comphy_emmc_power_up(void) 563 { 564 debug_enter(); 565 566 /* 567 * 1. Bus power ON, Bus voltage 1.8V 568 */ 569 reg_set((void __iomem *)SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); 570 571 /* 572 * 2. Set FIFO parameters 573 */ 574 reg_set((void __iomem *)SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); 575 576 /* 577 * 3. Set Capabilities 1_2 578 */ 579 reg_set((void __iomem *)SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); 580 581 /* 582 * 4. Set Endian 583 */ 584 reg_set((void __iomem *)SDIO_ENDIAN_ADDR, 0x00c00000, 0); 585 586 /* 587 * 4. Init PHY 588 */ 589 reg_set((void __iomem *)SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); 590 reg_set((void __iomem *)SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 591 0xF0000000); 592 593 /* 594 * 5. DLL reset 595 */ 596 reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); 597 reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0x00010000, 0); 598 599 debug_exit(); 600 601 return 1; 602 } 603 604 /* 605 * comphy_sgmii_power_up 606 * 607 * return: 608 */ 609 static void comphy_sgmii_phy_init(u32 lane, u32 speed) 610 { 611 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); 612 int addr, fix_idx; 613 u16 val; 614 615 fix_idx = 0; 616 for (addr = 0; addr < 512; addr++) { 617 /* 618 * All PHY register values are defined in full for 3.125Gbps 619 * SERDES speed. The values required for 1.25 Gbps are almost 620 * the same and only few registers should be "fixed" in 621 * comparison to 3.125 Gbps values. These register values are 622 * stored in "sgmii_phy_init_fix" array. 623 */ 624 if ((speed != PHY_SPEED_1_25G) && 625 (sgmii_phy_init_fix[fix_idx].addr == addr)) { 626 /* Use new value */ 627 val = sgmii_phy_init_fix[fix_idx].value; 628 if (fix_idx < fix_arr_sz) 629 fix_idx++; 630 } else { 631 val = sgmii_phy_init[addr]; 632 } 633 634 phy_write16(lane, addr, val, 0xFFFF); 635 } 636 } 637 638 /* 639 * comphy_sgmii_power_up 640 * 641 * return: 1 if PLL locked (OK), 0 otherwise (FAIL) 642 */ 643 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) 644 { 645 int ret; 646 647 debug_enter(); 648 649 /* 650 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 651 */ 652 reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); 653 654 /* 655 * 2. Reset PHY by setting PHY input port PIN_RESET=1. 656 * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 657 * PHY TXP/TXN output to idle state during PHY initialization 658 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 659 */ 660 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 661 rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref, 662 rb_pin_reset_core | rb_pin_pu_pll | 663 rb_pin_pu_rx | rb_pin_pu_tx); 664 665 /* 666 * 5. Release reset to the PHY by setting PIN_RESET=0. 667 */ 668 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 669 0, rb_pin_reset_comphy); 670 671 /* 672 * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide 673 * COMPHY bit rate 674 */ 675 if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ 676 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 677 (0x8 << rf_gen_rx_sel_shift) | 678 (0x8 << rf_gen_tx_sel_shift), 679 rf_gen_rx_select | rf_gen_tx_select); 680 681 } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ 682 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 683 (0x6 << rf_gen_rx_sel_shift) | 684 (0x6 << rf_gen_tx_sel_shift), 685 rf_gen_rx_select | rf_gen_tx_select); 686 } else { 687 printf("Unsupported COMPHY speed!\n"); 688 return 0; 689 } 690 691 /* 692 * 8. Wait 1mS for bandgap and reference clocks to stabilize; 693 * then start SW programming. 694 */ 695 mdelay(10); 696 697 /* 9. Program COMPHY register PHY_MODE */ 698 phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, 699 PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); 700 701 /* 702 * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK 703 * source 704 */ 705 phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel); 706 707 /* 708 * 11. Set correct reference clock frequency in COMPHY register 709 * REF_FREF_SEL. 710 */ 711 if (get_ref_clk() == 40) { 712 phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, 713 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); 714 } else { 715 /* 25MHz */ 716 phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, 717 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); 718 } 719 720 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ 721 /* 722 * This step is mentioned in the flow received from verification team. 723 * However the PHY_GEN_MAX value is only meaningful for other 724 * interfaces (not SGMII). For instance, it selects SATA speed 725 * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps 726 */ 727 728 /* 729 * 13. Program COMPHY register SEL_BITS to set correct parallel data 730 * bus width 731 */ 732 /* 10bit */ 733 phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask); 734 735 /* 736 * 14. As long as DFE function needs to be enabled in any mode, 737 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 738 * for real chip during COMPHY power on. 739 */ 740 /* 741 * The step 14 exists (and empty) in the original initialization flow 742 * obtained from the verification team. According to the functional 743 * specification DFE_UPDATE_EN already has the default value 0x3F 744 */ 745 746 /* 747 * 15. Program COMPHY GEN registers. 748 * These registers should be programmed based on the lab testing 749 * result to achieve optimal performance. Please contact the CEA 750 * group to get the related GEN table during real chip bring-up. 751 * We only requred to run though the entire registers programming 752 * flow defined by "comphy_sgmii_phy_init" when the REF clock is 753 * 40 MHz. For REF clock 25 MHz the default values stored in PHY 754 * registers are OK. 755 */ 756 debug("Running C-DPI phy init %s mode\n", 757 speed == PHY_SPEED_3_125G ? "2G5" : "1G"); 758 if (get_ref_clk() == 40) 759 comphy_sgmii_phy_init(lane, speed); 760 761 /* 762 * 16. [Simulation Only] should not be used for real chip. 763 * By pass power up calibration by programming EXT_FORCE_CAL_DONE 764 * (R02h[9]) to 1 to shorten COMPHY simulation time. 765 */ 766 /* 767 * 17. [Simulation Only: should not be used for real chip] 768 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX 769 * training simulation time. 770 */ 771 772 /* 773 * 18. Check the PHY Polarity invert bit 774 */ 775 if (invert & PHY_POLARITY_TXD_INVERT) 776 phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0); 777 778 if (invert & PHY_POLARITY_RXD_INVERT) 779 phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0); 780 781 /* 782 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 783 * to start PHY power up sequence. All the PHY register 784 * programming should be done before PIN_PU_PLL=1. There should be 785 * no register programming for normal PHY operation from this point. 786 */ 787 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 788 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx, 789 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx); 790 791 /* 792 * 20. Wait for PHY power up sequence to finish by checking output ports 793 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 794 */ 795 ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */ 796 rb_pll_ready_tx | rb_pll_ready_rx, /* value */ 797 rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ 798 PLL_LOCK_TIMEOUT, /* timeout */ 799 POLL_32B_REG); /* 32bit */ 800 if (ret == 0) 801 printf("Failed to lock PLL for SGMII PHY %d\n", lane); 802 803 /* 804 * 21. Set COMPHY input port PIN_TX_IDLE=0 805 */ 806 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), 807 0x0, rb_pin_tx_idle); 808 809 /* 810 * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. 811 * to start RX initialization. PIN_RX_INIT_DONE will be cleared to 812 * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE 813 * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after 814 * PIN_RX_INIT_DONE= 1. 815 * Please refer to RX initialization part for details. 816 */ 817 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 818 0x0); 819 820 ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */ 821 rb_rx_init_done, /* value */ 822 rb_rx_init_done, /* mask */ 823 PLL_LOCK_TIMEOUT, /* timeout */ 824 POLL_32B_REG); /* 32bit */ 825 if (ret == 0) 826 printf("Failed to init RX of SGMII PHY %d\n", lane); 827 828 debug_exit(); 829 830 return ret; 831 } 832 833 void comphy_dedicated_phys_init(void) 834 { 835 int node, usb32, ret = 1; 836 const void *blob = gd->fdt_blob; 837 838 debug_enter(); 839 840 for (usb32 = 0; usb32 <= 1; usb32++) { 841 /* 842 * There are 2 UTMI PHYs in this SOC. 843 * One is independendent and one is paired with USB3 port (OTG) 844 */ 845 if (usb32 == 0) { 846 node = fdt_node_offset_by_compatible( 847 blob, -1, "marvell,armada-3700-ehci"); 848 } else { 849 node = fdt_node_offset_by_compatible( 850 blob, -1, "marvell,armada3700-xhci"); 851 } 852 853 if (node > 0) { 854 if (fdtdec_get_is_enabled(blob, node)) { 855 ret = comphy_usb2_power_up(usb32); 856 if (ret == 0) 857 printf("Failed to initialize UTMI PHY\n"); 858 else 859 debug("UTMI PHY init succeed\n"); 860 } else { 861 debug("USB%d node is disabled\n", 862 usb32 == 0 ? 2 : 3); 863 } 864 } else { 865 debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3); 866 } 867 } 868 869 node = fdt_node_offset_by_compatible(blob, -1, 870 "marvell,armada-3700-ahci"); 871 if (node > 0) { 872 if (fdtdec_get_is_enabled(blob, node)) { 873 ret = comphy_sata_power_up(); 874 if (ret == 0) 875 printf("Failed to initialize SATA PHY\n"); 876 else 877 debug("SATA PHY init succeed\n"); 878 } else { 879 debug("SATA node is disabled\n"); 880 } 881 } else { 882 debug("No SATA node in DT\n"); 883 } 884 885 node = fdt_node_offset_by_compatible(blob, -1, 886 "marvell,armada-8k-sdhci"); 887 if (node <= 0) { 888 node = fdt_node_offset_by_compatible( 889 blob, -1, "marvell,armada-3700-sdhci"); 890 } 891 892 if (node > 0) { 893 if (fdtdec_get_is_enabled(blob, node)) { 894 ret = comphy_emmc_power_up(); 895 if (ret == 0) 896 printf("Failed to initialize SDIO/eMMC PHY\n"); 897 else 898 debug("SDIO/eMMC PHY init succeed\n"); 899 } else { 900 debug("SDIO/eMMC node is disabled\n"); 901 } 902 } else { 903 debug("No SDIO/eMMC node in DT\n"); 904 } 905 906 debug_exit(); 907 } 908 909 int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, 910 struct comphy_map *serdes_map) 911 { 912 struct comphy_map *comphy_map; 913 u32 comphy_max_count = chip_cfg->comphy_lanes_count; 914 u32 lane, ret = 0; 915 916 debug_enter(); 917 918 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; 919 lane++, comphy_map++) { 920 debug("Initialize serdes number %d\n", lane); 921 debug("Serdes type = 0x%x invert=%d\n", 922 comphy_map->type, comphy_map->invert); 923 924 switch (comphy_map->type) { 925 case PHY_TYPE_UNCONNECTED: 926 continue; 927 break; 928 929 case PHY_TYPE_PEX0: 930 ret = comphy_pcie_power_up(comphy_map->speed, 931 comphy_map->invert); 932 break; 933 934 case PHY_TYPE_USB3_HOST0: 935 case PHY_TYPE_USB3_DEVICE: 936 ret = comphy_usb3_power_up(comphy_map->type, 937 comphy_map->speed, 938 comphy_map->invert); 939 break; 940 941 case PHY_TYPE_SGMII0: 942 case PHY_TYPE_SGMII1: 943 ret = comphy_sgmii_power_up(lane, comphy_map->speed, 944 comphy_map->invert); 945 break; 946 947 default: 948 debug("Unknown SerDes type, skip initialize SerDes %d\n", 949 lane); 950 ret = 1; 951 break; 952 } 953 if (ret == 0) 954 printf("PLL is not locked - Failed to initialize lane %d\n", 955 lane); 956 } 957 958 debug_exit(); 959 return ret; 960 } 961