1 /* 2 * Freescale i.MX6 PCI Express Root-Complex driver 3 * 4 * Copyright (C) 2013 Marek Vasut <marex@denx.de> 5 * 6 * Based on upstream Linux kernel driver: 7 * pci-imx6.c: Sean Cross <xobs@kosagi.com> 8 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <pci.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/iomux.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/gpio.h> 19 #include <asm/io.h> 20 #include <linux/sizes.h> 21 #include <errno.h> 22 23 #define PCI_ACCESS_READ 0 24 #define PCI_ACCESS_WRITE 1 25 26 #ifdef CONFIG_MX6SX 27 #define MX6_DBI_ADDR 0x08ffc000 28 #define MX6_IO_ADDR 0x08000000 29 #define MX6_MEM_ADDR 0x08100000 30 #define MX6_ROOT_ADDR 0x08f00000 31 #else 32 #define MX6_DBI_ADDR 0x01ffc000 33 #define MX6_IO_ADDR 0x01000000 34 #define MX6_MEM_ADDR 0x01100000 35 #define MX6_ROOT_ADDR 0x01f00000 36 #endif 37 #define MX6_DBI_SIZE 0x4000 38 #define MX6_IO_SIZE 0x100000 39 #define MX6_MEM_SIZE 0xe00000 40 #define MX6_ROOT_SIZE 0xfc000 41 42 /* PCIe Port Logic registers (memory-mapped) */ 43 #define PL_OFFSET 0x700 44 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) 45 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) 46 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) 47 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) 48 49 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 50 #define PCIE_PHY_CTRL_DATA_LOC 0 51 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 52 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 53 #define PCIE_PHY_CTRL_WR_LOC 18 54 #define PCIE_PHY_CTRL_RD_LOC 19 55 56 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 57 #define PCIE_PHY_STAT_DATA_LOC 0 58 #define PCIE_PHY_STAT_ACK_LOC 16 59 60 /* PHY registers (not memory-mapped) */ 61 #define PCIE_PHY_RX_ASIC_OUT 0x100D 62 63 #define PHY_RX_OVRD_IN_LO 0x1005 64 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) 65 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) 66 67 #define PCIE_PHY_PUP_REQ (1 << 7) 68 69 /* iATU registers */ 70 #define PCIE_ATU_VIEWPORT 0x900 71 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) 72 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 73 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 74 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 75 #define PCIE_ATU_CR1 0x904 76 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 77 #define PCIE_ATU_TYPE_IO (0x2 << 0) 78 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 79 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 80 #define PCIE_ATU_CR2 0x908 81 #define PCIE_ATU_ENABLE (0x1 << 31) 82 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 83 #define PCIE_ATU_LOWER_BASE 0x90C 84 #define PCIE_ATU_UPPER_BASE 0x910 85 #define PCIE_ATU_LIMIT 0x914 86 #define PCIE_ATU_LOWER_TARGET 0x918 87 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 88 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 89 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 90 #define PCIE_ATU_UPPER_TARGET 0x91C 91 92 /* 93 * PHY access functions 94 */ 95 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) 96 { 97 u32 val; 98 u32 max_iterations = 10; 99 u32 wait_counter = 0; 100 101 do { 102 val = readl(dbi_base + PCIE_PHY_STAT); 103 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; 104 wait_counter++; 105 106 if (val == exp_val) 107 return 0; 108 109 udelay(1); 110 } while (wait_counter < max_iterations); 111 112 return -ETIMEDOUT; 113 } 114 115 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) 116 { 117 u32 val; 118 int ret; 119 120 val = addr << PCIE_PHY_CTRL_DATA_LOC; 121 writel(val, dbi_base + PCIE_PHY_CTRL); 122 123 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); 124 writel(val, dbi_base + PCIE_PHY_CTRL); 125 126 ret = pcie_phy_poll_ack(dbi_base, 1); 127 if (ret) 128 return ret; 129 130 val = addr << PCIE_PHY_CTRL_DATA_LOC; 131 writel(val, dbi_base + PCIE_PHY_CTRL); 132 133 ret = pcie_phy_poll_ack(dbi_base, 0); 134 if (ret) 135 return ret; 136 137 return 0; 138 } 139 140 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 141 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) 142 { 143 u32 val, phy_ctl; 144 int ret; 145 146 ret = pcie_phy_wait_ack(dbi_base, addr); 147 if (ret) 148 return ret; 149 150 /* assert Read signal */ 151 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; 152 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); 153 154 ret = pcie_phy_poll_ack(dbi_base, 1); 155 if (ret) 156 return ret; 157 158 val = readl(dbi_base + PCIE_PHY_STAT); 159 *data = val & 0xffff; 160 161 /* deassert Read signal */ 162 writel(0x00, dbi_base + PCIE_PHY_CTRL); 163 164 ret = pcie_phy_poll_ack(dbi_base, 0); 165 if (ret) 166 return ret; 167 168 return 0; 169 } 170 171 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) 172 { 173 u32 var; 174 int ret; 175 176 /* write addr */ 177 /* cap addr */ 178 ret = pcie_phy_wait_ack(dbi_base, addr); 179 if (ret) 180 return ret; 181 182 var = data << PCIE_PHY_CTRL_DATA_LOC; 183 writel(var, dbi_base + PCIE_PHY_CTRL); 184 185 /* capture data */ 186 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); 187 writel(var, dbi_base + PCIE_PHY_CTRL); 188 189 ret = pcie_phy_poll_ack(dbi_base, 1); 190 if (ret) 191 return ret; 192 193 /* deassert cap data */ 194 var = data << PCIE_PHY_CTRL_DATA_LOC; 195 writel(var, dbi_base + PCIE_PHY_CTRL); 196 197 /* wait for ack de-assertion */ 198 ret = pcie_phy_poll_ack(dbi_base, 0); 199 if (ret) 200 return ret; 201 202 /* assert wr signal */ 203 var = 0x1 << PCIE_PHY_CTRL_WR_LOC; 204 writel(var, dbi_base + PCIE_PHY_CTRL); 205 206 /* wait for ack */ 207 ret = pcie_phy_poll_ack(dbi_base, 1); 208 if (ret) 209 return ret; 210 211 /* deassert wr signal */ 212 var = data << PCIE_PHY_CTRL_DATA_LOC; 213 writel(var, dbi_base + PCIE_PHY_CTRL); 214 215 /* wait for ack de-assertion */ 216 ret = pcie_phy_poll_ack(dbi_base, 0); 217 if (ret) 218 return ret; 219 220 writel(0x0, dbi_base + PCIE_PHY_CTRL); 221 222 return 0; 223 } 224 225 static int imx6_pcie_link_up(void) 226 { 227 u32 rc, ltssm; 228 int rx_valid, temp; 229 230 /* link is debug bit 36, debug register 1 starts at bit 32 */ 231 rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1); 232 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) && 233 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)) 234 return -EAGAIN; 235 236 /* 237 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. 238 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). 239 * If (MAC/LTSSM.state == Recovery.RcvrLock) 240 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition 241 * to gen2 is stuck 242 */ 243 pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid); 244 ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F; 245 246 if (rx_valid & 0x01) 247 return 0; 248 249 if (ltssm != 0x0d) 250 return 0; 251 252 printf("transition to gen2 is stuck, reset PHY!\n"); 253 254 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); 255 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); 256 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); 257 258 udelay(3000); 259 260 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); 261 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); 262 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); 263 264 return 0; 265 } 266 267 /* 268 * iATU region setup 269 */ 270 static int imx_pcie_regions_setup(void) 271 { 272 /* 273 * i.MX6 defines 16MB in the AXI address map for PCIe. 274 * 275 * That address space excepted the pcie registers is 276 * split and defined into different regions by iATU, 277 * with sizes and offsets as follows: 278 * 279 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO 280 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM 281 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers 282 */ 283 284 /* CMD reg:I/O space, MEM space, and Bus Master Enable */ 285 setbits_le32(MX6_DBI_ADDR | PCI_COMMAND, 286 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 287 288 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ 289 setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION, 290 PCI_CLASS_BRIDGE_PCI << 16); 291 292 /* Region #0 is used for Outbound CFG space access. */ 293 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); 294 295 writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE); 296 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE); 297 writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT); 298 299 writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); 300 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET); 301 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); 302 writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2); 303 304 return 0; 305 } 306 307 /* 308 * PCI Express accessors 309 */ 310 static uint32_t get_bus_address(pci_dev_t d, int where) 311 { 312 uint32_t va_address; 313 314 /* Reconfigure Region #0 */ 315 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); 316 317 if (PCI_BUS(d) < 2) 318 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); 319 else 320 writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1); 321 322 if (PCI_BUS(d) == 0) { 323 va_address = MX6_DBI_ADDR; 324 } else { 325 writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); 326 va_address = MX6_IO_ADDR + SZ_16M - SZ_1M; 327 } 328 329 va_address += (where & ~0x3); 330 331 return va_address; 332 } 333 334 static int imx_pcie_addr_valid(pci_dev_t d) 335 { 336 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1)) 337 return -EINVAL; 338 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0)) 339 return -EINVAL; 340 return 0; 341 } 342 343 /* 344 * Replace the original ARM DABT handler with a simple jump-back one. 345 * 346 * The problem here is that if we have a PCIe bridge attached to this PCIe 347 * controller, but no PCIe device is connected to the bridges' downstream 348 * port, the attempt to read/write from/to the config space will produce 349 * a DABT. This is a behavior of the controller and can not be disabled 350 * unfortuatelly. 351 * 352 * To work around the problem, we backup the current DABT handler address 353 * and replace it with our own DABT handler, which only bounces right back 354 * into the code. 355 */ 356 static void imx_pcie_fix_dabt_handler(bool set) 357 { 358 extern uint32_t *_data_abort; 359 uint32_t *data_abort_addr = (uint32_t *)&_data_abort; 360 361 static const uint32_t data_abort_bounce_handler = 0xe25ef004; 362 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler; 363 364 static uint32_t data_abort_backup; 365 366 if (set) { 367 data_abort_backup = *data_abort_addr; 368 *data_abort_addr = data_abort_bounce_addr; 369 } else { 370 *data_abort_addr = data_abort_backup; 371 } 372 } 373 374 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, 375 int where, u32 *val) 376 { 377 uint32_t va_address; 378 int ret; 379 380 ret = imx_pcie_addr_valid(d); 381 if (ret) { 382 *val = 0xffffffff; 383 return ret; 384 } 385 386 va_address = get_bus_address(d, where); 387 388 /* 389 * Read the PCIe config space. We must replace the DABT handler 390 * here in case we got data abort from the PCIe controller, see 391 * imx_pcie_fix_dabt_handler() description. Note that writing the 392 * "val" with valid value is also imperative here as in case we 393 * did got DABT, the val would contain random value. 394 */ 395 imx_pcie_fix_dabt_handler(true); 396 writel(0xffffffff, val); 397 *val = readl(va_address); 398 imx_pcie_fix_dabt_handler(false); 399 400 return 0; 401 } 402 403 static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, 404 int where, u32 val) 405 { 406 uint32_t va_address = 0; 407 int ret; 408 409 ret = imx_pcie_addr_valid(d); 410 if (ret) 411 return ret; 412 413 va_address = get_bus_address(d, where); 414 415 /* 416 * Write the PCIe config space. We must replace the DABT handler 417 * here in case we got data abort from the PCIe controller, see 418 * imx_pcie_fix_dabt_handler() description. 419 */ 420 imx_pcie_fix_dabt_handler(true); 421 writel(val, va_address); 422 imx_pcie_fix_dabt_handler(false); 423 424 return 0; 425 } 426 427 /* 428 * Initial bus setup 429 */ 430 static int imx6_pcie_assert_core_reset(void) 431 { 432 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 433 #if defined(CONFIG_MX6SX) 434 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; 435 436 /* SSP_EN is not used on MX6SX anymore */ 437 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); 438 /* Force PCIe PHY reset */ 439 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); 440 /* Power up PCIe PHY */ 441 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); 442 #else 443 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); 444 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); 445 #endif 446 447 return 0; 448 } 449 450 static int imx6_pcie_init_phy(void) 451 { 452 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 453 454 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); 455 456 clrsetbits_le32(&iomuxc_regs->gpr[12], 457 IOMUXC_GPR12_DEVICE_TYPE_MASK, 458 IOMUXC_GPR12_DEVICE_TYPE_RC); 459 clrsetbits_le32(&iomuxc_regs->gpr[12], 460 IOMUXC_GPR12_LOS_LEVEL_MASK, 461 IOMUXC_GPR12_LOS_LEVEL_9); 462 463 #ifdef CONFIG_MX6SX 464 clrsetbits_le32(&iomuxc_regs->gpr[12], 465 IOMUXC_GPR12_RX_EQ_MASK, 466 IOMUXC_GPR12_RX_EQ_2); 467 #endif 468 469 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | 470 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | 471 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | 472 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) | 473 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET), 474 &iomuxc_regs->gpr[8]); 475 476 return 0; 477 } 478 479 __weak int imx6_pcie_toggle_power(void) 480 { 481 #ifdef CONFIG_PCIE_IMX_POWER_GPIO 482 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); 483 mdelay(20); 484 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); 485 mdelay(20); 486 #endif 487 return 0; 488 } 489 490 __weak int imx6_pcie_toggle_reset(void) 491 { 492 /* 493 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1' 494 * for detailed understanding of the PCIe CR reset logic. 495 * 496 * The PCIe #PERST reset line _MUST_ be connected, otherwise your 497 * design does not conform to the specification. You must wait at 498 * least 20 mS after de-asserting the #PERST so the EP device can 499 * do self-initialisation. 500 * 501 * In case your #PERST pin is connected to a plain GPIO pin of the 502 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's 503 * configuration file and the condition below will handle the rest 504 * of the reset toggling. 505 * 506 * In case your #PERST toggling logic is more complex, for example 507 * connected via CPLD or somesuch, you can override this function 508 * in your board file and implement reset logic as needed. You must 509 * not forget to wait at least 20 mS after de-asserting #PERST in 510 * this case either though. 511 * 512 * In case your #PERST line of the PCIe EP device is not connected 513 * at all, your design is broken and you should fix your design, 514 * otherwise you will observe problems like for example the link 515 * not coming up after rebooting the system back from running Linux 516 * that uses the PCIe as well OR the PCIe link might not come up in 517 * Linux at all in the first place since it's in some non-reset 518 * state due to being previously used in U-Boot. 519 */ 520 #ifdef CONFIG_PCIE_IMX_PERST_GPIO 521 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); 522 mdelay(20); 523 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); 524 mdelay(20); 525 #else 526 puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); 527 #endif 528 return 0; 529 } 530 531 static int imx6_pcie_deassert_core_reset(void) 532 { 533 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 534 535 imx6_pcie_toggle_power(); 536 537 enable_pcie_clock(); 538 539 /* 540 * Wait for the clock to settle a bit, when the clock are sourced 541 * from the CPU, we need about 30mS to settle. 542 */ 543 mdelay(50); 544 545 #if defined(CONFIG_MX6SX) 546 /* SSP_EN is not used on MX6SX anymore */ 547 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); 548 /* Clear PCIe PHY reset bit */ 549 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); 550 #else 551 /* Enable PCIe */ 552 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); 553 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); 554 #endif 555 556 imx6_pcie_toggle_reset(); 557 558 return 0; 559 } 560 561 static int imx_pcie_link_up(void) 562 { 563 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 564 uint32_t tmp; 565 int count = 0; 566 567 imx6_pcie_assert_core_reset(); 568 imx6_pcie_init_phy(); 569 imx6_pcie_deassert_core_reset(); 570 571 imx_pcie_regions_setup(); 572 573 /* 574 * FIXME: Force the PCIe RC to Gen1 operation 575 * The RC must be forced into Gen1 mode before bringing the link 576 * up, otherwise no downstream devices are detected. After the 577 * link is up, a managed Gen1->Gen2 transition can be initiated. 578 */ 579 tmp = readl(MX6_DBI_ADDR + 0x7c); 580 tmp &= ~0xf; 581 tmp |= 0x1; 582 writel(tmp, MX6_DBI_ADDR + 0x7c); 583 584 /* LTSSM enable, starting link. */ 585 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); 586 587 while (!imx6_pcie_link_up()) { 588 udelay(10); 589 count++; 590 if (count >= 2000) { 591 debug("phy link never came up\n"); 592 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 593 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), 594 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); 595 return -EINVAL; 596 } 597 } 598 599 return 0; 600 } 601 602 void imx_pcie_init(void) 603 { 604 /* Static instance of the controller. */ 605 static struct pci_controller pcc; 606 struct pci_controller *hose = &pcc; 607 int ret; 608 609 memset(&pcc, 0, sizeof(pcc)); 610 611 /* PCI I/O space */ 612 pci_set_region(&hose->regions[0], 613 MX6_IO_ADDR, MX6_IO_ADDR, 614 MX6_IO_SIZE, PCI_REGION_IO); 615 616 /* PCI memory space */ 617 pci_set_region(&hose->regions[1], 618 MX6_MEM_ADDR, MX6_MEM_ADDR, 619 MX6_MEM_SIZE, PCI_REGION_MEM); 620 621 /* System memory space */ 622 pci_set_region(&hose->regions[2], 623 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR, 624 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 625 626 hose->region_count = 3; 627 628 pci_set_ops(hose, 629 pci_hose_read_config_byte_via_dword, 630 pci_hose_read_config_word_via_dword, 631 imx_pcie_read_config, 632 pci_hose_write_config_byte_via_dword, 633 pci_hose_write_config_word_via_dword, 634 imx_pcie_write_config); 635 636 /* Start the controller. */ 637 ret = imx_pcie_link_up(); 638 639 if (!ret) { 640 pci_register_hose(hose); 641 hose->last_busno = pci_hose_scan(hose); 642 } 643 } 644 645 /* Probe function. */ 646 void pci_init_board(void) 647 { 648 imx_pcie_init(); 649 } 650