1 /* 2 * Freescale i.MX6 PCI Express Root-Complex driver 3 * 4 * Copyright (C) 2013 Marek Vasut <marex@denx.de> 5 * 6 * Based on upstream Linux kernel driver: 7 * pci-imx6.c: Sean Cross <xobs@kosagi.com> 8 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <pci.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/iomux.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/gpio.h> 19 #include <asm/io.h> 20 #include <linux/sizes.h> 21 #include <errno.h> 22 #include <asm/arch/sys_proto.h> 23 24 #define PCI_ACCESS_READ 0 25 #define PCI_ACCESS_WRITE 1 26 27 #ifdef CONFIG_MX6SX 28 #define MX6_DBI_ADDR 0x08ffc000 29 #define MX6_IO_ADDR 0x08000000 30 #define MX6_MEM_ADDR 0x08100000 31 #define MX6_ROOT_ADDR 0x08f00000 32 #else 33 #define MX6_DBI_ADDR 0x01ffc000 34 #define MX6_IO_ADDR 0x01000000 35 #define MX6_MEM_ADDR 0x01100000 36 #define MX6_ROOT_ADDR 0x01f00000 37 #endif 38 #define MX6_DBI_SIZE 0x4000 39 #define MX6_IO_SIZE 0x100000 40 #define MX6_MEM_SIZE 0xe00000 41 #define MX6_ROOT_SIZE 0xfc000 42 43 /* PCIe Port Logic registers (memory-mapped) */ 44 #define PL_OFFSET 0x700 45 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) 46 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) 47 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) 48 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) 49 50 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 51 #define PCIE_PHY_CTRL_DATA_LOC 0 52 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 53 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 54 #define PCIE_PHY_CTRL_WR_LOC 18 55 #define PCIE_PHY_CTRL_RD_LOC 19 56 57 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 58 #define PCIE_PHY_STAT_DATA_LOC 0 59 #define PCIE_PHY_STAT_ACK_LOC 16 60 61 /* PHY registers (not memory-mapped) */ 62 #define PCIE_PHY_RX_ASIC_OUT 0x100D 63 64 #define PHY_RX_OVRD_IN_LO 0x1005 65 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) 66 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) 67 68 #define PCIE_PHY_PUP_REQ (1 << 7) 69 70 /* iATU registers */ 71 #define PCIE_ATU_VIEWPORT 0x900 72 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) 73 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 74 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 75 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 76 #define PCIE_ATU_CR1 0x904 77 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 78 #define PCIE_ATU_TYPE_IO (0x2 << 0) 79 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 80 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 81 #define PCIE_ATU_CR2 0x908 82 #define PCIE_ATU_ENABLE (0x1 << 31) 83 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 84 #define PCIE_ATU_LOWER_BASE 0x90C 85 #define PCIE_ATU_UPPER_BASE 0x910 86 #define PCIE_ATU_LIMIT 0x914 87 #define PCIE_ATU_LOWER_TARGET 0x918 88 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 89 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 90 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 91 #define PCIE_ATU_UPPER_TARGET 0x91C 92 93 /* 94 * PHY access functions 95 */ 96 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) 97 { 98 u32 val; 99 u32 max_iterations = 10; 100 u32 wait_counter = 0; 101 102 do { 103 val = readl(dbi_base + PCIE_PHY_STAT); 104 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; 105 wait_counter++; 106 107 if (val == exp_val) 108 return 0; 109 110 udelay(1); 111 } while (wait_counter < max_iterations); 112 113 return -ETIMEDOUT; 114 } 115 116 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) 117 { 118 u32 val; 119 int ret; 120 121 val = addr << PCIE_PHY_CTRL_DATA_LOC; 122 writel(val, dbi_base + PCIE_PHY_CTRL); 123 124 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); 125 writel(val, dbi_base + PCIE_PHY_CTRL); 126 127 ret = pcie_phy_poll_ack(dbi_base, 1); 128 if (ret) 129 return ret; 130 131 val = addr << PCIE_PHY_CTRL_DATA_LOC; 132 writel(val, dbi_base + PCIE_PHY_CTRL); 133 134 ret = pcie_phy_poll_ack(dbi_base, 0); 135 if (ret) 136 return ret; 137 138 return 0; 139 } 140 141 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 142 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) 143 { 144 u32 val, phy_ctl; 145 int ret; 146 147 ret = pcie_phy_wait_ack(dbi_base, addr); 148 if (ret) 149 return ret; 150 151 /* assert Read signal */ 152 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; 153 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); 154 155 ret = pcie_phy_poll_ack(dbi_base, 1); 156 if (ret) 157 return ret; 158 159 val = readl(dbi_base + PCIE_PHY_STAT); 160 *data = val & 0xffff; 161 162 /* deassert Read signal */ 163 writel(0x00, dbi_base + PCIE_PHY_CTRL); 164 165 ret = pcie_phy_poll_ack(dbi_base, 0); 166 if (ret) 167 return ret; 168 169 return 0; 170 } 171 172 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) 173 { 174 u32 var; 175 int ret; 176 177 /* write addr */ 178 /* cap addr */ 179 ret = pcie_phy_wait_ack(dbi_base, addr); 180 if (ret) 181 return ret; 182 183 var = data << PCIE_PHY_CTRL_DATA_LOC; 184 writel(var, dbi_base + PCIE_PHY_CTRL); 185 186 /* capture data */ 187 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); 188 writel(var, dbi_base + PCIE_PHY_CTRL); 189 190 ret = pcie_phy_poll_ack(dbi_base, 1); 191 if (ret) 192 return ret; 193 194 /* deassert cap data */ 195 var = data << PCIE_PHY_CTRL_DATA_LOC; 196 writel(var, dbi_base + PCIE_PHY_CTRL); 197 198 /* wait for ack de-assertion */ 199 ret = pcie_phy_poll_ack(dbi_base, 0); 200 if (ret) 201 return ret; 202 203 /* assert wr signal */ 204 var = 0x1 << PCIE_PHY_CTRL_WR_LOC; 205 writel(var, dbi_base + PCIE_PHY_CTRL); 206 207 /* wait for ack */ 208 ret = pcie_phy_poll_ack(dbi_base, 1); 209 if (ret) 210 return ret; 211 212 /* deassert wr signal */ 213 var = data << PCIE_PHY_CTRL_DATA_LOC; 214 writel(var, dbi_base + PCIE_PHY_CTRL); 215 216 /* wait for ack de-assertion */ 217 ret = pcie_phy_poll_ack(dbi_base, 0); 218 if (ret) 219 return ret; 220 221 writel(0x0, dbi_base + PCIE_PHY_CTRL); 222 223 return 0; 224 } 225 226 static int imx6_pcie_link_up(void) 227 { 228 u32 rc, ltssm; 229 int rx_valid, temp; 230 231 /* link is debug bit 36, debug register 1 starts at bit 32 */ 232 rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1); 233 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) && 234 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)) 235 return -EAGAIN; 236 237 /* 238 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. 239 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). 240 * If (MAC/LTSSM.state == Recovery.RcvrLock) 241 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition 242 * to gen2 is stuck 243 */ 244 pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid); 245 ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F; 246 247 if (rx_valid & 0x01) 248 return 0; 249 250 if (ltssm != 0x0d) 251 return 0; 252 253 printf("transition to gen2 is stuck, reset PHY!\n"); 254 255 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); 256 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); 257 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); 258 259 udelay(3000); 260 261 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); 262 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); 263 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); 264 265 return 0; 266 } 267 268 /* 269 * iATU region setup 270 */ 271 static int imx_pcie_regions_setup(void) 272 { 273 /* 274 * i.MX6 defines 16MB in the AXI address map for PCIe. 275 * 276 * That address space excepted the pcie registers is 277 * split and defined into different regions by iATU, 278 * with sizes and offsets as follows: 279 * 280 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO 281 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM 282 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers 283 */ 284 285 /* CMD reg:I/O space, MEM space, and Bus Master Enable */ 286 setbits_le32(MX6_DBI_ADDR | PCI_COMMAND, 287 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 288 289 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ 290 setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION, 291 PCI_CLASS_BRIDGE_PCI << 16); 292 293 /* Region #0 is used for Outbound CFG space access. */ 294 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); 295 296 writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE); 297 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE); 298 writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT); 299 300 writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); 301 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET); 302 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); 303 writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2); 304 305 return 0; 306 } 307 308 /* 309 * PCI Express accessors 310 */ 311 static uint32_t get_bus_address(pci_dev_t d, int where) 312 { 313 uint32_t va_address; 314 315 /* Reconfigure Region #0 */ 316 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); 317 318 if (PCI_BUS(d) < 2) 319 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); 320 else 321 writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1); 322 323 if (PCI_BUS(d) == 0) { 324 va_address = MX6_DBI_ADDR; 325 } else { 326 writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); 327 va_address = MX6_IO_ADDR + SZ_16M - SZ_1M; 328 } 329 330 va_address += (where & ~0x3); 331 332 return va_address; 333 } 334 335 static int imx_pcie_addr_valid(pci_dev_t d) 336 { 337 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1)) 338 return -EINVAL; 339 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0)) 340 return -EINVAL; 341 return 0; 342 } 343 344 /* 345 * Replace the original ARM DABT handler with a simple jump-back one. 346 * 347 * The problem here is that if we have a PCIe bridge attached to this PCIe 348 * controller, but no PCIe device is connected to the bridges' downstream 349 * port, the attempt to read/write from/to the config space will produce 350 * a DABT. This is a behavior of the controller and can not be disabled 351 * unfortuatelly. 352 * 353 * To work around the problem, we backup the current DABT handler address 354 * and replace it with our own DABT handler, which only bounces right back 355 * into the code. 356 */ 357 static void imx_pcie_fix_dabt_handler(bool set) 358 { 359 extern uint32_t *_data_abort; 360 uint32_t *data_abort_addr = (uint32_t *)&_data_abort; 361 362 static const uint32_t data_abort_bounce_handler = 0xe25ef004; 363 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler; 364 365 static uint32_t data_abort_backup; 366 367 if (set) { 368 data_abort_backup = *data_abort_addr; 369 *data_abort_addr = data_abort_bounce_addr; 370 } else { 371 *data_abort_addr = data_abort_backup; 372 } 373 } 374 375 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, 376 int where, u32 *val) 377 { 378 uint32_t va_address; 379 int ret; 380 381 ret = imx_pcie_addr_valid(d); 382 if (ret) { 383 *val = 0xffffffff; 384 return 0; 385 } 386 387 va_address = get_bus_address(d, where); 388 389 /* 390 * Read the PCIe config space. We must replace the DABT handler 391 * here in case we got data abort from the PCIe controller, see 392 * imx_pcie_fix_dabt_handler() description. Note that writing the 393 * "val" with valid value is also imperative here as in case we 394 * did got DABT, the val would contain random value. 395 */ 396 imx_pcie_fix_dabt_handler(true); 397 writel(0xffffffff, val); 398 *val = readl(va_address); 399 imx_pcie_fix_dabt_handler(false); 400 401 return 0; 402 } 403 404 static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, 405 int where, u32 val) 406 { 407 uint32_t va_address = 0; 408 int ret; 409 410 ret = imx_pcie_addr_valid(d); 411 if (ret) 412 return ret; 413 414 va_address = get_bus_address(d, where); 415 416 /* 417 * Write the PCIe config space. We must replace the DABT handler 418 * here in case we got data abort from the PCIe controller, see 419 * imx_pcie_fix_dabt_handler() description. 420 */ 421 imx_pcie_fix_dabt_handler(true); 422 writel(val, va_address); 423 imx_pcie_fix_dabt_handler(false); 424 425 return 0; 426 } 427 428 /* 429 * Initial bus setup 430 */ 431 static int imx6_pcie_assert_core_reset(void) 432 { 433 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 434 435 if (is_mx6dqp()) 436 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); 437 438 #if defined(CONFIG_MX6SX) 439 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; 440 441 /* SSP_EN is not used on MX6SX anymore */ 442 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); 443 /* Force PCIe PHY reset */ 444 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); 445 /* Power up PCIe PHY */ 446 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); 447 #else 448 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); 449 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); 450 #endif 451 452 return 0; 453 } 454 455 static int imx6_pcie_init_phy(void) 456 { 457 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 458 459 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); 460 461 clrsetbits_le32(&iomuxc_regs->gpr[12], 462 IOMUXC_GPR12_DEVICE_TYPE_MASK, 463 IOMUXC_GPR12_DEVICE_TYPE_RC); 464 clrsetbits_le32(&iomuxc_regs->gpr[12], 465 IOMUXC_GPR12_LOS_LEVEL_MASK, 466 IOMUXC_GPR12_LOS_LEVEL_9); 467 468 #ifdef CONFIG_MX6SX 469 clrsetbits_le32(&iomuxc_regs->gpr[12], 470 IOMUXC_GPR12_RX_EQ_MASK, 471 IOMUXC_GPR12_RX_EQ_2); 472 #endif 473 474 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | 475 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | 476 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | 477 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) | 478 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET), 479 &iomuxc_regs->gpr[8]); 480 481 return 0; 482 } 483 484 __weak int imx6_pcie_toggle_power(void) 485 { 486 #ifdef CONFIG_PCIE_IMX_POWER_GPIO 487 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); 488 mdelay(20); 489 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); 490 mdelay(20); 491 #endif 492 return 0; 493 } 494 495 __weak int imx6_pcie_toggle_reset(void) 496 { 497 /* 498 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1' 499 * for detailed understanding of the PCIe CR reset logic. 500 * 501 * The PCIe #PERST reset line _MUST_ be connected, otherwise your 502 * design does not conform to the specification. You must wait at 503 * least 20 ms after de-asserting the #PERST so the EP device can 504 * do self-initialisation. 505 * 506 * In case your #PERST pin is connected to a plain GPIO pin of the 507 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's 508 * configuration file and the condition below will handle the rest 509 * of the reset toggling. 510 * 511 * In case your #PERST toggling logic is more complex, for example 512 * connected via CPLD or somesuch, you can override this function 513 * in your board file and implement reset logic as needed. You must 514 * not forget to wait at least 20 ms after de-asserting #PERST in 515 * this case either though. 516 * 517 * In case your #PERST line of the PCIe EP device is not connected 518 * at all, your design is broken and you should fix your design, 519 * otherwise you will observe problems like for example the link 520 * not coming up after rebooting the system back from running Linux 521 * that uses the PCIe as well OR the PCIe link might not come up in 522 * Linux at all in the first place since it's in some non-reset 523 * state due to being previously used in U-Boot. 524 */ 525 #ifdef CONFIG_PCIE_IMX_PERST_GPIO 526 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); 527 mdelay(20); 528 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); 529 mdelay(20); 530 #else 531 puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); 532 #endif 533 return 0; 534 } 535 536 static int imx6_pcie_deassert_core_reset(void) 537 { 538 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 539 540 imx6_pcie_toggle_power(); 541 542 enable_pcie_clock(); 543 544 if (is_mx6dqp()) 545 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); 546 547 /* 548 * Wait for the clock to settle a bit, when the clock are sourced 549 * from the CPU, we need about 30 ms to settle. 550 */ 551 mdelay(50); 552 553 #if defined(CONFIG_MX6SX) 554 /* SSP_EN is not used on MX6SX anymore */ 555 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); 556 /* Clear PCIe PHY reset bit */ 557 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); 558 #else 559 /* Enable PCIe */ 560 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); 561 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); 562 #endif 563 564 imx6_pcie_toggle_reset(); 565 566 return 0; 567 } 568 569 static int imx_pcie_link_up(void) 570 { 571 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 572 uint32_t tmp; 573 int count = 0; 574 575 imx6_pcie_assert_core_reset(); 576 imx6_pcie_init_phy(); 577 imx6_pcie_deassert_core_reset(); 578 579 imx_pcie_regions_setup(); 580 581 /* 582 * FIXME: Force the PCIe RC to Gen1 operation 583 * The RC must be forced into Gen1 mode before bringing the link 584 * up, otherwise no downstream devices are detected. After the 585 * link is up, a managed Gen1->Gen2 transition can be initiated. 586 */ 587 tmp = readl(MX6_DBI_ADDR + 0x7c); 588 tmp &= ~0xf; 589 tmp |= 0x1; 590 writel(tmp, MX6_DBI_ADDR + 0x7c); 591 592 /* LTSSM enable, starting link. */ 593 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); 594 595 while (!imx6_pcie_link_up()) { 596 udelay(10); 597 count++; 598 if (count >= 4000) { 599 #ifdef CONFIG_PCI_SCAN_SHOW 600 puts("PCI: pcie phy link never came up\n"); 601 #endif 602 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 603 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), 604 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); 605 return -EINVAL; 606 } 607 } 608 609 return 0; 610 } 611 612 void imx_pcie_init(void) 613 { 614 /* Static instance of the controller. */ 615 static struct pci_controller pcc; 616 struct pci_controller *hose = &pcc; 617 int ret; 618 619 memset(&pcc, 0, sizeof(pcc)); 620 621 /* PCI I/O space */ 622 pci_set_region(&hose->regions[0], 623 MX6_IO_ADDR, MX6_IO_ADDR, 624 MX6_IO_SIZE, PCI_REGION_IO); 625 626 /* PCI memory space */ 627 pci_set_region(&hose->regions[1], 628 MX6_MEM_ADDR, MX6_MEM_ADDR, 629 MX6_MEM_SIZE, PCI_REGION_MEM); 630 631 /* System memory space */ 632 pci_set_region(&hose->regions[2], 633 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR, 634 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 635 636 hose->region_count = 3; 637 638 pci_set_ops(hose, 639 pci_hose_read_config_byte_via_dword, 640 pci_hose_read_config_word_via_dword, 641 imx_pcie_read_config, 642 pci_hose_write_config_byte_via_dword, 643 pci_hose_write_config_word_via_dword, 644 imx_pcie_write_config); 645 646 /* Start the controller. */ 647 ret = imx_pcie_link_up(); 648 649 if (!ret) { 650 pci_register_hose(hose); 651 hose->last_busno = pci_hose_scan(hose); 652 } 653 } 654 655 /* Probe function. */ 656 void pci_init_board(void) 657 { 658 imx_pcie_init(); 659 } 660