1 /* 2 * Copyright (C) 2015 Marvell International Ltd. 3 * 4 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 5 * 6 * Based on: 7 * - drivers/pci/pcie_imx.c 8 * - drivers/pci/pci_mvebu.c 9 * - drivers/pci/pcie_xilinx.c 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <pci.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* PCI Config space registers */ 23 #define PCIE_CONFIG_BAR0 0x10 24 #define PCIE_LINK_STATUS_REG 0x80 25 #define PCIE_LINK_STATUS_SPEED_OFF 16 26 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 27 #define PCIE_LINK_STATUS_WIDTH_OFF 20 28 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 29 30 /* Resizable bar capability registers */ 31 #define RESIZABLE_BAR_CAP 0x250 32 #define RESIZABLE_BAR_CTL0 0x254 33 #define RESIZABLE_BAR_CTL1 0x258 34 35 /* iATU registers */ 36 #define PCIE_ATU_VIEWPORT 0x900 37 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) 38 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 39 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 40 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 41 #define PCIE_ATU_CR1 0x904 42 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 43 #define PCIE_ATU_TYPE_IO (0x2 << 0) 44 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 45 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 46 #define PCIE_ATU_CR2 0x908 47 #define PCIE_ATU_ENABLE (0x1 << 31) 48 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 49 #define PCIE_ATU_LOWER_BASE 0x90C 50 #define PCIE_ATU_UPPER_BASE 0x910 51 #define PCIE_ATU_LIMIT 0x914 52 #define PCIE_ATU_LOWER_TARGET 0x918 53 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 54 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 55 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 56 #define PCIE_ATU_UPPER_TARGET 0x91C 57 58 #define PCIE_LINK_CAPABILITY 0x7C 59 #define PCIE_LINK_CTL_2 0xA0 60 #define TARGET_LINK_SPEED_MASK 0xF 61 #define LINK_SPEED_GEN_1 0x1 62 #define LINK_SPEED_GEN_2 0x2 63 #define LINK_SPEED_GEN_3 0x3 64 65 #define PCIE_GEN3_RELATED 0x890 66 #define GEN3_EQU_DISABLE (1 << 16) 67 #define GEN3_ZRXDC_NON_COMP (1 << 0) 68 69 #define PCIE_GEN3_EQU_CTRL 0x8A8 70 #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5) 71 72 #define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4) 73 74 #define PCIE_LINK_UP_TIMEOUT_MS 100 75 76 #define PCIE_GLOBAL_CONTROL 0x8000 77 #define PCIE_APP_LTSSM_EN (1 << 2) 78 #define PCIE_DEVICE_TYPE_OFFSET (4) 79 #define PCIE_DEVICE_TYPE_MASK (0xF) 80 #define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */ 81 #define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */ 82 #define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */ 83 84 #define PCIE_GLOBAL_STATUS 0x8008 85 #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1) 86 #define PCIE_GLB_STS_PHY_LINK_UP (1 << 9) 87 88 #define PCIE_ARCACHE_TRC 0x8050 89 #define PCIE_AWCACHE_TRC 0x8054 90 #define ARCACHE_SHAREABLE_CACHEABLE 0x3511 91 #define AWCACHE_SHAREABLE_CACHEABLE 0x5311 92 93 #define LINK_SPEED_GEN_1 0x1 94 #define LINK_SPEED_GEN_2 0x2 95 #define LINK_SPEED_GEN_3 0x3 96 97 /** 98 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state 99 * 100 * @ctrl_base: The base address of the register space 101 * @cfg_base: The base address of the configuration space 102 * @cfg_size: The size of the configuration space which is needed 103 * as it gets written into the PCIE_ATU_LIMIT register 104 * @first_busno: This driver supports multiple PCIe controllers. 105 * first_busno stores the bus number of the PCIe root-port 106 * number which may vary depending on the PCIe setup 107 * (PEX switches etc). 108 */ 109 struct pcie_dw_mvebu { 110 void *ctrl_base; 111 void *cfg_base; 112 fdt_size_t cfg_size; 113 int first_busno; 114 }; 115 116 static int pcie_dw_get_link_speed(const void *regs_base) 117 { 118 return (readl(regs_base + PCIE_LINK_STATUS_REG) & 119 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 120 } 121 122 static int pcie_dw_get_link_width(const void *regs_base) 123 { 124 return (readl(regs_base + PCIE_LINK_STATUS_REG) & 125 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 126 } 127 128 /** 129 * set_cfg_address() - Configure the PCIe controller config space access 130 * 131 * @pcie: Pointer to the PCI controller state 132 * @d: PCI device to access 133 * @where: Offset in the configuration space 134 * 135 * Configures the PCIe controller to access the configuration space of 136 * a specific PCIe device and returns the address to use for this 137 * access. 138 * 139 * Return: Address that can be used to access the configation space 140 * of the requested device / offset 141 */ 142 static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, 143 pci_dev_t d, uint where) 144 { 145 uintptr_t va_address; 146 147 /* 148 * Region #0 is used for Outbound CFG space access. 149 * Direction = Outbound 150 * Region Index = 0 151 */ 152 writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT); 153 154 if (PCI_BUS(d) == (pcie->first_busno + 1)) 155 /* For local bus, change TLP Type field to 4. */ 156 writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1); 157 else 158 /* Otherwise, change TLP Type field to 5. */ 159 writel(PCIE_ATU_TYPE_CFG1, pcie->ctrl_base + PCIE_ATU_CR1); 160 161 if (PCI_BUS(d) == pcie->first_busno) { 162 /* Accessing root port configuration space. */ 163 va_address = (uintptr_t)pcie->ctrl_base; 164 } else { 165 d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno); 166 writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); 167 va_address = (uintptr_t)pcie->cfg_base; 168 } 169 170 va_address += where & ~0x3; 171 172 return va_address; 173 } 174 175 /** 176 * pcie_dw_addr_valid() - Check for valid bus address 177 * 178 * @d: The PCI device to access 179 * @first_busno: Bus number of the PCIe controller root complex 180 * 181 * Return 1 (true) if the PCI device can be accessed by this controller. 182 * 183 * Return: 1 on valid, 0 on invalid 184 */ 185 static int pcie_dw_addr_valid(pci_dev_t d, int first_busno) 186 { 187 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 188 return 0; 189 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 190 return 0; 191 192 return 1; 193 } 194 195 /** 196 * pcie_dw_mvebu_read_config() - Read from configuration space 197 * 198 * @bus: Pointer to the PCI bus 199 * @bdf: Identifies the PCIe device to access 200 * @offset: The offset into the device's configuration space 201 * @valuep: A pointer at which to store the read value 202 * @size: Indicates the size of access to perform 203 * 204 * Read a value of size @size from offset @offset within the configuration 205 * space of the device identified by the bus, device & function numbers in @bdf 206 * on the PCI bus @bus. 207 * 208 * Return: 0 on success 209 */ 210 static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf, 211 uint offset, ulong *valuep, 212 enum pci_size_t size) 213 { 214 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); 215 uintptr_t va_address; 216 ulong value; 217 218 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", 219 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 220 221 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { 222 debug("- out of range\n"); 223 *valuep = pci_get_ff(size); 224 return 0; 225 } 226 227 va_address = set_cfg_address(pcie, bdf, offset); 228 229 value = readl(va_address); 230 231 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 232 *valuep = pci_conv_32_to_size(value, offset, size); 233 234 return 0; 235 } 236 237 /** 238 * pcie_dw_mvebu_write_config() - Write to configuration space 239 * 240 * @bus: Pointer to the PCI bus 241 * @bdf: Identifies the PCIe device to access 242 * @offset: The offset into the device's configuration space 243 * @value: The value to write 244 * @size: Indicates the size of access to perform 245 * 246 * Write the value @value of size @size from offset @offset within the 247 * configuration space of the device identified by the bus, device & function 248 * numbers in @bdf on the PCI bus @bus. 249 * 250 * Return: 0 on success 251 */ 252 static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf, 253 uint offset, ulong value, 254 enum pci_size_t size) 255 { 256 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); 257 uintptr_t va_address; 258 ulong old; 259 260 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", 261 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 262 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 263 264 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { 265 debug("- out of range\n"); 266 return 0; 267 } 268 269 va_address = set_cfg_address(pcie, bdf, offset); 270 271 old = readl(va_address); 272 value = pci_conv_size_to_32(old, value, offset, size); 273 writel(value, va_address); 274 275 return 0; 276 } 277 278 /** 279 * pcie_dw_configure() - Configure link capabilities and speed 280 * 281 * @regs_base: A pointer to the PCIe controller registers 282 * @cap_speed: The capabilities and speed to configure 283 * 284 * Configure the link capabilities and speed in the PCIe root complex. 285 */ 286 static void pcie_dw_configure(const void *regs_base, u32 cap_speed) 287 { 288 /* 289 * TODO (shadi@marvell.com, sr@denx.de): 290 * Need to read the serdes speed from the dts and according to it 291 * configure the PCIe gen 292 */ 293 294 /* Set link to GEN 3 */ 295 clrsetbits_le32(regs_base + PCIE_LINK_CTL_2, 296 TARGET_LINK_SPEED_MASK, cap_speed); 297 clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY, 298 TARGET_LINK_SPEED_MASK, cap_speed); 299 setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE); 300 } 301 302 /** 303 * is_link_up() - Return the link state 304 * 305 * @regs_base: A pointer to the PCIe controller registers 306 * 307 * Return: 1 (true) for active line and 0 (false) for no link 308 */ 309 static int is_link_up(const void *regs_base) 310 { 311 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; 312 u32 reg; 313 314 reg = readl(regs_base + PCIE_GLOBAL_STATUS); 315 if ((reg & mask) == mask) 316 return 1; 317 318 return 0; 319 } 320 321 /** 322 * wait_link_up() - Wait for the link to come up 323 * 324 * @regs_base: A pointer to the PCIe controller registers 325 * 326 * Return: 1 (true) for active line and 0 (false) for no link (timeout) 327 */ 328 static int wait_link_up(const void *regs_base) 329 { 330 unsigned long timeout; 331 332 timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS; 333 while (!is_link_up(regs_base)) { 334 if (get_timer(0) > timeout) 335 return 0; 336 }; 337 338 return 1; 339 } 340 341 /** 342 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port 343 * 344 * @regs_base: A pointer to the PCIe controller registers 345 * @cap_speed: The capabilities and speed to configure 346 * 347 * Configure the PCIe controller root complex depending on the 348 * requested link capabilities and speed. 349 * 350 * Return: 1 (true) for active line and 0 (false) for no link 351 */ 352 static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed) 353 { 354 if (!is_link_up(regs_base)) { 355 /* Disable LTSSM state machine to enable configuration */ 356 clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 357 PCIE_APP_LTSSM_EN); 358 } 359 360 clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 361 PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET, 362 PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET); 363 364 /* Set the PCIe master AXI attributes */ 365 writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC); 366 writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC); 367 368 /* DW pre link configurations */ 369 pcie_dw_configure(regs_base, cap_speed); 370 371 if (!is_link_up(regs_base)) { 372 /* Configuration done. Start LTSSM */ 373 setbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 374 PCIE_APP_LTSSM_EN); 375 } 376 377 /* Check that link was established */ 378 if (!wait_link_up(regs_base)) 379 return 0; 380 381 /* 382 * Link can be established in Gen 1. still need to wait 383 * till MAC nagaotiation is completed 384 */ 385 udelay(100); 386 387 return 1; 388 } 389 390 /** 391 * pcie_dw_regions_setup() - iATU region setup 392 * 393 * @pcie: Pointer to the PCI controller state 394 * 395 * Configure the iATU regions in the PCIe controller for outbound access. 396 */ 397 static void pcie_dw_regions_setup(struct pcie_dw_mvebu *pcie) 398 { 399 /* 400 * Region #0 is used for Outbound CFG space access. 401 * Direction = Outbound 402 * Region Index = 0 403 */ 404 writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT); 405 406 writel((u32)(uintptr_t)pcie->cfg_base, pcie->ctrl_base 407 + PCIE_ATU_LOWER_BASE); 408 writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_BASE); 409 writel((u32)(uintptr_t)pcie->cfg_base + pcie->cfg_size, 410 pcie->ctrl_base + PCIE_ATU_LIMIT); 411 412 writel(0, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); 413 writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_TARGET); 414 writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1); 415 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2); 416 } 417 418 /** 419 * pcie_dw_set_host_bars() - Configure the host BARs 420 * 421 * @regs_base: A pointer to the PCIe controller registers 422 * 423 * Configure the host BARs of the PCIe controller root port so that 424 * PCI(e) devices may access the system memory. 425 */ 426 static void pcie_dw_set_host_bars(const void *regs_base) 427 { 428 u32 size = gd->ram_size; 429 u64 max_size; 430 u32 reg; 431 u32 bar0; 432 433 /* Verify the maximal BAR size */ 434 reg = readl(regs_base + RESIZABLE_BAR_CAP); 435 max_size = 1ULL << (5 + (reg + (1 << 4))); 436 437 if (size > max_size) { 438 size = max_size; 439 printf("Warning: PCIe BARs can't map all DRAM space\n"); 440 } 441 442 /* Set the BAR base and size towards DDR */ 443 bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf; 444 bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32; 445 writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); 446 447 reg = ((size >> 20) - 1) << 12; 448 writel(size, regs_base + RESIZABLE_BAR_CTL0); 449 } 450 451 /** 452 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link 453 * 454 * @dev: A pointer to the device being operated on 455 * 456 * Probe for an active link on the PCIe bus and configure the controller 457 * to enable this port. 458 * 459 * Return: 0 on success, else -ENODEV 460 */ 461 static int pcie_dw_mvebu_probe(struct udevice *dev) 462 { 463 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); 464 struct udevice *ctlr = pci_get_controller(dev); 465 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 466 #ifdef CONFIG_DM_GPIO 467 struct gpio_desc reset_gpio; 468 469 gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio, 470 GPIOD_IS_OUT); 471 /* 472 * Issue reset to add-in card trough the dedicated GPIO. 473 * Some boards are connecting the card reset pin to common system 474 * reset wire and others are using separate GPIO port. 475 * In the last case we have to release a reset of the addon card 476 * using this GPIO. 477 */ 478 if (dm_gpio_is_valid(&reset_gpio)) { 479 dm_gpio_set_value(&reset_gpio, 1); 480 mdelay(200); 481 } 482 #else 483 debug("PCIE Reset on GPIO support is missing\n"); 484 #endif /* CONFIG_DM_GPIO */ 485 486 pcie->first_busno = dev->seq; 487 488 /* Don't register host if link is down */ 489 if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) { 490 printf("PCIE-%d: Link down\n", dev->seq); 491 } else { 492 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq, 493 pcie_dw_get_link_speed(pcie->ctrl_base), 494 pcie_dw_get_link_width(pcie->ctrl_base), 495 hose->first_busno); 496 } 497 498 pcie_dw_regions_setup(pcie); 499 500 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ 501 clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION, 502 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16); 503 504 pcie_dw_set_host_bars(pcie->ctrl_base); 505 506 return 0; 507 } 508 509 /** 510 * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state 511 * 512 * @dev: A pointer to the device being operated on 513 * 514 * Translate relevant data from the device tree pertaining to device @dev into 515 * state that the driver will later make use of. This state is stored in the 516 * device's private data structure. 517 * 518 * Return: 0 on success, else -EINVAL 519 */ 520 static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev) 521 { 522 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); 523 524 /* Get the controller base address */ 525 pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0); 526 if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE) 527 return -EINVAL; 528 529 /* Get the config space base address and size */ 530 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, 531 &pcie->cfg_size); 532 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) 533 return -EINVAL; 534 535 return 0; 536 } 537 538 static const struct dm_pci_ops pcie_dw_mvebu_ops = { 539 .read_config = pcie_dw_mvebu_read_config, 540 .write_config = pcie_dw_mvebu_write_config, 541 }; 542 543 static const struct udevice_id pcie_dw_mvebu_ids[] = { 544 { .compatible = "marvell,armada8k-pcie" }, 545 { } 546 }; 547 548 U_BOOT_DRIVER(pcie_dw_mvebu) = { 549 .name = "pcie_dw_mvebu", 550 .id = UCLASS_PCI, 551 .of_match = pcie_dw_mvebu_ids, 552 .ops = &pcie_dw_mvebu_ops, 553 .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata, 554 .probe = pcie_dw_mvebu_probe, 555 .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu), 556 }; 557