1 /* 2 * Copyright (C) 2015 Marvell International Ltd. 3 * 4 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 5 * 6 * Based on: 7 * - drivers/pci/pcie_imx.c 8 * - drivers/pci/pci_mvebu.c 9 * - drivers/pci/pcie_xilinx.c 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <pci.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* PCI Config space registers */ 23 #define PCIE_CONFIG_BAR0 0x10 24 #define PCIE_LINK_STATUS_REG 0x80 25 #define PCIE_LINK_STATUS_SPEED_OFF 16 26 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 27 #define PCIE_LINK_STATUS_WIDTH_OFF 20 28 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 29 30 /* Resizable bar capability registers */ 31 #define RESIZABLE_BAR_CAP 0x250 32 #define RESIZABLE_BAR_CTL0 0x254 33 #define RESIZABLE_BAR_CTL1 0x258 34 35 /* iATU registers */ 36 #define PCIE_ATU_VIEWPORT 0x900 37 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) 38 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 39 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 40 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 41 #define PCIE_ATU_CR1 0x904 42 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 43 #define PCIE_ATU_TYPE_IO (0x2 << 0) 44 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 45 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 46 #define PCIE_ATU_CR2 0x908 47 #define PCIE_ATU_ENABLE (0x1 << 31) 48 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 49 #define PCIE_ATU_LOWER_BASE 0x90C 50 #define PCIE_ATU_UPPER_BASE 0x910 51 #define PCIE_ATU_LIMIT 0x914 52 #define PCIE_ATU_LOWER_TARGET 0x918 53 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 54 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 55 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 56 #define PCIE_ATU_UPPER_TARGET 0x91C 57 58 #define PCIE_LINK_CAPABILITY 0x7C 59 #define PCIE_LINK_CTL_2 0xA0 60 #define TARGET_LINK_SPEED_MASK 0xF 61 #define LINK_SPEED_GEN_1 0x1 62 #define LINK_SPEED_GEN_2 0x2 63 #define LINK_SPEED_GEN_3 0x3 64 65 #define PCIE_GEN3_RELATED 0x890 66 #define GEN3_EQU_DISABLE (1 << 16) 67 #define GEN3_ZRXDC_NON_COMP (1 << 0) 68 69 #define PCIE_GEN3_EQU_CTRL 0x8A8 70 #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5) 71 72 #define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4) 73 74 #define PCIE_LINK_UP_TIMEOUT_MS 100 75 76 #define PCIE_GLOBAL_CONTROL 0x8000 77 #define PCIE_APP_LTSSM_EN (1 << 2) 78 #define PCIE_DEVICE_TYPE_OFFSET (4) 79 #define PCIE_DEVICE_TYPE_MASK (0xF) 80 #define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */ 81 #define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */ 82 #define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */ 83 84 #define PCIE_GLOBAL_STATUS 0x8008 85 #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1) 86 #define PCIE_GLB_STS_PHY_LINK_UP (1 << 9) 87 88 #define PCIE_ARCACHE_TRC 0x8050 89 #define PCIE_AWCACHE_TRC 0x8054 90 #define ARCACHE_SHAREABLE_CACHEABLE 0x3511 91 #define AWCACHE_SHAREABLE_CACHEABLE 0x5311 92 93 #define LINK_SPEED_GEN_1 0x1 94 #define LINK_SPEED_GEN_2 0x2 95 #define LINK_SPEED_GEN_3 0x3 96 97 /** 98 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state 99 * 100 * @ctrl_base: The base address of the register space 101 * @cfg_base: The base address of the configuration space 102 * @cfg_size: The size of the configuration space which is needed 103 * as it gets written into the PCIE_ATU_LIMIT register 104 * @first_busno: This driver supports multiple PCIe controllers. 105 * first_busno stores the bus number of the PCIe root-port 106 * number which may vary depending on the PCIe setup 107 * (PEX switches etc). 108 */ 109 struct pcie_dw_mvebu { 110 void *ctrl_base; 111 void *cfg_base; 112 fdt_size_t cfg_size; 113 int first_busno; 114 }; 115 116 static int pcie_dw_get_link_speed(const void *regs_base) 117 { 118 return (readl(regs_base + PCIE_LINK_STATUS_REG) & 119 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 120 } 121 122 static int pcie_dw_get_link_width(const void *regs_base) 123 { 124 return (readl(regs_base + PCIE_LINK_STATUS_REG) & 125 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 126 } 127 128 /** 129 * set_cfg_address() - Configure the PCIe controller config space access 130 * 131 * @pcie: Pointer to the PCI controller state 132 * @d: PCI device to access 133 * @where: Offset in the configuration space 134 * 135 * Configures the PCIe controller to access the configuration space of 136 * a specific PCIe device and returns the address to use for this 137 * access. 138 * 139 * Return: Address that can be used to access the configation space 140 * of the requested device / offset 141 */ 142 static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, 143 pci_dev_t d, uint where) 144 { 145 uintptr_t va_address; 146 147 /* 148 * Region #0 is used for Outbound CFG space access. 149 * Direction = Outbound 150 * Region Index = 0 151 */ 152 writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT); 153 154 if (PCI_BUS(d) == (pcie->first_busno + 1)) 155 /* For local bus, change TLP Type field to 4. */ 156 writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1); 157 else 158 /* Otherwise, change TLP Type field to 5. */ 159 writel(PCIE_ATU_TYPE_CFG1, pcie->ctrl_base + PCIE_ATU_CR1); 160 161 if (PCI_BUS(d) == pcie->first_busno) { 162 /* Accessing root port configuration space. */ 163 va_address = (uintptr_t)pcie->ctrl_base; 164 } else { 165 writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); 166 va_address = (uintptr_t)pcie->cfg_base; 167 } 168 169 va_address += where & ~0x3; 170 171 return va_address; 172 } 173 174 /** 175 * pcie_dw_addr_valid() - Check for valid bus address 176 * 177 * @d: The PCI device to access 178 * @first_busno: Bus number of the PCIe controller root complex 179 * 180 * Return 1 (true) if the PCI device can be accessed by this controller. 181 * 182 * Return: 1 on valid, 0 on invalid 183 */ 184 static int pcie_dw_addr_valid(pci_dev_t d, int first_busno) 185 { 186 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 187 return 0; 188 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 189 return 0; 190 191 return 1; 192 } 193 194 /** 195 * pcie_dw_mvebu_read_config() - Read from configuration space 196 * 197 * @bus: Pointer to the PCI bus 198 * @bdf: Identifies the PCIe device to access 199 * @offset: The offset into the device's configuration space 200 * @valuep: A pointer at which to store the read value 201 * @size: Indicates the size of access to perform 202 * 203 * Read a value of size @size from offset @offset within the configuration 204 * space of the device identified by the bus, device & function numbers in @bdf 205 * on the PCI bus @bus. 206 * 207 * Return: 0 on success 208 */ 209 static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf, 210 uint offset, ulong *valuep, 211 enum pci_size_t size) 212 { 213 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); 214 uintptr_t va_address; 215 ulong value; 216 217 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", 218 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 219 220 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { 221 debug("- out of range\n"); 222 *valuep = pci_get_ff(size); 223 return 0; 224 } 225 226 va_address = set_cfg_address(pcie, bdf, offset); 227 228 value = readl(va_address); 229 230 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 231 *valuep = pci_conv_32_to_size(value, offset, size); 232 233 return 0; 234 } 235 236 /** 237 * pcie_dw_mvebu_write_config() - Write to configuration space 238 * 239 * @bus: Pointer to the PCI bus 240 * @bdf: Identifies the PCIe device to access 241 * @offset: The offset into the device's configuration space 242 * @value: The value to write 243 * @size: Indicates the size of access to perform 244 * 245 * Write the value @value of size @size from offset @offset within the 246 * configuration space of the device identified by the bus, device & function 247 * numbers in @bdf on the PCI bus @bus. 248 * 249 * Return: 0 on success 250 */ 251 static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf, 252 uint offset, ulong value, 253 enum pci_size_t size) 254 { 255 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); 256 uintptr_t va_address; 257 ulong old; 258 259 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", 260 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 261 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 262 263 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { 264 debug("- out of range\n"); 265 return 0; 266 } 267 268 va_address = set_cfg_address(pcie, bdf, offset); 269 270 old = readl(va_address); 271 value = pci_conv_size_to_32(old, value, offset, size); 272 writel(value, va_address); 273 274 return 0; 275 } 276 277 /** 278 * pcie_dw_configure() - Configure link capabilities and speed 279 * 280 * @regs_base: A pointer to the PCIe controller registers 281 * @cap_speed: The capabilities and speed to configure 282 * 283 * Configure the link capabilities and speed in the PCIe root complex. 284 */ 285 static void pcie_dw_configure(const void *regs_base, u32 cap_speed) 286 { 287 /* 288 * TODO (shadi@marvell.com, sr@denx.de): 289 * Need to read the serdes speed from the dts and according to it 290 * configure the PCIe gen 291 */ 292 293 /* Set link to GEN 3 */ 294 clrsetbits_le32(regs_base + PCIE_LINK_CTL_2, 295 TARGET_LINK_SPEED_MASK, cap_speed); 296 clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY, 297 TARGET_LINK_SPEED_MASK, cap_speed); 298 setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE); 299 } 300 301 /** 302 * is_link_up() - Return the link state 303 * 304 * @regs_base: A pointer to the PCIe controller registers 305 * 306 * Return: 1 (true) for active line and 0 (false) for no link 307 */ 308 static int is_link_up(const void *regs_base) 309 { 310 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; 311 u32 reg; 312 313 reg = readl(regs_base + PCIE_GLOBAL_STATUS); 314 if ((reg & mask) == mask) 315 return 1; 316 317 return 0; 318 } 319 320 /** 321 * wait_link_up() - Wait for the link to come up 322 * 323 * @regs_base: A pointer to the PCIe controller registers 324 * 325 * Return: 1 (true) for active line and 0 (false) for no link (timeout) 326 */ 327 static int wait_link_up(const void *regs_base) 328 { 329 unsigned long timeout; 330 331 timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS; 332 while (!is_link_up(regs_base)) { 333 if (get_timer(0) > timeout) 334 return 0; 335 }; 336 337 return 1; 338 } 339 340 /** 341 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port 342 * 343 * @regs_base: A pointer to the PCIe controller registers 344 * @cap_speed: The capabilities and speed to configure 345 * 346 * Configure the PCIe controller root complex depending on the 347 * requested link capabilities and speed. 348 * 349 * Return: 1 (true) for active line and 0 (false) for no link 350 */ 351 static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed) 352 { 353 if (!is_link_up(regs_base)) { 354 /* Disable LTSSM state machine to enable configuration */ 355 clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 356 PCIE_APP_LTSSM_EN); 357 } 358 359 clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 360 PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET, 361 PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET); 362 363 /* Set the PCIe master AXI attributes */ 364 writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC); 365 writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC); 366 367 /* DW pre link configurations */ 368 pcie_dw_configure(regs_base, cap_speed); 369 370 if (!is_link_up(regs_base)) { 371 /* Configuration done. Start LTSSM */ 372 setbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 373 PCIE_APP_LTSSM_EN); 374 } 375 376 /* Check that link was established */ 377 if (!wait_link_up(regs_base)) 378 return 0; 379 380 /* 381 * Link can be established in Gen 1. still need to wait 382 * till MAC nagaotiation is completed 383 */ 384 udelay(100); 385 386 return 1; 387 } 388 389 /** 390 * pcie_dw_regions_setup() - iATU region setup 391 * 392 * @pcie: Pointer to the PCI controller state 393 * 394 * Configure the iATU regions in the PCIe controller for outbound access. 395 */ 396 static void pcie_dw_regions_setup(struct pcie_dw_mvebu *pcie) 397 { 398 /* 399 * Region #0 is used for Outbound CFG space access. 400 * Direction = Outbound 401 * Region Index = 0 402 */ 403 writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT); 404 405 writel((u32)(uintptr_t)pcie->cfg_base, pcie->ctrl_base 406 + PCIE_ATU_LOWER_BASE); 407 writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_BASE); 408 writel((u32)(uintptr_t)pcie->cfg_base + pcie->cfg_size, 409 pcie->ctrl_base + PCIE_ATU_LIMIT); 410 411 writel(0, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); 412 writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_TARGET); 413 writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1); 414 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2); 415 } 416 417 /** 418 * pcie_dw_set_host_bars() - Configure the host BARs 419 * 420 * @regs_base: A pointer to the PCIe controller registers 421 * 422 * Configure the host BARs of the PCIe controller root port so that 423 * PCI(e) devices may access the system memory. 424 */ 425 static void pcie_dw_set_host_bars(const void *regs_base) 426 { 427 u32 size = gd->ram_size; 428 u64 max_size; 429 u32 reg; 430 u32 bar0; 431 432 /* Verify the maximal BAR size */ 433 reg = readl(regs_base + RESIZABLE_BAR_CAP); 434 max_size = 1ULL << (5 + (reg + (1 << 4))); 435 436 if (size > max_size) { 437 size = max_size; 438 printf("Warning: PCIe BARs can't map all DRAM space\n"); 439 } 440 441 /* Set the BAR base and size towards DDR */ 442 bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf; 443 bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32; 444 writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); 445 446 reg = ((size >> 20) - 1) << 12; 447 writel(size, regs_base + RESIZABLE_BAR_CTL0); 448 } 449 450 /** 451 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link 452 * 453 * @dev: A pointer to the device being operated on 454 * 455 * Probe for an active link on the PCIe bus and configure the controller 456 * to enable this port. 457 * 458 * Return: 0 on success, else -ENODEV 459 */ 460 static int pcie_dw_mvebu_probe(struct udevice *dev) 461 { 462 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); 463 struct udevice *ctlr = pci_get_controller(dev); 464 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 465 #ifdef CONFIG_DM_GPIO 466 struct gpio_desc reset_gpio; 467 468 gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio, 469 GPIOD_IS_OUT); 470 /* 471 * Issue reset to add-in card trough the dedicated GPIO. 472 * Some boards are connecting the card reset pin to common system 473 * reset wire and others are using separate GPIO port. 474 * In the last case we have to release a reset of the addon card 475 * using this GPIO. 476 */ 477 if (dm_gpio_is_valid(&reset_gpio)) { 478 dm_gpio_set_value(&reset_gpio, 1); 479 mdelay(200); 480 } 481 #else 482 debug("PCIE Reset on GPIO support is missing\n"); 483 #endif /* CONFIG_DM_GPIO */ 484 485 pcie->first_busno = dev->seq; 486 487 /* Don't register host if link is down */ 488 if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) { 489 printf("PCIE-%d: Link down\n", dev->seq); 490 } else { 491 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq, 492 pcie_dw_get_link_speed(pcie->ctrl_base), 493 pcie_dw_get_link_width(pcie->ctrl_base), 494 hose->first_busno); 495 } 496 497 pcie_dw_regions_setup(pcie); 498 499 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ 500 clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION, 501 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16); 502 503 pcie_dw_set_host_bars(pcie->ctrl_base); 504 505 return 0; 506 } 507 508 /** 509 * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state 510 * 511 * @dev: A pointer to the device being operated on 512 * 513 * Translate relevant data from the device tree pertaining to device @dev into 514 * state that the driver will later make use of. This state is stored in the 515 * device's private data structure. 516 * 517 * Return: 0 on success, else -EINVAL 518 */ 519 static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev) 520 { 521 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); 522 523 /* Get the controller base address */ 524 pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0); 525 if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE) 526 return -EINVAL; 527 528 /* Get the config space base address and size */ 529 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, 530 &pcie->cfg_size); 531 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) 532 return -EINVAL; 533 534 return 0; 535 } 536 537 static const struct dm_pci_ops pcie_dw_mvebu_ops = { 538 .read_config = pcie_dw_mvebu_read_config, 539 .write_config = pcie_dw_mvebu_write_config, 540 }; 541 542 static const struct udevice_id pcie_dw_mvebu_ids[] = { 543 { .compatible = "marvell,armada8k-pcie" }, 544 { } 545 }; 546 547 U_BOOT_DRIVER(pcie_dw_mvebu) = { 548 .name = "pcie_dw_mvebu", 549 .id = UCLASS_PCI, 550 .of_match = pcie_dw_mvebu_ids, 551 .ops = &pcie_dw_mvebu_ops, 552 .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata, 553 .probe = pcie_dw_mvebu_probe, 554 .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu), 555 }; 556