xref: /openbmc/u-boot/drivers/pci/Kconfig (revision 76b00aca)
1menuconfig PCI
2	bool "PCI support"
3	default y if PPC || X86
4	help
5	  Enable support for PCI (Peripheral Interconnect Bus), a type of bus
6	  used on some devices to allow the CPU to communicate with its
7	  peripherals.
8
9if PCI
10
11config DM_PCI
12	bool "Enable driver model for PCI"
13	depends on DM
14	help
15	  Use driver model for PCI. Driver model is the new method for
16	  orgnising devices in U-Boot. For PCI, driver model keeps track of
17	  available PCI devices, allows scanning of PCI buses and provides
18	  device configuration support.
19
20config DM_PCI_COMPAT
21	bool "Enable compatible functions for PCI"
22	depends on DM_PCI
23	help
24	  Enable compatibility functions for PCI so that old code can be used
25	  with CONFIG_DM_PCI enabled. This should be used as an interim
26	  measure when porting a board to use driver model for PCI. Once the
27	  board is fully supported, this option should be disabled.
28
29config PCI_PNP
30	bool "Enable Plug & Play support for PCI"
31	depends on PCI || DM_PCI
32	default y
33	help
34	  Enable PCI memory and I/O space resource allocation and assignment.
35
36config PCIE_DW_MVEBU
37	bool "Enable Armada-8K PCIe driver (DesignWare core)"
38	default n
39	depends on DM_PCI
40	depends on ARMADA_8K
41	help
42	  Say Y here if you want to enable PCIe controller support on
43	  Armada-8K SoCs. The PCIe controller on Armada-8K is based on
44	  DesignWare hardware.
45
46config PCI_SANDBOX
47	bool "Sandbox PCI support"
48	depends on SANDBOX && DM_PCI
49	help
50	  Support PCI on sandbox, as an emulated bus. This permits testing of
51	  PCI feature such as bus scanning, device configuration and device
52	  access. The available (emulated) devices are defined statically in
53	  the device tree but the normal PCI scan technique is used to find
54	  then.
55
56config PCI_TEGRA
57	bool "Tegra PCI support"
58	depends on TEGRA
59	depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
60	help
61	  Enable support for the PCIe controller found on some generations of
62	  Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
63	  3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
64	  with a total of 5 lanes. Some boards require this for Ethernet
65	  support to work (e.g. beaver, jetson-tk1).
66
67config PCI_XILINX
68	bool "Xilinx AXI Bridge for PCI Express"
69	depends on DM_PCI
70	help
71	  Enable support for the Xilinx AXI bridge for PCI express, an IP block
72	  which can be used on some generations of Xilinx FPGAs.
73
74config PCIE_LAYERSCAPE
75	bool "Layerscape PCIe support"
76	depends on DM_PCI
77	help
78	  Support Layerscape PCIe. The Layerscape SoC may have one or several
79	  PCIe controllers. The PCIe may works in RC or EP mode according to
80	  RCW[HOST_AGT_PEX] setting.
81
82endif
83