1menuconfig PCI 2 bool "PCI support" 3 default y if PPC || X86 4 help 5 Enable support for PCI (Peripheral Interconnect Bus), a type of bus 6 used on some devices to allow the CPU to communicate with its 7 peripherals. 8 9if PCI 10 11config DM_PCI 12 bool "Enable driver mode for PCI" 13 depends on DM 14 help 15 Use driver model for PCI. Driver model is the new method for 16 orgnising devices in U-Boot. For PCI, driver model keeps track of 17 available PCI devices, allows scanning of PCI buses and provides 18 device configuration support. 19 20config DM_PCI_COMPAT 21 bool "Enable compatible functions for PCI" 22 depends on DM_PCI 23 help 24 Enable compatibility functions for PCI so that old code can be used 25 with CONFIG_DM_PCI enabled. This should be used as an interim 26 measure when porting a board to use driver model for PCI. Once the 27 board is fully supported, this option should be disabled. 28 29config PCI_PNP 30 bool "Enable Plug & Play support for PCI" 31 depends on PCI || DM_PCI 32 default y 33 help 34 Enable PCI memory and I/O space resource allocation and assignment. 35 36config PCI_SANDBOX 37 bool "Sandbox PCI support" 38 depends on SANDBOX && DM_PCI 39 help 40 Support PCI on sandbox, as an emulated bus. This permits testing of 41 PCI feature such as bus scanning, device configuration and device 42 access. The available (emulated) devices are defined statically in 43 the device tree but the normal PCI scan technique is used to find 44 then. 45 46config PCI_TEGRA 47 bool "Tegra PCI support" 48 depends on TEGRA 49 depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) 50 help 51 Enable support for the PCIe controller found on some generations of 52 Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 53 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports 54 with a total of 5 lanes. Some boards require this for Ethernet 55 support to work (e.g. beaver, jetson-tk1). 56 57config PCI_XILINX 58 bool "Xilinx AXI Bridge for PCI Express" 59 depends on DM_PCI 60 help 61 Enable support for the Xilinx AXI bridge for PCI express, an IP block 62 which can be used on some generations of Xilinx FPGAs. 63 64endif 65