1source "drivers/net/phy/Kconfig" 2source "drivers/net/pfe_eth/Kconfig" 3 4config DM_ETH 5 bool "Enable Driver Model for Ethernet drivers" 6 depends on DM 7 help 8 Enable driver model for Ethernet. 9 10 The eth_*() interface will be implemented by the UCLASS_ETH class 11 This is currently implemented in net/eth-uclass.c 12 Look in include/net.h for details. 13 14menuconfig NETDEVICES 15 bool "Network device support" 16 depends on NET 17 default y if DM_ETH 18 help 19 You must select Y to enable any network device support 20 Generally if you have any networking support this is a given 21 22 If unsure, say Y 23 24if NETDEVICES 25 26config PHY_GIGE 27 bool "Enable GbE PHY status parsing and configuration" 28 help 29 Enables support for parsing the status output and for 30 configuring GbE PHYs (affects the inner workings of some 31 commands and miiphyutil.c). 32 33config AG7XXX 34 bool "Atheros AG7xxx Ethernet MAC support" 35 depends on DM_ETH && ARCH_ATH79 36 select PHYLIB 37 help 38 This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is 39 present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips. 40 41 42config ALTERA_TSE 43 bool "Altera Triple-Speed Ethernet MAC support" 44 depends on DM_ETH 45 select PHYLIB 46 help 47 This driver supports the Altera Triple-Speed (TSE) Ethernet MAC. 48 Please find details on the "Triple-Speed Ethernet MegaCore Function 49 Resource Center" of Altera. 50 51config BCM_SF2_ETH 52 bool "Broadcom SF2 (Starfighter2) Ethernet support" 53 select PHYLIB 54 help 55 This is an abstract framework which provides a generic interface 56 to MAC and DMA management for multiple Broadcom SoCs such as 57 Cygnus, NSP and bcm28155_ap platforms. 58 59config BCM_SF2_ETH_DEFAULT_PORT 60 int "Broadcom SF2 (Starfighter2) Ethernet default port number" 61 depends on BCM_SF2_ETH 62 default 0 63 help 64 Default port number for the Starfighter2 ethernet driver. 65 66config BCM_SF2_ETH_GMAC 67 bool "Broadcom SF2 (Starfighter2) GMAC Ethernet support" 68 depends on BCM_SF2_ETH 69 help 70 This flag enables the ethernet support for Broadcom platforms with 71 GMAC such as Cygnus. This driver is based on the framework provided 72 by the BCM_SF2_ETH driver. 73 Say Y to any bcmcygnus based platforms. 74 75config BCM6348_ETH 76 bool "BCM6348 EMAC support" 77 depends on DM_ETH && ARCH_BMIPS 78 select DMA 79 select DMA_CHANNELS 80 select MII 81 select PHYLIB 82 help 83 This driver supports the BCM6348 Ethernet MAC. 84 85config BCM6368_ETH 86 bool "BCM6368 EMAC support" 87 depends on DM_ETH && ARCH_BMIPS 88 select DMA 89 select MII 90 help 91 This driver supports the BCM6368 Ethernet MAC. 92 93config DWC_ETH_QOS 94 bool "Synopsys DWC Ethernet QOS device support" 95 depends on DM_ETH 96 select PHYLIB 97 help 98 This driver supports the Synopsys Designware Ethernet QOS (Quality 99 Of Service) IP block. The IP supports many options for bus type, 100 clocking/reset structure, and feature list. This driver currently 101 supports the specific configuration used in NVIDIA's Tegra186 chip, 102 but should be extensible to other combinations quite easily. 103 104config E1000 105 bool "Intel PRO/1000 Gigabit Ethernet support" 106 help 107 This driver supports Intel(R) PRO/1000 gigabit ethernet family of 108 adapters. For more information on how to identify your adapter, go 109 to the Adapter & Driver ID Guide at: 110 111 <http://support.intel.com/support/network/adapter/pro100/21397.htm> 112 113config E1000_SPI_GENERIC 114 bool "Allow access to the Intel 8257x SPI bus" 115 depends on E1000 116 help 117 Allow generic access to the SPI bus on the Intel 8257x, for 118 example with the "sspi" command. 119 120config E1000_SPI 121 bool "Enable SPI bus utility code" 122 depends on E1000 123 help 124 Utility code for direct access to the SPI bus on Intel 8257x. 125 This does not do anything useful unless you set at least one 126 of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC. 127 128config CMD_E1000 129 bool "Enable the e1000 command" 130 depends on E1000 131 help 132 This enables the 'e1000' management command for E1000 devices. When 133 used on devices with SPI support you can reprogram the EEPROM from 134 U-Boot. 135 136config ETH_SANDBOX 137 depends on DM_ETH && SANDBOX 138 default y 139 bool "Sandbox: Mocked Ethernet driver" 140 help 141 This driver simply responds with fake ARP replies and ping 142 replies that are used to verify network stack functionality 143 144 This driver is particularly useful in the test/dm/eth.c tests 145 146config ETH_SANDBOX_RAW 147 depends on DM_ETH && SANDBOX 148 default y 149 bool "Sandbox: Bridge to Linux Raw Sockets" 150 help 151 This driver is a bridge from the bottom of the network stack 152 in U-Boot to the RAW AF_PACKET API in Linux. This allows real 153 network traffic to be tested from within sandbox. See 154 board/sandbox/README.sandbox for more details. 155 156config ETH_DESIGNWARE 157 bool "Synopsys Designware Ethernet MAC" 158 select PHYLIB 159 help 160 This MAC is present in SoCs from various vendors. It supports 161 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to 162 provide the PHY (physical media interface). 163 164config ETH_DESIGNWARE_SOCFPGA 165 bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" 166 depends on DM_ETH && ETH_DESIGNWARE 167 help 168 The Altera SoCFPGA requires additional configuration of the 169 Altera system manager to correctly interface with the PHY. 170 This code handles those SoC specifics. 171 172config ETHOC 173 bool "OpenCores 10/100 Mbps Ethernet MAC" 174 help 175 This MAC is present in OpenRISC and Xtensa XTFPGA boards. 176 177config FEC_MXC_SHARE_MDIO 178 bool "Share the MDIO bus for FEC controller" 179 depends on FEC_MXC 180 181config FEC_MXC_MDIO_BASE 182 hex "MDIO base address for the FEC controller" 183 depends on FEC_MXC_SHARE_MDIO 184 help 185 This specifies the MDIO registers base address. It is used when 186 two FEC controllers share MDIO bus. 187 188config FEC_MXC 189 bool "FEC Ethernet controller" 190 depends on MX5 || MX6 || MX7 || IMX8 191 help 192 This driver supports the 10/100 Fast Ethernet controller for 193 NXP i.MX processors. 194 195config FTMAC100 196 bool "Ftmac100 Ethernet Support" 197 help 198 This MAC is present in Andestech SoCs. 199 200config FTGMAC100 201 bool "Ftgmac100 Ethernet Support" 202 depends on DM_ETH 203 select PHYLIB 204 help 205 This driver supports the Faraday's FTGMAC100 Gigabit SoC 206 Ethernet controller that can be found on Aspeed SoCs (which 207 include NCSI). 208 209 It is fully compliant with IEEE 802.3 specification for 210 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000 211 Mbps Ethernet and includes Reduced Media Independent 212 Interface (RMII) and Reduced Gigabit Media Independent 213 Interface (RGMII) interfaces. It adopts an AHB bus interface 214 and integrates a link list DMA engine with direct M-Bus 215 accesses for transmitting and receiving packets. It has 216 independent TX/RX fifos, supports half and full duplex (1000 217 Mbps mode only supports full duplex), flow control for full 218 duplex and backpressure for half duplex. 219 220 The FTGMAC100 also implements IP, TCP, UDP checksum offloads 221 and supports IEEE 802.1Q VLAN tag insertion and removal. It 222 offers high-priority transmit queue for QoS and CoS 223 applications. 224 225 226config MVGBE 227 bool "Marvell Orion5x/Kirkwood network interface support" 228 depends on KIRKWOOD || ORION5X 229 select PHYLIB if DM_ETH 230 help 231 This driver supports the network interface units in the 232 Marvell Orion5x and Kirkwood SoCs 233 234config MVNETA 235 bool "Marvell Armada XP/385/3700 network interface support" 236 depends on ARMADA_XP || ARMADA_38X || ARMADA_3700 237 select PHYLIB 238 help 239 This driver supports the network interface units in the 240 Marvell ARMADA XP, ARMADA 38X and ARMADA 3700 SoCs 241 242config MVPP2 243 bool "Marvell Armada 375/7K/8K network interface support" 244 depends on ARMADA_375 || ARMADA_8K 245 select PHYLIB 246 help 247 This driver supports the network interface units in the 248 Marvell ARMADA 375, 7K and 8K SoCs. 249 250config MACB 251 bool "Cadence MACB/GEM Ethernet Interface" 252 depends on DM_ETH 253 select PHYLIB 254 help 255 The Cadence MACB ethernet interface is found on many Atmel 256 AT91 and SAMA5 parts. This driver also supports the Cadence 257 GEM (Gigabit Ethernet MAC) found in some ARM SoC devices. 258 Say Y to include support for the MACB/GEM chip. 259 260config MACB_ZYNQ 261 bool "Cadence MACB/GEM Ethernet Interface for Xilinx Zynq" 262 depends on MACB 263 help 264 The Cadence MACB ethernet interface was used on Zynq platform. 265 Say Y to enable support for the MACB/GEM in Zynq chip. 266 267config MT7628_ETH 268 bool "MediaTek MT7628 Ethernet Interface" 269 depends on ARCH_MT7620 270 help 271 The MediaTek MT7628 ethernet interface is used on MT7628 and 272 MT7688 based boards. 273 274config PCH_GBE 275 bool "Intel Platform Controller Hub EG20T GMAC driver" 276 depends on DM_ETH && DM_PCI 277 select PHYLIB 278 help 279 This MAC is present in Intel Platform Controller Hub EG20T. It 280 supports 10/100/1000 Mbps operation. 281 282config RGMII 283 bool "Enable RGMII" 284 help 285 Enable the support of the Reduced Gigabit Media-Independent 286 Interface (RGMII). 287 288config MII 289 bool "Enable MII" 290 help 291 Enable support of the Media-Independent Interface (MII) 292 293config RTL8139 294 bool "Realtek 8139 series Ethernet controller driver" 295 help 296 This driver supports Realtek 8139 series fast ethernet family of 297 PCI chipsets/adapters. 298 299config RTL8169 300 bool "Realtek 8169 series Ethernet controller driver" 301 help 302 This driver supports Realtek 8169 series gigabit ethernet family of 303 PCI/PCIe chipsets/adapters. 304 305config SMC911X 306 bool "SMSC LAN911x and LAN921x controller driver" 307 308if SMC911X 309 310config SMC911X_BASE 311 hex "SMC911X Base Address" 312 help 313 Define this to hold the physical address 314 of the device (I/O space) 315 316choice 317 prompt "SMC911X bus width" 318 default SMC911X_16_BIT 319 320config SMC911X_32_BIT 321 bool "Enable 32-bit interface" 322 323config SMC911X_16_BIT 324 bool "Enable 16-bit interface" 325 help 326 Define this if data bus is 16 bits. If your processor 327 automatically converts one 32 bit word to two 16 bit 328 words you may also try CONFIG_SMC911X_32_BIT. 329 330endchoice 331endif #SMC911X 332 333config SUN7I_GMAC 334 bool "Enable Allwinner GMAC Ethernet support" 335 help 336 Enable the support for Sun7i GMAC Ethernet controller 337 338config SUN7I_GMAC_FORCE_TXERR 339 bool "Force PA17 as gmac function" 340 depends on SUN7I_GMAC 341 help 342 Some ethernet phys needs TXERR control. Since the GMAC 343 doesn't have such signal, setting PA17 as GMAC function 344 makes the pin output low, which enables data transmission. 345 346config SUN4I_EMAC 347 bool "Allwinner Sun4i Ethernet MAC support" 348 depends on DM_ETH 349 select PHYLIB 350 help 351 This driver supports the Allwinner based SUN4I Ethernet MAC. 352 353config SUN8I_EMAC 354 bool "Allwinner Sun8i Ethernet MAC support" 355 depends on DM_ETH 356 select PHYLIB 357 select PHY_GIGE 358 help 359 This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. 360 It can be found in H3/A64/A83T based SoCs and compatible with both 361 External and Internal PHYs. 362 363config SH_ETHER 364 bool "Renesas SH Ethernet MAC" 365 select PHYLIB 366 help 367 This driver supports the Ethernet for Renesas SH and ARM SoCs. 368 369source "drivers/net/ti/Kconfig" 370 371config XILINX_AXIEMAC 372 depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) 373 select PHYLIB 374 select MII 375 bool "Xilinx AXI Ethernet" 376 help 377 This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. 378 379config XILINX_EMACLITE 380 depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || MIPS) 381 select PHYLIB 382 select MII 383 bool "Xilinx Ethernetlite" 384 help 385 This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. 386 387config ZYNQ_GEM 388 depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL) 389 select PHYLIB 390 bool "Xilinx Ethernet GEM" 391 help 392 This MAC is present in Xilinx Zynq and ZynqMP SoCs. 393 394config PIC32_ETH 395 bool "Microchip PIC32 Ethernet Support" 396 depends on DM_ETH && MACH_PIC32 397 select PHYLIB 398 help 399 This driver implements 10/100 Mbps Ethernet and MAC layer for 400 Microchip PIC32 microcontrollers. 401 402config GMAC_ROCKCHIP 403 bool "Rockchip Synopsys Designware Ethernet MAC" 404 depends on DM_ETH && ETH_DESIGNWARE 405 help 406 This driver provides Rockchip SoCs network support based on the 407 Synopsys Designware driver. 408 409config RENESAS_RAVB 410 bool "Renesas Ethernet AVB MAC" 411 depends on DM_ETH && RCAR_GEN3 412 select PHYLIB 413 help 414 This driver implements support for the Ethernet AVB block in 415 Renesas M3 and H3 SoCs. 416 417config MPC8XX_FEC 418 bool "Fast Ethernet Controller on MPC8XX" 419 depends on MPC8xx 420 select MII 421 help 422 This driver implements support for the Fast Ethernet Controller 423 on MPC8XX 424 425config SNI_AVE 426 bool "Socionext AVE Ethernet support" 427 depends on DM_ETH && ARCH_UNIPHIER 428 select PHYLIB 429 select SYSCON 430 select REGMAP 431 help 432 This driver implements support for the Socionext AVE Ethernet 433 controller, as found on the Socionext UniPhier family. 434 435config ETHER_ON_FEC1 436 bool "FEC1" 437 depends on MPC8XX_FEC 438 default y 439 440config FEC1_PHY 441 int "FEC1 PHY" 442 depends on ETHER_ON_FEC1 443 default -1 444 help 445 Define to the hardcoded PHY address which corresponds 446 to the given FEC; i. e. 447 #define CONFIG_FEC1_PHY 4 448 means that the PHY with address 4 is connected to FEC1 449 450 When set to -1, means to probe for first available. 451 452config PHY_NORXERR 453 bool "PHY_NORXERR" 454 depends on ETHER_ON_FEC1 455 default n 456 help 457 The PHY does not have a RXERR line (RMII only). 458 (so program the FEC to ignore it). 459 460config ETHER_ON_FEC2 461 bool "FEC2" 462 depends on MPC8XX_FEC && MPC885 463 default y 464 465config FEC2_PHY 466 int "FEC2 PHY" 467 depends on ETHER_ON_FEC2 468 default -1 469 help 470 Define to the hardcoded PHY address which corresponds 471 to the given FEC; i. e. 472 #define CONFIG_FEC1_PHY 4 473 means that the PHY with address 4 is connected to FEC1 474 475 When set to -1, means to probe for first available. 476 477config FEC2_PHY_NORXERR 478 bool "PHY_NORXERR" 479 depends on ETHER_ON_FEC2 480 default n 481 help 482 The PHY does not have a RXERR line (RMII only). 483 (so program the FEC to ignore it). 484 485config SYS_DPAA_QBMAN 486 bool "Device tree fixup for QBMan on freescale SOCs" 487 depends on (ARM || PPC) && !SPL_BUILD 488 default y if ARCH_B4860 || \ 489 ARCH_B4420 || \ 490 ARCH_P1023 || \ 491 ARCH_P2041 || \ 492 ARCH_T1023 || \ 493 ARCH_T1024 || \ 494 ARCH_T1040 || \ 495 ARCH_T1042 || \ 496 ARCH_T2080 || \ 497 ARCH_T2081 || \ 498 ARCH_T4240 || \ 499 ARCH_T4160 || \ 500 ARCH_P4080 || \ 501 ARCH_P3041 || \ 502 ARCH_P5040 || \ 503 ARCH_P5020 || \ 504 ARCH_LS1043A || \ 505 ARCH_LS1046A 506 help 507 QBman fixups to allow deep sleep in DPAA 1 SOCs 508 509config TSEC_ENET 510 select PHYLIB 511 bool "Enable Three-Speed Ethernet Controller" 512 help 513 This driver implements support for the (Enhanced) Three-Speed 514 Ethernet Controller found on Freescale SoCs. 515 516endif # NETDEVICES 517