1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 * 9 * Synced from Linux v4.19 10 */ 11 12 #include <common.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/log2.h> 16 #include <linux/math64.h> 17 #include <linux/sizes.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/spi-nor.h> 21 #include <spi-mem.h> 22 #include <spi.h> 23 24 #include "sf_internal.h" 25 26 /* Define max times to check status register before we give up. */ 27 28 /* 29 * For everything but full-chip erase; probably could be much smaller, but kept 30 * around for safety for now 31 */ 32 33 #define HZ CONFIG_SYS_HZ 34 35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 36 37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op 38 *op, void *buf) 39 { 40 if (op->data.dir == SPI_MEM_DATA_IN) 41 op->data.buf.in = buf; 42 else 43 op->data.buf.out = buf; 44 return spi_mem_exec_op(nor->spi, op); 45 } 46 47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) 48 { 49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1), 50 SPI_MEM_OP_NO_ADDR, 51 SPI_MEM_OP_NO_DUMMY, 52 SPI_MEM_OP_DATA_IN(len, NULL, 1)); 53 int ret; 54 55 ret = spi_nor_read_write_reg(nor, &op, val); 56 if (ret < 0) 57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret, 58 code); 59 60 return ret; 61 } 62 63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) 64 { 65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), 66 SPI_MEM_OP_NO_ADDR, 67 SPI_MEM_OP_NO_DUMMY, 68 SPI_MEM_OP_DATA_OUT(len, NULL, 1)); 69 70 return spi_nor_read_write_reg(nor, &op, buf); 71 } 72 73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 74 u_char *buf) 75 { 76 struct spi_mem_op op = 77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1), 79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 80 SPI_MEM_OP_DATA_IN(len, buf, 1)); 81 size_t remaining = len; 82 int ret; 83 84 /* get transfer protocols. */ 85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 87 op.dummy.buswidth = op.addr.buswidth; 88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 89 90 /* convert the dummy cycles to the number of bytes */ 91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 92 93 while (remaining) { 94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 95 ret = spi_mem_adjust_op_size(nor->spi, &op); 96 if (ret) 97 return ret; 98 99 ret = spi_mem_exec_op(nor->spi, &op); 100 if (ret) 101 return ret; 102 103 op.addr.val += op.data.nbytes; 104 remaining -= op.data.nbytes; 105 op.data.buf.in += op.data.nbytes; 106 } 107 108 return len; 109 } 110 111 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 112 const u_char *buf) 113 { 114 struct spi_mem_op op = 115 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 116 SPI_MEM_OP_ADDR(nor->addr_width, to, 1), 117 SPI_MEM_OP_NO_DUMMY, 118 SPI_MEM_OP_DATA_OUT(len, buf, 1)); 119 size_t remaining = len; 120 int ret; 121 122 /* get transfer protocols. */ 123 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 124 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 125 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 126 127 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 128 op.addr.nbytes = 0; 129 130 while (remaining) { 131 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 132 ret = spi_mem_adjust_op_size(nor->spi, &op); 133 if (ret) 134 return ret; 135 136 ret = spi_mem_exec_op(nor->spi, &op); 137 if (ret) 138 return ret; 139 140 op.addr.val += op.data.nbytes; 141 remaining -= op.data.nbytes; 142 op.data.buf.out += op.data.nbytes; 143 } 144 145 return len; 146 } 147 148 /* 149 * Read the status register, returning its value in the location 150 * Return the status register value. 151 * Returns negative if error occurred. 152 */ 153 static int read_sr(struct spi_nor *nor) 154 { 155 int ret; 156 u8 val; 157 158 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); 159 if (ret < 0) { 160 pr_debug("error %d reading SR\n", (int)ret); 161 return ret; 162 } 163 164 return val; 165 } 166 167 /* 168 * Read the flag status register, returning its value in the location 169 * Return the status register value. 170 * Returns negative if error occurred. 171 */ 172 static int read_fsr(struct spi_nor *nor) 173 { 174 int ret; 175 u8 val; 176 177 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); 178 if (ret < 0) { 179 pr_debug("error %d reading FSR\n", ret); 180 return ret; 181 } 182 183 return val; 184 } 185 186 /* 187 * Read configuration register, returning its value in the 188 * location. Return the configuration register value. 189 * Returns negative if error occurred. 190 */ 191 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 192 static int read_cr(struct spi_nor *nor) 193 { 194 int ret; 195 u8 val; 196 197 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); 198 if (ret < 0) { 199 dev_dbg(nor->dev, "error %d reading CR\n", ret); 200 return ret; 201 } 202 203 return val; 204 } 205 #endif 206 207 /* 208 * Write status register 1 byte 209 * Returns negative if error occurred. 210 */ 211 static int write_sr(struct spi_nor *nor, u8 val) 212 { 213 nor->cmd_buf[0] = val; 214 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); 215 } 216 217 /* 218 * Set write enable latch with Write Enable command. 219 * Returns negative if error occurred. 220 */ 221 static int write_enable(struct spi_nor *nor) 222 { 223 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); 224 } 225 226 /* 227 * Send write disable instruction to the chip. 228 */ 229 static int write_disable(struct spi_nor *nor) 230 { 231 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); 232 } 233 234 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) 235 { 236 return mtd->priv; 237 } 238 239 #ifndef CONFIG_SPI_FLASH_BAR 240 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 241 { 242 size_t i; 243 244 for (i = 0; i < size; i++) 245 if (table[i][0] == opcode) 246 return table[i][1]; 247 248 /* No conversion found, keep input op code. */ 249 return opcode; 250 } 251 252 static u8 spi_nor_convert_3to4_read(u8 opcode) 253 { 254 static const u8 spi_nor_3to4_read[][2] = { 255 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 256 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 257 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 258 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 259 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 260 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 261 262 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 263 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 264 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 265 }; 266 267 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 268 ARRAY_SIZE(spi_nor_3to4_read)); 269 } 270 271 static u8 spi_nor_convert_3to4_program(u8 opcode) 272 { 273 static const u8 spi_nor_3to4_program[][2] = { 274 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 275 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 276 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 277 }; 278 279 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 280 ARRAY_SIZE(spi_nor_3to4_program)); 281 } 282 283 static u8 spi_nor_convert_3to4_erase(u8 opcode) 284 { 285 static const u8 spi_nor_3to4_erase[][2] = { 286 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 287 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 288 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 289 }; 290 291 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 292 ARRAY_SIZE(spi_nor_3to4_erase)); 293 } 294 295 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, 296 const struct flash_info *info) 297 { 298 /* Do some manufacturer fixups first */ 299 switch (JEDEC_MFR(info)) { 300 case SNOR_MFR_SPANSION: 301 /* No small sector erase for 4-byte command set */ 302 nor->erase_opcode = SPINOR_OP_SE; 303 nor->mtd.erasesize = info->sector_size; 304 break; 305 306 default: 307 break; 308 } 309 310 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 311 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 312 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 313 } 314 #endif /* !CONFIG_SPI_FLASH_BAR */ 315 316 /* Enable/disable 4-byte addressing mode. */ 317 static int set_4byte(struct spi_nor *nor, const struct flash_info *info, 318 int enable) 319 { 320 int status; 321 bool need_wren = false; 322 u8 cmd; 323 324 switch (JEDEC_MFR(info)) { 325 case SNOR_MFR_ST: 326 case SNOR_MFR_MICRON: 327 /* Some Micron need WREN command; all will accept it */ 328 need_wren = true; 329 case SNOR_MFR_MACRONIX: 330 case SNOR_MFR_WINBOND: 331 if (need_wren) 332 write_enable(nor); 333 334 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; 335 status = nor->write_reg(nor, cmd, NULL, 0); 336 if (need_wren) 337 write_disable(nor); 338 339 if (!status && !enable && 340 JEDEC_MFR(info) == SNOR_MFR_WINBOND) { 341 /* 342 * On Winbond W25Q256FV, leaving 4byte mode causes 343 * the Extended Address Register to be set to 1, so all 344 * 3-byte-address reads come from the second 16M. 345 * We must clear the register to enable normal behavior. 346 */ 347 write_enable(nor); 348 nor->cmd_buf[0] = 0; 349 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1); 350 write_disable(nor); 351 } 352 353 return status; 354 default: 355 /* Spansion style */ 356 nor->cmd_buf[0] = enable << 7; 357 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); 358 } 359 } 360 361 static int spi_nor_sr_ready(struct spi_nor *nor) 362 { 363 int sr = read_sr(nor); 364 365 if (sr < 0) 366 return sr; 367 368 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) { 369 if (sr & SR_E_ERR) 370 dev_dbg(nor->dev, "Erase Error occurred\n"); 371 else 372 dev_dbg(nor->dev, "Programming Error occurred\n"); 373 374 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); 375 return -EIO; 376 } 377 378 return !(sr & SR_WIP); 379 } 380 381 static int spi_nor_fsr_ready(struct spi_nor *nor) 382 { 383 int fsr = read_fsr(nor); 384 385 if (fsr < 0) 386 return fsr; 387 388 if (fsr & (FSR_E_ERR | FSR_P_ERR)) { 389 if (fsr & FSR_E_ERR) 390 dev_dbg(nor->dev, "Erase operation failed.\n"); 391 else 392 dev_dbg(nor->dev, "Program operation failed.\n"); 393 394 if (fsr & FSR_PT_ERR) 395 dev_dbg(nor->dev, 396 "Attempted to modify a protected sector.\n"); 397 398 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); 399 return -EIO; 400 } 401 402 return fsr & FSR_READY; 403 } 404 405 static int spi_nor_ready(struct spi_nor *nor) 406 { 407 int sr, fsr; 408 409 sr = spi_nor_sr_ready(nor); 410 if (sr < 0) 411 return sr; 412 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 413 if (fsr < 0) 414 return fsr; 415 return sr && fsr; 416 } 417 418 /* 419 * Service routine to read status register until ready, or timeout occurs. 420 * Returns non-zero if error. 421 */ 422 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 423 unsigned long timeout) 424 { 425 unsigned long timebase; 426 int ret; 427 428 timebase = get_timer(0); 429 430 while (get_timer(timebase) < timeout) { 431 ret = spi_nor_ready(nor); 432 if (ret < 0) 433 return ret; 434 if (ret) 435 return 0; 436 } 437 438 dev_err(nor->dev, "flash operation timed out\n"); 439 440 return -ETIMEDOUT; 441 } 442 443 static int spi_nor_wait_till_ready(struct spi_nor *nor) 444 { 445 return spi_nor_wait_till_ready_with_timeout(nor, 446 DEFAULT_READY_WAIT_JIFFIES); 447 } 448 449 #ifdef CONFIG_SPI_FLASH_BAR 450 /* 451 * This "clean_bar" is necessary in a situation when one was accessing 452 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 453 * 454 * After it the BA24 bit shall be cleared to allow access to correct 455 * memory region after SW reset (by calling "reset" command). 456 * 457 * Otherwise, the BA24 bit may be left set and then after reset, the 458 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 459 */ 460 static int clean_bar(struct spi_nor *nor) 461 { 462 u8 cmd, bank_sel = 0; 463 464 if (nor->bank_curr == 0) 465 return 0; 466 cmd = nor->bank_write_cmd; 467 nor->bank_curr = 0; 468 write_enable(nor); 469 470 return nor->write_reg(nor, cmd, &bank_sel, 1); 471 } 472 473 static int write_bar(struct spi_nor *nor, u32 offset) 474 { 475 u8 cmd, bank_sel; 476 int ret; 477 478 bank_sel = offset / SZ_16M; 479 if (bank_sel == nor->bank_curr) 480 goto bar_end; 481 482 cmd = nor->bank_write_cmd; 483 write_enable(nor); 484 ret = nor->write_reg(nor, cmd, &bank_sel, 1); 485 if (ret < 0) { 486 debug("SF: fail to write bank register\n"); 487 return ret; 488 } 489 490 bar_end: 491 nor->bank_curr = bank_sel; 492 return nor->bank_curr; 493 } 494 495 static int read_bar(struct spi_nor *nor, const struct flash_info *info) 496 { 497 u8 curr_bank = 0; 498 int ret; 499 500 switch (JEDEC_MFR(info)) { 501 case SNOR_MFR_SPANSION: 502 nor->bank_read_cmd = SPINOR_OP_BRRD; 503 nor->bank_write_cmd = SPINOR_OP_BRWR; 504 break; 505 default: 506 nor->bank_read_cmd = SPINOR_OP_RDEAR; 507 nor->bank_write_cmd = SPINOR_OP_WREAR; 508 } 509 510 ret = nor->read_reg(nor, nor->bank_read_cmd, 511 &curr_bank, 1); 512 if (ret) { 513 debug("SF: fail to read bank addr register\n"); 514 return ret; 515 } 516 nor->bank_curr = curr_bank; 517 518 return 0; 519 } 520 #endif 521 522 /* 523 * Initiate the erasure of a single sector 524 */ 525 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 526 { 527 u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; 528 int i; 529 530 if (nor->erase) 531 return nor->erase(nor, addr); 532 533 /* 534 * Default implementation, if driver doesn't have a specialized HW 535 * control 536 */ 537 for (i = nor->addr_width - 1; i >= 0; i--) { 538 buf[i] = addr & 0xff; 539 addr >>= 8; 540 } 541 542 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); 543 } 544 545 /* 546 * Erase an address range on the nor chip. The address range may extend 547 * one or more erase sectors. Return an error is there is a problem erasing. 548 */ 549 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 550 { 551 struct spi_nor *nor = mtd_to_spi_nor(mtd); 552 u32 addr, len, rem; 553 int ret; 554 555 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 556 (long long)instr->len); 557 558 div_u64_rem(instr->len, mtd->erasesize, &rem); 559 if (rem) 560 return -EINVAL; 561 562 addr = instr->addr; 563 len = instr->len; 564 565 while (len) { 566 #ifdef CONFIG_SPI_FLASH_BAR 567 ret = write_bar(nor, addr); 568 if (ret < 0) 569 return ret; 570 #endif 571 write_enable(nor); 572 573 ret = spi_nor_erase_sector(nor, addr); 574 if (ret) 575 goto erase_err; 576 577 addr += mtd->erasesize; 578 len -= mtd->erasesize; 579 580 ret = spi_nor_wait_till_ready(nor); 581 if (ret) 582 goto erase_err; 583 } 584 585 erase_err: 586 #ifdef CONFIG_SPI_FLASH_BAR 587 ret = clean_bar(nor); 588 #endif 589 write_disable(nor); 590 591 return ret; 592 } 593 594 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 595 /* Write status register and ensure bits in mask match written values */ 596 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) 597 { 598 int ret; 599 600 write_enable(nor); 601 ret = write_sr(nor, status_new); 602 if (ret) 603 return ret; 604 605 ret = spi_nor_wait_till_ready(nor); 606 if (ret) 607 return ret; 608 609 ret = read_sr(nor); 610 if (ret < 0) 611 return ret; 612 613 return ((ret & mask) != (status_new & mask)) ? -EIO : 0; 614 } 615 616 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, 617 uint64_t *len) 618 { 619 struct mtd_info *mtd = &nor->mtd; 620 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 621 int shift = ffs(mask) - 1; 622 int pow; 623 624 if (!(sr & mask)) { 625 /* No protection */ 626 *ofs = 0; 627 *len = 0; 628 } else { 629 pow = ((sr & mask) ^ mask) >> shift; 630 *len = mtd->size >> pow; 631 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) 632 *ofs = 0; 633 else 634 *ofs = mtd->size - *len; 635 } 636 } 637 638 /* 639 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 640 * @locked is false); 0 otherwise 641 */ 642 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len, 643 u8 sr, bool locked) 644 { 645 loff_t lock_offs; 646 uint64_t lock_len; 647 648 if (!len) 649 return 1; 650 651 stm_get_locked_range(nor, sr, &lock_offs, &lock_len); 652 653 if (locked) 654 /* Requested range is a sub-range of locked range */ 655 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 656 else 657 /* Requested range does not overlap with locked range */ 658 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 659 } 660 661 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 662 u8 sr) 663 { 664 return stm_check_lock_status_sr(nor, ofs, len, sr, true); 665 } 666 667 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 668 u8 sr) 669 { 670 return stm_check_lock_status_sr(nor, ofs, len, sr, false); 671 } 672 673 /* 674 * Lock a region of the flash. Compatible with ST Micro and similar flash. 675 * Supports the block protection bits BP{0,1,2} in the status register 676 * (SR). Does not support these features found in newer SR bitfields: 677 * - SEC: sector/block protect - only handle SEC=0 (block protect) 678 * - CMP: complement protect - only support CMP=0 (range is not complemented) 679 * 680 * Support for the following is provided conditionally for some flash: 681 * - TB: top/bottom protect 682 * 683 * Sample table portion for 8MB flash (Winbond w25q64fw): 684 * 685 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 686 * -------------------------------------------------------------------------- 687 * X | X | 0 | 0 | 0 | NONE | NONE 688 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 689 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 690 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 691 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 692 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 693 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 694 * X | X | 1 | 1 | 1 | 8 MB | ALL 695 * ------|-------|-------|-------|-------|---------------|------------------- 696 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 697 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 698 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 699 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 700 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 701 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 702 * 703 * Returns negative on errors, 0 on success. 704 */ 705 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 706 { 707 struct mtd_info *mtd = &nor->mtd; 708 int status_old, status_new; 709 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 710 u8 shift = ffs(mask) - 1, pow, val; 711 loff_t lock_len; 712 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 713 bool use_top; 714 715 status_old = read_sr(nor); 716 if (status_old < 0) 717 return status_old; 718 719 /* If nothing in our range is unlocked, we don't need to do anything */ 720 if (stm_is_locked_sr(nor, ofs, len, status_old)) 721 return 0; 722 723 /* If anything below us is unlocked, we can't use 'bottom' protection */ 724 if (!stm_is_locked_sr(nor, 0, ofs, status_old)) 725 can_be_bottom = false; 726 727 /* If anything above us is unlocked, we can't use 'top' protection */ 728 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 729 status_old)) 730 can_be_top = false; 731 732 if (!can_be_bottom && !can_be_top) 733 return -EINVAL; 734 735 /* Prefer top, if both are valid */ 736 use_top = can_be_top; 737 738 /* lock_len: length of region that should end up locked */ 739 if (use_top) 740 lock_len = mtd->size - ofs; 741 else 742 lock_len = ofs + len; 743 744 /* 745 * Need smallest pow such that: 746 * 747 * 1 / (2^pow) <= (len / size) 748 * 749 * so (assuming power-of-2 size) we do: 750 * 751 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 752 */ 753 pow = ilog2(mtd->size) - ilog2(lock_len); 754 val = mask - (pow << shift); 755 if (val & ~mask) 756 return -EINVAL; 757 /* Don't "lock" with no region! */ 758 if (!(val & mask)) 759 return -EINVAL; 760 761 status_new = (status_old & ~mask & ~SR_TB) | val; 762 763 /* Disallow further writes if WP pin is asserted */ 764 status_new |= SR_SRWD; 765 766 if (!use_top) 767 status_new |= SR_TB; 768 769 /* Don't bother if they're the same */ 770 if (status_new == status_old) 771 return 0; 772 773 /* Only modify protection if it will not unlock other areas */ 774 if ((status_new & mask) < (status_old & mask)) 775 return -EINVAL; 776 777 return write_sr_and_check(nor, status_new, mask); 778 } 779 780 /* 781 * Unlock a region of the flash. See stm_lock() for more info 782 * 783 * Returns negative on errors, 0 on success. 784 */ 785 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 786 { 787 struct mtd_info *mtd = &nor->mtd; 788 int status_old, status_new; 789 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 790 u8 shift = ffs(mask) - 1, pow, val; 791 loff_t lock_len; 792 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 793 bool use_top; 794 795 status_old = read_sr(nor); 796 if (status_old < 0) 797 return status_old; 798 799 /* If nothing in our range is locked, we don't need to do anything */ 800 if (stm_is_unlocked_sr(nor, ofs, len, status_old)) 801 return 0; 802 803 /* If anything below us is locked, we can't use 'top' protection */ 804 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) 805 can_be_top = false; 806 807 /* If anything above us is locked, we can't use 'bottom' protection */ 808 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 809 status_old)) 810 can_be_bottom = false; 811 812 if (!can_be_bottom && !can_be_top) 813 return -EINVAL; 814 815 /* Prefer top, if both are valid */ 816 use_top = can_be_top; 817 818 /* lock_len: length of region that should remain locked */ 819 if (use_top) 820 lock_len = mtd->size - (ofs + len); 821 else 822 lock_len = ofs; 823 824 /* 825 * Need largest pow such that: 826 * 827 * 1 / (2^pow) >= (len / size) 828 * 829 * so (assuming power-of-2 size) we do: 830 * 831 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 832 */ 833 pow = ilog2(mtd->size) - order_base_2(lock_len); 834 if (lock_len == 0) { 835 val = 0; /* fully unlocked */ 836 } else { 837 val = mask - (pow << shift); 838 /* Some power-of-two sizes are not supported */ 839 if (val & ~mask) 840 return -EINVAL; 841 } 842 843 status_new = (status_old & ~mask & ~SR_TB) | val; 844 845 /* Don't protect status register if we're fully unlocked */ 846 if (lock_len == 0) 847 status_new &= ~SR_SRWD; 848 849 if (!use_top) 850 status_new |= SR_TB; 851 852 /* Don't bother if they're the same */ 853 if (status_new == status_old) 854 return 0; 855 856 /* Only modify protection if it will not lock other areas */ 857 if ((status_new & mask) > (status_old & mask)) 858 return -EINVAL; 859 860 return write_sr_and_check(nor, status_new, mask); 861 } 862 863 /* 864 * Check if a region of the flash is (completely) locked. See stm_lock() for 865 * more info. 866 * 867 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 868 * negative on errors. 869 */ 870 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 871 { 872 int status; 873 874 status = read_sr(nor); 875 if (status < 0) 876 return status; 877 878 return stm_is_locked_sr(nor, ofs, len, status); 879 } 880 #endif /* CONFIG_SPI_FLASH_STMICRO */ 881 882 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 883 { 884 int tmp; 885 u8 id[SPI_NOR_MAX_ID_LEN]; 886 const struct flash_info *info; 887 888 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); 889 if (tmp < 0) { 890 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); 891 return ERR_PTR(tmp); 892 } 893 894 info = spi_nor_ids; 895 for (; info->name; info++) { 896 if (info->id_len) { 897 if (!memcmp(info->id, id, info->id_len)) 898 return info; 899 } 900 } 901 902 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 903 id[0], id[1], id[2]); 904 return ERR_PTR(-ENODEV); 905 } 906 907 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 908 size_t *retlen, u_char *buf) 909 { 910 struct spi_nor *nor = mtd_to_spi_nor(mtd); 911 int ret; 912 913 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 914 915 while (len) { 916 loff_t addr = from; 917 size_t read_len = len; 918 919 #ifdef CONFIG_SPI_FLASH_BAR 920 u32 remain_len; 921 922 ret = write_bar(nor, addr); 923 if (ret < 0) 924 return log_ret(ret); 925 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr; 926 927 if (len < remain_len) 928 read_len = len; 929 else 930 read_len = remain_len; 931 #endif 932 933 ret = nor->read(nor, addr, read_len, buf); 934 if (ret == 0) { 935 /* We shouldn't see 0-length reads */ 936 ret = -EIO; 937 goto read_err; 938 } 939 if (ret < 0) 940 goto read_err; 941 942 *retlen += ret; 943 buf += ret; 944 from += ret; 945 len -= ret; 946 } 947 ret = 0; 948 949 read_err: 950 #ifdef CONFIG_SPI_FLASH_BAR 951 ret = clean_bar(nor); 952 #endif 953 return ret; 954 } 955 956 #ifdef CONFIG_SPI_FLASH_SST 957 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len, 958 size_t *retlen, const u_char *buf) 959 { 960 size_t actual; 961 int ret = 0; 962 963 for (actual = 0; actual < len; actual++) { 964 nor->program_opcode = SPINOR_OP_BP; 965 966 write_enable(nor); 967 /* write one byte. */ 968 ret = nor->write(nor, to, 1, buf + actual); 969 if (ret < 0) 970 goto sst_write_err; 971 ret = spi_nor_wait_till_ready(nor); 972 if (ret) 973 goto sst_write_err; 974 to++; 975 } 976 977 sst_write_err: 978 write_disable(nor); 979 return ret; 980 } 981 982 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 983 size_t *retlen, const u_char *buf) 984 { 985 struct spi_nor *nor = mtd_to_spi_nor(mtd); 986 struct spi_slave *spi = nor->spi; 987 size_t actual; 988 int ret; 989 990 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 991 if (spi->mode & SPI_TX_BYTE) 992 return sst_write_byteprogram(nor, to, len, retlen, buf); 993 994 write_enable(nor); 995 996 nor->sst_write_second = false; 997 998 actual = to % 2; 999 /* Start write from odd address. */ 1000 if (actual) { 1001 nor->program_opcode = SPINOR_OP_BP; 1002 1003 /* write one byte. */ 1004 ret = nor->write(nor, to, 1, buf); 1005 if (ret < 0) 1006 goto sst_write_err; 1007 ret = spi_nor_wait_till_ready(nor); 1008 if (ret) 1009 goto sst_write_err; 1010 } 1011 to += actual; 1012 1013 /* Write out most of the data here. */ 1014 for (; actual < len - 1; actual += 2) { 1015 nor->program_opcode = SPINOR_OP_AAI_WP; 1016 1017 /* write two bytes. */ 1018 ret = nor->write(nor, to, 2, buf + actual); 1019 if (ret < 0) 1020 goto sst_write_err; 1021 ret = spi_nor_wait_till_ready(nor); 1022 if (ret) 1023 goto sst_write_err; 1024 to += 2; 1025 nor->sst_write_second = true; 1026 } 1027 nor->sst_write_second = false; 1028 1029 write_disable(nor); 1030 ret = spi_nor_wait_till_ready(nor); 1031 if (ret) 1032 goto sst_write_err; 1033 1034 /* Write out trailing byte if it exists. */ 1035 if (actual != len) { 1036 write_enable(nor); 1037 1038 nor->program_opcode = SPINOR_OP_BP; 1039 ret = nor->write(nor, to, 1, buf + actual); 1040 if (ret < 0) 1041 goto sst_write_err; 1042 ret = spi_nor_wait_till_ready(nor); 1043 if (ret) 1044 goto sst_write_err; 1045 write_disable(nor); 1046 actual += 1; 1047 } 1048 sst_write_err: 1049 *retlen += actual; 1050 return ret; 1051 } 1052 #endif 1053 /* 1054 * Write an address range to the nor chip. Data must be written in 1055 * FLASH_PAGESIZE chunks. The address range may be any size provided 1056 * it is within the physical boundaries. 1057 */ 1058 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 1059 size_t *retlen, const u_char *buf) 1060 { 1061 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1062 size_t page_offset, page_remain, i; 1063 ssize_t ret; 1064 1065 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1066 1067 for (i = 0; i < len; ) { 1068 ssize_t written; 1069 loff_t addr = to + i; 1070 1071 /* 1072 * If page_size is a power of two, the offset can be quickly 1073 * calculated with an AND operation. On the other cases we 1074 * need to do a modulus operation (more expensive). 1075 * Power of two numbers have only one bit set and we can use 1076 * the instruction hweight32 to detect if we need to do a 1077 * modulus (do_div()) or not. 1078 */ 1079 if (hweight32(nor->page_size) == 1) { 1080 page_offset = addr & (nor->page_size - 1); 1081 } else { 1082 u64 aux = addr; 1083 1084 page_offset = do_div(aux, nor->page_size); 1085 } 1086 /* the size of data remaining on the first page */ 1087 page_remain = min_t(size_t, 1088 nor->page_size - page_offset, len - i); 1089 1090 #ifdef CONFIG_SPI_FLASH_BAR 1091 ret = write_bar(nor, addr); 1092 if (ret < 0) 1093 return ret; 1094 #endif 1095 write_enable(nor); 1096 ret = nor->write(nor, addr, page_remain, buf + i); 1097 if (ret < 0) 1098 goto write_err; 1099 written = ret; 1100 1101 ret = spi_nor_wait_till_ready(nor); 1102 if (ret) 1103 goto write_err; 1104 *retlen += written; 1105 i += written; 1106 if (written != page_remain) { 1107 ret = -EIO; 1108 goto write_err; 1109 } 1110 } 1111 1112 write_err: 1113 #ifdef CONFIG_SPI_FLASH_BAR 1114 ret = clean_bar(nor); 1115 #endif 1116 return ret; 1117 } 1118 1119 #ifdef CONFIG_SPI_FLASH_MACRONIX 1120 /** 1121 * macronix_quad_enable() - set QE bit in Status Register. 1122 * @nor: pointer to a 'struct spi_nor' 1123 * 1124 * Set the Quad Enable (QE) bit in the Status Register. 1125 * 1126 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. 1127 * 1128 * Return: 0 on success, -errno otherwise. 1129 */ 1130 static int macronix_quad_enable(struct spi_nor *nor) 1131 { 1132 int ret, val; 1133 1134 val = read_sr(nor); 1135 if (val < 0) 1136 return val; 1137 if (val & SR_QUAD_EN_MX) 1138 return 0; 1139 1140 write_enable(nor); 1141 1142 write_sr(nor, val | SR_QUAD_EN_MX); 1143 1144 ret = spi_nor_wait_till_ready(nor); 1145 if (ret) 1146 return ret; 1147 1148 ret = read_sr(nor); 1149 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { 1150 dev_err(nor->dev, "Macronix Quad bit not set\n"); 1151 return -EINVAL; 1152 } 1153 1154 return 0; 1155 } 1156 #endif 1157 1158 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1159 /* 1160 * Write status Register and configuration register with 2 bytes 1161 * The first byte will be written to the status register, while the 1162 * second byte will be written to the configuration register. 1163 * Return negative if error occurred. 1164 */ 1165 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) 1166 { 1167 int ret; 1168 1169 write_enable(nor); 1170 1171 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); 1172 if (ret < 0) { 1173 dev_dbg(nor->dev, 1174 "error while writing configuration register\n"); 1175 return -EINVAL; 1176 } 1177 1178 ret = spi_nor_wait_till_ready(nor); 1179 if (ret) { 1180 dev_dbg(nor->dev, 1181 "timeout while writing configuration register\n"); 1182 return ret; 1183 } 1184 1185 return 0; 1186 } 1187 1188 /** 1189 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. 1190 * @nor: pointer to a 'struct spi_nor' 1191 * 1192 * Set the Quad Enable (QE) bit in the Configuration Register. 1193 * This function should be used with QSPI memories supporting the Read 1194 * Configuration Register (35h) instruction. 1195 * 1196 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1197 * memories. 1198 * 1199 * Return: 0 on success, -errno otherwise. 1200 */ 1201 static int spansion_read_cr_quad_enable(struct spi_nor *nor) 1202 { 1203 u8 sr_cr[2]; 1204 int ret; 1205 1206 /* Check current Quad Enable bit value. */ 1207 ret = read_cr(nor); 1208 if (ret < 0) { 1209 dev_dbg(dev, "error while reading configuration register\n"); 1210 return -EINVAL; 1211 } 1212 1213 if (ret & CR_QUAD_EN_SPAN) 1214 return 0; 1215 1216 sr_cr[1] = ret | CR_QUAD_EN_SPAN; 1217 1218 /* Keep the current value of the Status Register. */ 1219 ret = read_sr(nor); 1220 if (ret < 0) { 1221 dev_dbg(dev, "error while reading status register\n"); 1222 return -EINVAL; 1223 } 1224 sr_cr[0] = ret; 1225 1226 ret = write_sr_cr(nor, sr_cr); 1227 if (ret) 1228 return ret; 1229 1230 /* Read back and check it. */ 1231 ret = read_cr(nor); 1232 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { 1233 dev_dbg(nor->dev, "Spansion Quad bit not set\n"); 1234 return -EINVAL; 1235 } 1236 1237 return 0; 1238 } 1239 1240 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1241 /** 1242 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. 1243 * @nor: pointer to a 'struct spi_nor' 1244 * 1245 * Set the Quad Enable (QE) bit in the Configuration Register. 1246 * This function should be used with QSPI memories not supporting the Read 1247 * Configuration Register (35h) instruction. 1248 * 1249 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1250 * memories. 1251 * 1252 * Return: 0 on success, -errno otherwise. 1253 */ 1254 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) 1255 { 1256 u8 sr_cr[2]; 1257 int ret; 1258 1259 /* Keep the current value of the Status Register. */ 1260 ret = read_sr(nor); 1261 if (ret < 0) { 1262 dev_dbg(nor->dev, "error while reading status register\n"); 1263 return -EINVAL; 1264 } 1265 sr_cr[0] = ret; 1266 sr_cr[1] = CR_QUAD_EN_SPAN; 1267 1268 return write_sr_cr(nor, sr_cr); 1269 } 1270 1271 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */ 1272 #endif /* CONFIG_SPI_FLASH_SPANSION */ 1273 1274 struct spi_nor_read_command { 1275 u8 num_mode_clocks; 1276 u8 num_wait_states; 1277 u8 opcode; 1278 enum spi_nor_protocol proto; 1279 }; 1280 1281 struct spi_nor_pp_command { 1282 u8 opcode; 1283 enum spi_nor_protocol proto; 1284 }; 1285 1286 enum spi_nor_read_command_index { 1287 SNOR_CMD_READ, 1288 SNOR_CMD_READ_FAST, 1289 SNOR_CMD_READ_1_1_1_DTR, 1290 1291 /* Dual SPI */ 1292 SNOR_CMD_READ_1_1_2, 1293 SNOR_CMD_READ_1_2_2, 1294 SNOR_CMD_READ_2_2_2, 1295 SNOR_CMD_READ_1_2_2_DTR, 1296 1297 /* Quad SPI */ 1298 SNOR_CMD_READ_1_1_4, 1299 SNOR_CMD_READ_1_4_4, 1300 SNOR_CMD_READ_4_4_4, 1301 SNOR_CMD_READ_1_4_4_DTR, 1302 1303 /* Octo SPI */ 1304 SNOR_CMD_READ_1_1_8, 1305 SNOR_CMD_READ_1_8_8, 1306 SNOR_CMD_READ_8_8_8, 1307 SNOR_CMD_READ_1_8_8_DTR, 1308 1309 SNOR_CMD_READ_MAX 1310 }; 1311 1312 enum spi_nor_pp_command_index { 1313 SNOR_CMD_PP, 1314 1315 /* Quad SPI */ 1316 SNOR_CMD_PP_1_1_4, 1317 SNOR_CMD_PP_1_4_4, 1318 SNOR_CMD_PP_4_4_4, 1319 1320 /* Octo SPI */ 1321 SNOR_CMD_PP_1_1_8, 1322 SNOR_CMD_PP_1_8_8, 1323 SNOR_CMD_PP_8_8_8, 1324 1325 SNOR_CMD_PP_MAX 1326 }; 1327 1328 struct spi_nor_flash_parameter { 1329 u64 size; 1330 u32 page_size; 1331 1332 struct spi_nor_hwcaps hwcaps; 1333 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 1334 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 1335 1336 int (*quad_enable)(struct spi_nor *nor); 1337 }; 1338 1339 static void 1340 spi_nor_set_read_settings(struct spi_nor_read_command *read, 1341 u8 num_mode_clocks, 1342 u8 num_wait_states, 1343 u8 opcode, 1344 enum spi_nor_protocol proto) 1345 { 1346 read->num_mode_clocks = num_mode_clocks; 1347 read->num_wait_states = num_wait_states; 1348 read->opcode = opcode; 1349 read->proto = proto; 1350 } 1351 1352 static void 1353 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, 1354 u8 opcode, 1355 enum spi_nor_protocol proto) 1356 { 1357 pp->opcode = opcode; 1358 pp->proto = proto; 1359 } 1360 1361 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1362 /* 1363 * Serial Flash Discoverable Parameters (SFDP) parsing. 1364 */ 1365 1366 /** 1367 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters. 1368 * @nor: pointer to a 'struct spi_nor' 1369 * @addr: offset in the SFDP area to start reading data from 1370 * @len: number of bytes to read 1371 * @buf: buffer where the SFDP data are copied into (dma-safe memory) 1372 * 1373 * Whatever the actual numbers of bytes for address and dummy cycles are 1374 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always 1375 * followed by a 3-byte address and 8 dummy clock cycles. 1376 * 1377 * Return: 0 on success, -errno otherwise. 1378 */ 1379 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, 1380 size_t len, void *buf) 1381 { 1382 u8 addr_width, read_opcode, read_dummy; 1383 int ret; 1384 1385 read_opcode = nor->read_opcode; 1386 addr_width = nor->addr_width; 1387 read_dummy = nor->read_dummy; 1388 1389 nor->read_opcode = SPINOR_OP_RDSFDP; 1390 nor->addr_width = 3; 1391 nor->read_dummy = 8; 1392 1393 while (len) { 1394 ret = nor->read(nor, addr, len, (u8 *)buf); 1395 if (!ret || ret > len) { 1396 ret = -EIO; 1397 goto read_err; 1398 } 1399 if (ret < 0) 1400 goto read_err; 1401 1402 buf += ret; 1403 addr += ret; 1404 len -= ret; 1405 } 1406 ret = 0; 1407 1408 read_err: 1409 nor->read_opcode = read_opcode; 1410 nor->addr_width = addr_width; 1411 nor->read_dummy = read_dummy; 1412 1413 return ret; 1414 } 1415 1416 struct sfdp_parameter_header { 1417 u8 id_lsb; 1418 u8 minor; 1419 u8 major; 1420 u8 length; /* in double words */ 1421 u8 parameter_table_pointer[3]; /* byte address */ 1422 u8 id_msb; 1423 }; 1424 1425 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) 1426 #define SFDP_PARAM_HEADER_PTP(p) \ 1427 (((p)->parameter_table_pointer[2] << 16) | \ 1428 ((p)->parameter_table_pointer[1] << 8) | \ 1429 ((p)->parameter_table_pointer[0] << 0)) 1430 1431 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ 1432 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ 1433 1434 #define SFDP_SIGNATURE 0x50444653U 1435 #define SFDP_JESD216_MAJOR 1 1436 #define SFDP_JESD216_MINOR 0 1437 #define SFDP_JESD216A_MINOR 5 1438 #define SFDP_JESD216B_MINOR 6 1439 1440 struct sfdp_header { 1441 u32 signature; /* Ox50444653U <=> "SFDP" */ 1442 u8 minor; 1443 u8 major; 1444 u8 nph; /* 0-base number of parameter headers */ 1445 u8 unused; 1446 1447 /* Basic Flash Parameter Table. */ 1448 struct sfdp_parameter_header bfpt_header; 1449 }; 1450 1451 /* Basic Flash Parameter Table */ 1452 1453 /* 1454 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 1455 * They are indexed from 1 but C arrays are indexed from 0. 1456 */ 1457 #define BFPT_DWORD(i) ((i) - 1) 1458 #define BFPT_DWORD_MAX 16 1459 1460 /* The first version of JESB216 defined only 9 DWORDs. */ 1461 #define BFPT_DWORD_MAX_JESD216 9 1462 1463 /* 1st DWORD. */ 1464 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 1465 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 1466 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 1467 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 1468 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 1469 #define BFPT_DWORD1_DTR BIT(19) 1470 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 1471 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 1472 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 1473 1474 /* 5th DWORD. */ 1475 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 1476 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 1477 1478 /* 11th DWORD. */ 1479 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 1480 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 1481 1482 /* 15th DWORD. */ 1483 1484 /* 1485 * (from JESD216 rev B) 1486 * Quad Enable Requirements (QER): 1487 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 1488 * reads based on instruction. DQ3/HOLD# functions are hold during 1489 * instruction phase. 1490 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 1491 * two data bytes where bit 1 of the second byte is one. 1492 * [...] 1493 * Writing only one byte to the status register has the side-effect of 1494 * clearing status register 2, including the QE bit. The 100b code is 1495 * used if writing one byte to the status register does not modify 1496 * status register 2. 1497 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 1498 * one data byte where bit 6 is one. 1499 * [...] 1500 * - 011b: QE is bit 7 of status register 2. It is set via Write status 1501 * register 2 instruction 3Eh with one data byte where bit 7 is one. 1502 * [...] 1503 * The status register 2 is read using instruction 3Fh. 1504 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 1505 * two data bytes where bit 1 of the second byte is one. 1506 * [...] 1507 * In contrast to the 001b code, writing one byte to the status 1508 * register does not modify status register 2. 1509 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 1510 * Read Status instruction 05h. Status register2 is read using 1511 * instruction 35h. QE is set via Writ Status instruction 01h with 1512 * two data bytes where bit 1 of the second byte is one. 1513 * [...] 1514 */ 1515 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 1516 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 1517 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 1518 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 1519 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 1520 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 1521 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 1522 1523 struct sfdp_bfpt { 1524 u32 dwords[BFPT_DWORD_MAX]; 1525 }; 1526 1527 /* Fast Read settings. */ 1528 1529 static void 1530 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read, 1531 u16 half, 1532 enum spi_nor_protocol proto) 1533 { 1534 read->num_mode_clocks = (half >> 5) & 0x07; 1535 read->num_wait_states = (half >> 0) & 0x1f; 1536 read->opcode = (half >> 8) & 0xff; 1537 read->proto = proto; 1538 } 1539 1540 struct sfdp_bfpt_read { 1541 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ 1542 u32 hwcaps; 1543 1544 /* 1545 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us 1546 * whether the Fast Read x-y-z command is supported. 1547 */ 1548 u32 supported_dword; 1549 u32 supported_bit; 1550 1551 /* 1552 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD 1553 * encodes the op code, the number of mode clocks and the number of wait 1554 * states to be used by Fast Read x-y-z command. 1555 */ 1556 u32 settings_dword; 1557 u32 settings_shift; 1558 1559 /* The SPI protocol for this Fast Read x-y-z command. */ 1560 enum spi_nor_protocol proto; 1561 }; 1562 1563 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = { 1564 /* Fast Read 1-1-2 */ 1565 { 1566 SNOR_HWCAPS_READ_1_1_2, 1567 BFPT_DWORD(1), BIT(16), /* Supported bit */ 1568 BFPT_DWORD(4), 0, /* Settings */ 1569 SNOR_PROTO_1_1_2, 1570 }, 1571 1572 /* Fast Read 1-2-2 */ 1573 { 1574 SNOR_HWCAPS_READ_1_2_2, 1575 BFPT_DWORD(1), BIT(20), /* Supported bit */ 1576 BFPT_DWORD(4), 16, /* Settings */ 1577 SNOR_PROTO_1_2_2, 1578 }, 1579 1580 /* Fast Read 2-2-2 */ 1581 { 1582 SNOR_HWCAPS_READ_2_2_2, 1583 BFPT_DWORD(5), BIT(0), /* Supported bit */ 1584 BFPT_DWORD(6), 16, /* Settings */ 1585 SNOR_PROTO_2_2_2, 1586 }, 1587 1588 /* Fast Read 1-1-4 */ 1589 { 1590 SNOR_HWCAPS_READ_1_1_4, 1591 BFPT_DWORD(1), BIT(22), /* Supported bit */ 1592 BFPT_DWORD(3), 16, /* Settings */ 1593 SNOR_PROTO_1_1_4, 1594 }, 1595 1596 /* Fast Read 1-4-4 */ 1597 { 1598 SNOR_HWCAPS_READ_1_4_4, 1599 BFPT_DWORD(1), BIT(21), /* Supported bit */ 1600 BFPT_DWORD(3), 0, /* Settings */ 1601 SNOR_PROTO_1_4_4, 1602 }, 1603 1604 /* Fast Read 4-4-4 */ 1605 { 1606 SNOR_HWCAPS_READ_4_4_4, 1607 BFPT_DWORD(5), BIT(4), /* Supported bit */ 1608 BFPT_DWORD(7), 16, /* Settings */ 1609 SNOR_PROTO_4_4_4, 1610 }, 1611 }; 1612 1613 struct sfdp_bfpt_erase { 1614 /* 1615 * The half-word at offset <shift> in DWORD <dwoard> encodes the 1616 * op code and erase sector size to be used by Sector Erase commands. 1617 */ 1618 u32 dword; 1619 u32 shift; 1620 }; 1621 1622 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { 1623 /* Erase Type 1 in DWORD8 bits[15:0] */ 1624 {BFPT_DWORD(8), 0}, 1625 1626 /* Erase Type 2 in DWORD8 bits[31:16] */ 1627 {BFPT_DWORD(8), 16}, 1628 1629 /* Erase Type 3 in DWORD9 bits[15:0] */ 1630 {BFPT_DWORD(9), 0}, 1631 1632 /* Erase Type 4 in DWORD9 bits[31:16] */ 1633 {BFPT_DWORD(9), 16}, 1634 }; 1635 1636 static int spi_nor_hwcaps_read2cmd(u32 hwcaps); 1637 1638 /** 1639 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. 1640 * @nor: pointer to a 'struct spi_nor' 1641 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing 1642 * the Basic Flash Parameter Table length and version 1643 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1644 * filled 1645 * 1646 * The Basic Flash Parameter Table is the main and only mandatory table as 1647 * defined by the SFDP (JESD216) specification. 1648 * It provides us with the total size (memory density) of the data array and 1649 * the number of address bytes for Fast Read, Page Program and Sector Erase 1650 * commands. 1651 * For Fast READ commands, it also gives the number of mode clock cycles and 1652 * wait states (regrouped in the number of dummy clock cycles) for each 1653 * supported instruction op code. 1654 * For Page Program, the page size is now available since JESD216 rev A, however 1655 * the supported instruction op codes are still not provided. 1656 * For Sector Erase commands, this table stores the supported instruction op 1657 * codes and the associated sector sizes. 1658 * Finally, the Quad Enable Requirements (QER) are also available since JESD216 1659 * rev A. The QER bits encode the manufacturer dependent procedure to be 1660 * executed to set the Quad Enable (QE) bit in some internal register of the 1661 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before 1662 * sending any Quad SPI command to the memory. Actually, setting the QE bit 1663 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2 1664 * and IO3 hence enabling 4 (Quad) I/O lines. 1665 * 1666 * Return: 0 on success, -errno otherwise. 1667 */ 1668 static int spi_nor_parse_bfpt(struct spi_nor *nor, 1669 const struct sfdp_parameter_header *bfpt_header, 1670 struct spi_nor_flash_parameter *params) 1671 { 1672 struct mtd_info *mtd = &nor->mtd; 1673 struct sfdp_bfpt bfpt; 1674 size_t len; 1675 int i, cmd, err; 1676 u32 addr; 1677 u16 half; 1678 1679 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ 1680 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) 1681 return -EINVAL; 1682 1683 /* Read the Basic Flash Parameter Table. */ 1684 len = min_t(size_t, sizeof(bfpt), 1685 bfpt_header->length * sizeof(u32)); 1686 addr = SFDP_PARAM_HEADER_PTP(bfpt_header); 1687 memset(&bfpt, 0, sizeof(bfpt)); 1688 err = spi_nor_read_sfdp(nor, addr, len, &bfpt); 1689 if (err < 0) 1690 return err; 1691 1692 /* Fix endianness of the BFPT DWORDs. */ 1693 for (i = 0; i < BFPT_DWORD_MAX; i++) 1694 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]); 1695 1696 /* Number of address bytes. */ 1697 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { 1698 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: 1699 nor->addr_width = 3; 1700 break; 1701 1702 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: 1703 nor->addr_width = 4; 1704 break; 1705 1706 default: 1707 break; 1708 } 1709 1710 /* Flash Memory Density (in bits). */ 1711 params->size = bfpt.dwords[BFPT_DWORD(2)]; 1712 if (params->size & BIT(31)) { 1713 params->size &= ~BIT(31); 1714 1715 /* 1716 * Prevent overflows on params->size. Anyway, a NOR of 2^64 1717 * bits is unlikely to exist so this error probably means 1718 * the BFPT we are reading is corrupted/wrong. 1719 */ 1720 if (params->size > 63) 1721 return -EINVAL; 1722 1723 params->size = 1ULL << params->size; 1724 } else { 1725 params->size++; 1726 } 1727 params->size >>= 3; /* Convert to bytes. */ 1728 1729 /* Fast Read settings. */ 1730 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { 1731 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i]; 1732 struct spi_nor_read_command *read; 1733 1734 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { 1735 params->hwcaps.mask &= ~rd->hwcaps; 1736 continue; 1737 } 1738 1739 params->hwcaps.mask |= rd->hwcaps; 1740 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps); 1741 read = ¶ms->reads[cmd]; 1742 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; 1743 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); 1744 } 1745 1746 /* Sector Erase settings. */ 1747 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { 1748 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i]; 1749 u32 erasesize; 1750 u8 opcode; 1751 1752 half = bfpt.dwords[er->dword] >> er->shift; 1753 erasesize = half & 0xff; 1754 1755 /* erasesize == 0 means this Erase Type is not supported. */ 1756 if (!erasesize) 1757 continue; 1758 1759 erasesize = 1U << erasesize; 1760 opcode = (half >> 8) & 0xff; 1761 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 1762 if (erasesize == SZ_4K) { 1763 nor->erase_opcode = opcode; 1764 mtd->erasesize = erasesize; 1765 break; 1766 } 1767 #endif 1768 if (!mtd->erasesize || mtd->erasesize < erasesize) { 1769 nor->erase_opcode = opcode; 1770 mtd->erasesize = erasesize; 1771 } 1772 } 1773 1774 /* Stop here if not JESD216 rev A or later. */ 1775 if (bfpt_header->length < BFPT_DWORD_MAX) 1776 return 0; 1777 1778 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ 1779 params->page_size = bfpt.dwords[BFPT_DWORD(11)]; 1780 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK; 1781 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT; 1782 params->page_size = 1U << params->page_size; 1783 1784 /* Quad Enable Requirements. */ 1785 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { 1786 case BFPT_DWORD15_QER_NONE: 1787 params->quad_enable = NULL; 1788 break; 1789 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1790 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: 1791 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: 1792 params->quad_enable = spansion_no_read_cr_quad_enable; 1793 break; 1794 #endif 1795 #ifdef CONFIG_SPI_FLASH_MACRONIX 1796 case BFPT_DWORD15_QER_SR1_BIT6: 1797 params->quad_enable = macronix_quad_enable; 1798 break; 1799 #endif 1800 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1801 case BFPT_DWORD15_QER_SR2_BIT1: 1802 params->quad_enable = spansion_read_cr_quad_enable; 1803 break; 1804 #endif 1805 default: 1806 return -EINVAL; 1807 } 1808 1809 return 0; 1810 } 1811 1812 /** 1813 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. 1814 * @nor: pointer to a 'struct spi_nor' 1815 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1816 * filled 1817 * 1818 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216 1819 * specification. This is a standard which tends to supported by almost all 1820 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at 1821 * runtime the main parameters needed to perform basic SPI flash operations such 1822 * as Fast Read, Page Program or Sector Erase commands. 1823 * 1824 * Return: 0 on success, -errno otherwise. 1825 */ 1826 static int spi_nor_parse_sfdp(struct spi_nor *nor, 1827 struct spi_nor_flash_parameter *params) 1828 { 1829 const struct sfdp_parameter_header *param_header, *bfpt_header; 1830 struct sfdp_parameter_header *param_headers = NULL; 1831 struct sfdp_header header; 1832 size_t psize; 1833 int i, err; 1834 1835 /* Get the SFDP header. */ 1836 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); 1837 if (err < 0) 1838 return err; 1839 1840 /* Check the SFDP header version. */ 1841 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE || 1842 header.major != SFDP_JESD216_MAJOR) 1843 return -EINVAL; 1844 1845 /* 1846 * Verify that the first and only mandatory parameter header is a 1847 * Basic Flash Parameter Table header as specified in JESD216. 1848 */ 1849 bfpt_header = &header.bfpt_header; 1850 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID || 1851 bfpt_header->major != SFDP_JESD216_MAJOR) 1852 return -EINVAL; 1853 1854 /* 1855 * Allocate memory then read all parameter headers with a single 1856 * Read SFDP command. These parameter headers will actually be parsed 1857 * twice: a first time to get the latest revision of the basic flash 1858 * parameter table, then a second time to handle the supported optional 1859 * tables. 1860 * Hence we read the parameter headers once for all to reduce the 1861 * processing time. Also we use kmalloc() instead of devm_kmalloc() 1862 * because we don't need to keep these parameter headers: the allocated 1863 * memory is always released with kfree() before exiting this function. 1864 */ 1865 if (header.nph) { 1866 psize = header.nph * sizeof(*param_headers); 1867 1868 param_headers = kmalloc(psize, GFP_KERNEL); 1869 if (!param_headers) 1870 return -ENOMEM; 1871 1872 err = spi_nor_read_sfdp(nor, sizeof(header), 1873 psize, param_headers); 1874 if (err < 0) { 1875 dev_err(dev, "failed to read SFDP parameter headers\n"); 1876 goto exit; 1877 } 1878 } 1879 1880 /* 1881 * Check other parameter headers to get the latest revision of 1882 * the basic flash parameter table. 1883 */ 1884 for (i = 0; i < header.nph; i++) { 1885 param_header = ¶m_headers[i]; 1886 1887 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID && 1888 param_header->major == SFDP_JESD216_MAJOR && 1889 (param_header->minor > bfpt_header->minor || 1890 (param_header->minor == bfpt_header->minor && 1891 param_header->length > bfpt_header->length))) 1892 bfpt_header = param_header; 1893 } 1894 1895 err = spi_nor_parse_bfpt(nor, bfpt_header, params); 1896 if (err) 1897 goto exit; 1898 1899 /* Parse other parameter headers. */ 1900 for (i = 0; i < header.nph; i++) { 1901 param_header = ¶m_headers[i]; 1902 1903 switch (SFDP_PARAM_HEADER_ID(param_header)) { 1904 case SFDP_SECTOR_MAP_ID: 1905 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n"); 1906 break; 1907 1908 default: 1909 break; 1910 } 1911 1912 if (err) 1913 goto exit; 1914 } 1915 1916 exit: 1917 kfree(param_headers); 1918 return err; 1919 } 1920 #else 1921 static int spi_nor_parse_sfdp(struct spi_nor *nor, 1922 struct spi_nor_flash_parameter *params) 1923 { 1924 return -EINVAL; 1925 } 1926 #endif /* SPI_FLASH_SFDP_SUPPORT */ 1927 1928 static int spi_nor_init_params(struct spi_nor *nor, 1929 const struct flash_info *info, 1930 struct spi_nor_flash_parameter *params) 1931 { 1932 /* Set legacy flash parameters as default. */ 1933 memset(params, 0, sizeof(*params)); 1934 1935 /* Set SPI NOR sizes. */ 1936 params->size = info->sector_size * info->n_sectors; 1937 params->page_size = info->page_size; 1938 1939 /* (Fast) Read settings. */ 1940 params->hwcaps.mask |= SNOR_HWCAPS_READ; 1941 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 1942 0, 0, SPINOR_OP_READ, 1943 SNOR_PROTO_1_1_1); 1944 1945 if (!(info->flags & SPI_NOR_NO_FR)) { 1946 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 1947 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 1948 0, 8, SPINOR_OP_READ_FAST, 1949 SNOR_PROTO_1_1_1); 1950 } 1951 1952 if (info->flags & SPI_NOR_DUAL_READ) { 1953 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 1954 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 1955 0, 8, SPINOR_OP_READ_1_1_2, 1956 SNOR_PROTO_1_1_2); 1957 } 1958 1959 if (info->flags & SPI_NOR_QUAD_READ) { 1960 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 1961 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 1962 0, 8, SPINOR_OP_READ_1_1_4, 1963 SNOR_PROTO_1_1_4); 1964 } 1965 1966 /* Page Program settings. */ 1967 params->hwcaps.mask |= SNOR_HWCAPS_PP; 1968 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 1969 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 1970 1971 if (info->flags & SPI_NOR_QUAD_READ) { 1972 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 1973 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 1974 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 1975 } 1976 1977 /* Select the procedure to set the Quad Enable bit. */ 1978 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | 1979 SNOR_HWCAPS_PP_QUAD)) { 1980 switch (JEDEC_MFR(info)) { 1981 #ifdef CONFIG_SPI_FLASH_MACRONIX 1982 case SNOR_MFR_MACRONIX: 1983 params->quad_enable = macronix_quad_enable; 1984 break; 1985 #endif 1986 case SNOR_MFR_ST: 1987 case SNOR_MFR_MICRON: 1988 break; 1989 1990 default: 1991 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1992 /* Kept only for backward compatibility purpose. */ 1993 params->quad_enable = spansion_read_cr_quad_enable; 1994 #endif 1995 break; 1996 } 1997 } 1998 1999 /* Override the parameters with data read from SFDP tables. */ 2000 nor->addr_width = 0; 2001 nor->mtd.erasesize = 0; 2002 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && 2003 !(info->flags & SPI_NOR_SKIP_SFDP)) { 2004 struct spi_nor_flash_parameter sfdp_params; 2005 2006 memcpy(&sfdp_params, params, sizeof(sfdp_params)); 2007 if (spi_nor_parse_sfdp(nor, &sfdp_params)) { 2008 nor->addr_width = 0; 2009 nor->mtd.erasesize = 0; 2010 } else { 2011 memcpy(params, &sfdp_params, sizeof(*params)); 2012 } 2013 } 2014 2015 return 0; 2016 } 2017 2018 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2019 { 2020 size_t i; 2021 2022 for (i = 0; i < size; i++) 2023 if (table[i][0] == (int)hwcaps) 2024 return table[i][1]; 2025 2026 return -EINVAL; 2027 } 2028 2029 static int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2030 { 2031 static const int hwcaps_read2cmd[][2] = { 2032 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2033 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2034 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2035 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2036 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2037 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2038 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2039 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2040 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2041 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2042 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2043 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2044 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2045 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2046 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2047 }; 2048 2049 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2050 ARRAY_SIZE(hwcaps_read2cmd)); 2051 } 2052 2053 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2054 { 2055 static const int hwcaps_pp2cmd[][2] = { 2056 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2057 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2058 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2059 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2060 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2061 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2062 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2063 }; 2064 2065 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2066 ARRAY_SIZE(hwcaps_pp2cmd)); 2067 } 2068 2069 static int spi_nor_select_read(struct spi_nor *nor, 2070 const struct spi_nor_flash_parameter *params, 2071 u32 shared_hwcaps) 2072 { 2073 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2074 const struct spi_nor_read_command *read; 2075 2076 if (best_match < 0) 2077 return -EINVAL; 2078 2079 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2080 if (cmd < 0) 2081 return -EINVAL; 2082 2083 read = ¶ms->reads[cmd]; 2084 nor->read_opcode = read->opcode; 2085 nor->read_proto = read->proto; 2086 2087 /* 2088 * In the spi-nor framework, we don't need to make the difference 2089 * between mode clock cycles and wait state clock cycles. 2090 * Indeed, the value of the mode clock cycles is used by a QSPI 2091 * flash memory to know whether it should enter or leave its 0-4-4 2092 * (Continuous Read / XIP) mode. 2093 * eXecution In Place is out of the scope of the mtd sub-system. 2094 * Hence we choose to merge both mode and wait state clock cycles 2095 * into the so called dummy clock cycles. 2096 */ 2097 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2098 return 0; 2099 } 2100 2101 static int spi_nor_select_pp(struct spi_nor *nor, 2102 const struct spi_nor_flash_parameter *params, 2103 u32 shared_hwcaps) 2104 { 2105 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2106 const struct spi_nor_pp_command *pp; 2107 2108 if (best_match < 0) 2109 return -EINVAL; 2110 2111 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2112 if (cmd < 0) 2113 return -EINVAL; 2114 2115 pp = ¶ms->page_programs[cmd]; 2116 nor->program_opcode = pp->opcode; 2117 nor->write_proto = pp->proto; 2118 return 0; 2119 } 2120 2121 static int spi_nor_select_erase(struct spi_nor *nor, 2122 const struct flash_info *info) 2123 { 2124 struct mtd_info *mtd = &nor->mtd; 2125 2126 /* Do nothing if already configured from SFDP. */ 2127 if (mtd->erasesize) 2128 return 0; 2129 2130 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 2131 /* prefer "small sector" erase if possible */ 2132 if (info->flags & SECT_4K) { 2133 nor->erase_opcode = SPINOR_OP_BE_4K; 2134 mtd->erasesize = 4096; 2135 } else if (info->flags & SECT_4K_PMC) { 2136 nor->erase_opcode = SPINOR_OP_BE_4K_PMC; 2137 mtd->erasesize = 4096; 2138 } else 2139 #endif 2140 { 2141 nor->erase_opcode = SPINOR_OP_SE; 2142 mtd->erasesize = info->sector_size; 2143 } 2144 return 0; 2145 } 2146 2147 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, 2148 const struct spi_nor_flash_parameter *params, 2149 const struct spi_nor_hwcaps *hwcaps) 2150 { 2151 u32 ignored_mask, shared_mask; 2152 bool enable_quad_io; 2153 int err; 2154 2155 /* 2156 * Keep only the hardware capabilities supported by both the SPI 2157 * controller and the SPI flash memory. 2158 */ 2159 shared_mask = hwcaps->mask & params->hwcaps.mask; 2160 2161 /* SPI n-n-n protocols are not supported yet. */ 2162 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | 2163 SNOR_HWCAPS_READ_4_4_4 | 2164 SNOR_HWCAPS_READ_8_8_8 | 2165 SNOR_HWCAPS_PP_4_4_4 | 2166 SNOR_HWCAPS_PP_8_8_8); 2167 if (shared_mask & ignored_mask) { 2168 dev_dbg(nor->dev, 2169 "SPI n-n-n protocols are not supported yet.\n"); 2170 shared_mask &= ~ignored_mask; 2171 } 2172 2173 /* Select the (Fast) Read command. */ 2174 err = spi_nor_select_read(nor, params, shared_mask); 2175 if (err) { 2176 dev_dbg(nor->dev, 2177 "can't select read settings supported by both the SPI controller and memory.\n"); 2178 return err; 2179 } 2180 2181 /* Select the Page Program command. */ 2182 err = spi_nor_select_pp(nor, params, shared_mask); 2183 if (err) { 2184 dev_dbg(nor->dev, 2185 "can't select write settings supported by both the SPI controller and memory.\n"); 2186 return err; 2187 } 2188 2189 /* Select the Sector Erase command. */ 2190 err = spi_nor_select_erase(nor, info); 2191 if (err) { 2192 dev_dbg(nor->dev, 2193 "can't select erase settings supported by both the SPI controller and memory.\n"); 2194 return err; 2195 } 2196 2197 /* Enable Quad I/O if needed. */ 2198 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 || 2199 spi_nor_get_protocol_width(nor->write_proto) == 4); 2200 if (enable_quad_io && params->quad_enable) 2201 nor->quad_enable = params->quad_enable; 2202 else 2203 nor->quad_enable = NULL; 2204 2205 return 0; 2206 } 2207 2208 static int spi_nor_init(struct spi_nor *nor) 2209 { 2210 int err; 2211 2212 /* 2213 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up 2214 * with the software protection bits set 2215 */ 2216 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || 2217 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || 2218 JEDEC_MFR(nor->info) == SNOR_MFR_SST || 2219 nor->info->flags & SPI_NOR_HAS_LOCK) { 2220 write_enable(nor); 2221 write_sr(nor, 0); 2222 spi_nor_wait_till_ready(nor); 2223 } 2224 2225 if (nor->quad_enable) { 2226 err = nor->quad_enable(nor); 2227 if (err) { 2228 dev_dbg(nor->dev, "quad mode not supported\n"); 2229 return err; 2230 } 2231 } 2232 2233 if (nor->addr_width == 4 && 2234 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION)) { 2235 /* 2236 * If the RESET# pin isn't hooked up properly, or the system 2237 * otherwise doesn't perform a reset command in the boot 2238 * sequence, it's impossible to 100% protect against unexpected 2239 * reboots (e.g., crashes). Warn the user (or hopefully, system 2240 * designer) that this is bad. 2241 */ 2242 if (nor->flags & SNOR_F_BROKEN_RESET) 2243 printf("enabling reset hack; may not recover from unexpected reboots\n"); 2244 set_4byte(nor, nor->info, 1); 2245 } 2246 2247 return 0; 2248 } 2249 2250 int spi_nor_scan(struct spi_nor *nor) 2251 { 2252 struct spi_nor_flash_parameter params; 2253 const struct flash_info *info = NULL; 2254 struct mtd_info *mtd = &nor->mtd; 2255 struct spi_nor_hwcaps hwcaps = { 2256 .mask = SNOR_HWCAPS_READ | 2257 SNOR_HWCAPS_READ_FAST | 2258 SNOR_HWCAPS_PP, 2259 }; 2260 struct spi_slave *spi = nor->spi; 2261 int ret; 2262 2263 /* Reset SPI protocol for all commands. */ 2264 nor->reg_proto = SNOR_PROTO_1_1_1; 2265 nor->read_proto = SNOR_PROTO_1_1_1; 2266 nor->write_proto = SNOR_PROTO_1_1_1; 2267 nor->read = spi_nor_read_data; 2268 nor->write = spi_nor_write_data; 2269 nor->read_reg = spi_nor_read_reg; 2270 nor->write_reg = spi_nor_write_reg; 2271 2272 if (spi->mode & SPI_RX_QUAD) { 2273 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2274 2275 if (spi->mode & SPI_TX_QUAD) 2276 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 | 2277 SNOR_HWCAPS_PP_1_1_4 | 2278 SNOR_HWCAPS_PP_1_4_4); 2279 } else if (spi->mode & SPI_RX_DUAL) { 2280 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2281 2282 if (spi->mode & SPI_TX_DUAL) 2283 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2; 2284 } 2285 2286 info = spi_nor_read_id(nor); 2287 if (IS_ERR_OR_NULL(info)) 2288 return -ENOENT; 2289 /* Parse the Serial Flash Discoverable Parameters table. */ 2290 ret = spi_nor_init_params(nor, info, ¶ms); 2291 if (ret) 2292 return ret; 2293 2294 if (!mtd->name) 2295 mtd->name = info->name; 2296 mtd->priv = nor; 2297 mtd->type = MTD_NORFLASH; 2298 mtd->writesize = 1; 2299 mtd->flags = MTD_CAP_NORFLASH; 2300 mtd->size = params.size; 2301 mtd->_erase = spi_nor_erase; 2302 mtd->_read = spi_nor_read; 2303 2304 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 2305 /* NOR protection support for STmicro/Micron chips and similar */ 2306 if (JEDEC_MFR(info) == SNOR_MFR_ST || 2307 JEDEC_MFR(info) == SNOR_MFR_MICRON || 2308 JEDEC_MFR(info) == SNOR_MFR_SST || 2309 info->flags & SPI_NOR_HAS_LOCK) { 2310 nor->flash_lock = stm_lock; 2311 nor->flash_unlock = stm_unlock; 2312 nor->flash_is_locked = stm_is_locked; 2313 } 2314 #endif 2315 2316 #ifdef CONFIG_SPI_FLASH_SST 2317 /* sst nor chips use AAI word program */ 2318 if (info->flags & SST_WRITE) 2319 mtd->_write = sst_write; 2320 else 2321 #endif 2322 mtd->_write = spi_nor_write; 2323 2324 if (info->flags & USE_FSR) 2325 nor->flags |= SNOR_F_USE_FSR; 2326 if (info->flags & SPI_NOR_HAS_TB) 2327 nor->flags |= SNOR_F_HAS_SR_TB; 2328 if (info->flags & NO_CHIP_ERASE) 2329 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2330 if (info->flags & USE_CLSR) 2331 nor->flags |= SNOR_F_USE_CLSR; 2332 2333 if (info->flags & SPI_NOR_NO_ERASE) 2334 mtd->flags |= MTD_NO_ERASE; 2335 2336 nor->page_size = params.page_size; 2337 mtd->writebufsize = nor->page_size; 2338 2339 /* Some devices cannot do fast-read, no matter what DT tells us */ 2340 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW)) 2341 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2342 2343 /* 2344 * Configure the SPI memory: 2345 * - select op codes for (Fast) Read, Page Program and Sector Erase. 2346 * - set the number of dummy cycles (mode cycles + wait states). 2347 * - set the SPI protocols for register and memory accesses. 2348 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). 2349 */ 2350 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); 2351 if (ret) 2352 return ret; 2353 2354 if (nor->addr_width) { 2355 /* already configured from SFDP */ 2356 } else if (info->addr_width) { 2357 nor->addr_width = info->addr_width; 2358 } else if (mtd->size > SZ_16M) { 2359 #ifndef CONFIG_SPI_FLASH_BAR 2360 /* enable 4-byte addressing if the device exceeds 16MiB */ 2361 nor->addr_width = 4; 2362 spi_nor_set_4byte_opcodes(nor, info); 2363 #else 2364 /* Configure the BAR - discover bank cmds and read current bank */ 2365 nor->addr_width = 3; 2366 ret = read_bar(nor, info); 2367 if (ret < 0) 2368 return ret; 2369 #endif 2370 } else { 2371 nor->addr_width = 3; 2372 } 2373 2374 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 2375 dev_dbg(dev, "address width is too large: %u\n", 2376 nor->addr_width); 2377 return -EINVAL; 2378 } 2379 2380 /* Send all the required SPI flash commands to initialize device */ 2381 nor->info = info; 2382 ret = spi_nor_init(nor); 2383 if (ret) 2384 return ret; 2385 2386 nor->name = mtd->name; 2387 nor->size = mtd->size; 2388 nor->erase_size = mtd->erasesize; 2389 nor->sector_size = mtd->erasesize; 2390 2391 #ifndef CONFIG_SPL_BUILD 2392 printf("SF: Detected %s with page size ", nor->name); 2393 print_size(nor->page_size, ", erase size "); 2394 print_size(nor->erase_size, ", total "); 2395 print_size(nor->size, ""); 2396 puts("\n"); 2397 #endif 2398 2399 return 0; 2400 } 2401 2402 /* U-Boot specific functions, need to extend MTD to support these */ 2403 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor) 2404 { 2405 int sr = read_sr(nor); 2406 2407 if (sr < 0) 2408 return sr; 2409 2410 return (sr >> 2) & 7; 2411 } 2412