1 /* 2 * Basic I2C functions 3 * 4 * Copyright (c) 2004 Texas Instruments 5 * 6 * This package is free software; you can redistribute it and/or 7 * modify it under the terms of the license found in the file 8 * named COPYING that should have accompanied this file. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments 15 * 16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de 17 * Rewritten to fit into the current U-Boot framework 18 * 19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com 20 * 21 */ 22 23 #include <common.h> 24 25 #include <asm/arch/i2c.h> 26 #include <asm/io.h> 27 28 #include "omap24xx_i2c.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define I2C_STAT_TIMEO (1 << 31) 33 #define I2C_TIMEOUT 10 34 35 static u32 wait_for_bb(void); 36 static u32 wait_for_status_mask(u16 mask); 37 static void flush_fifo(void); 38 39 /* 40 * For SPL boot some boards need i2c before SDRAM is initialised so force 41 * variables to live in SRAM 42 */ 43 static struct i2c __attribute__((section (".data"))) *i2c_base = 44 (struct i2c *)I2C_DEFAULT_BASE; 45 static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = 46 { [0 ... (I2C_BUS_MAX-1)] = 0 }; 47 static unsigned int __attribute__((section (".data"))) current_bus = 0; 48 49 void i2c_init(int speed, int slaveadd) 50 { 51 int psc, fsscll, fssclh; 52 int hsscll = 0, hssclh = 0; 53 u32 scll, sclh; 54 55 /* Only handle standard, fast and high speeds */ 56 if ((speed != OMAP_I2C_STANDARD) && 57 (speed != OMAP_I2C_FAST_MODE) && 58 (speed != OMAP_I2C_HIGH_SPEED)) { 59 printf("Error : I2C unsupported speed %d\n", speed); 60 return; 61 } 62 63 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; 64 psc -= 1; 65 if (psc < I2C_PSC_MIN) { 66 printf("Error : I2C unsupported prescalar %d\n", psc); 67 return; 68 } 69 70 if (speed == OMAP_I2C_HIGH_SPEED) { 71 /* High speed */ 72 73 /* For first phase of HS mode */ 74 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / 75 (2 * OMAP_I2C_FAST_MODE); 76 77 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; 78 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; 79 if (((fsscll < 0) || (fssclh < 0)) || 80 ((fsscll > 255) || (fssclh > 255))) { 81 puts("Error : I2C initializing first phase clock\n"); 82 return; 83 } 84 85 /* For second phase of HS mode */ 86 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 87 88 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; 89 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; 90 if (((fsscll < 0) || (fssclh < 0)) || 91 ((fsscll > 255) || (fssclh > 255))) { 92 puts("Error : I2C initializing second phase clock\n"); 93 return; 94 } 95 96 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; 97 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; 98 99 } else { 100 /* Standard and fast speed */ 101 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 102 103 fsscll -= I2C_FASTSPEED_SCLL_TRIM; 104 fssclh -= I2C_FASTSPEED_SCLH_TRIM; 105 if (((fsscll < 0) || (fssclh < 0)) || 106 ((fsscll > 255) || (fssclh > 255))) { 107 puts("Error : I2C initializing clock\n"); 108 return; 109 } 110 111 scll = (unsigned int)fsscll; 112 sclh = (unsigned int)fssclh; 113 } 114 115 if (gd->flags & GD_FLG_RELOC) 116 bus_initialized[current_bus] = 1; 117 118 if (readw(&i2c_base->con) & I2C_CON_EN) { 119 writew(0, &i2c_base->con); 120 udelay(50000); 121 } 122 123 writew(psc, &i2c_base->psc); 124 writew(scll, &i2c_base->scll); 125 writew(sclh, &i2c_base->sclh); 126 127 /* own address */ 128 writew(slaveadd, &i2c_base->oa); 129 writew(I2C_CON_EN, &i2c_base->con); 130 131 /* have to enable intrrupts or OMAP i2c module doesn't work */ 132 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | 133 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); 134 udelay(1000); 135 flush_fifo(); 136 writew(0xFFFF, &i2c_base->stat); 137 writew(0, &i2c_base->cnt); 138 } 139 140 static void flush_fifo(void) 141 { u16 stat; 142 143 /* note: if you try and read data when its not there or ready 144 * you get a bus error 145 */ 146 while (1) { 147 stat = readw(&i2c_base->stat); 148 if (stat == I2C_STAT_RRDY) { 149 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 150 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) 151 readb(&i2c_base->data); 152 #else 153 readw(&i2c_base->data); 154 #endif 155 writew(I2C_STAT_RRDY, &i2c_base->stat); 156 udelay(1000); 157 } else 158 break; 159 } 160 } 161 162 int i2c_probe(uchar chip) 163 { 164 u32 status; 165 int res = 1; /* default = fail */ 166 167 if (chip == readw(&i2c_base->oa)) 168 return res; 169 170 /* wait until bus not busy */ 171 status = wait_for_bb(); 172 /* exit on BUS busy */ 173 if (status & I2C_STAT_TIMEO) 174 return res; 175 176 /* try to write one byte */ 177 writew(1, &i2c_base->cnt); 178 /* set slave address */ 179 writew(chip, &i2c_base->sa); 180 /* stop bit needed here */ 181 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT 182 | I2C_CON_STP, &i2c_base->con); 183 /* enough delay for the NACK bit set */ 184 udelay(9000); 185 186 if (!(readw(&i2c_base->stat) & I2C_STAT_NACK)) { 187 res = 0; /* success case */ 188 flush_fifo(); 189 writew(0xFFFF, &i2c_base->stat); 190 } else { 191 /* failure, clear sources*/ 192 writew(0xFFFF, &i2c_base->stat); 193 /* finish up xfer */ 194 writew(readw(&i2c_base->con) | I2C_CON_STP, &i2c_base->con); 195 status = wait_for_bb(); 196 /* exit on BUS busy */ 197 if (status & I2C_STAT_TIMEO) 198 return res; 199 } 200 flush_fifo(); 201 /* don't allow any more data in... we don't want it. */ 202 writew(0, &i2c_base->cnt); 203 writew(0xFFFF, &i2c_base->stat); 204 return res; 205 } 206 207 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 208 { 209 int i2c_error = 0, i; 210 u32 status; 211 212 if ((alen > 2) || (alen < 0)) 213 return 1; 214 215 if (alen < 2) { 216 if (addr + len > 256) 217 return 1; 218 } else if (addr + len > 0xFFFF) { 219 return 1; 220 } 221 222 /* wait until bus not busy */ 223 status = wait_for_bb(); 224 225 /* exit on BUS busy */ 226 if (status & I2C_STAT_TIMEO) 227 return 1; 228 229 writew((alen & 0xFF), &i2c_base->cnt); 230 /* set slave address */ 231 writew(chip, &i2c_base->sa); 232 /* Clear the Tx & Rx FIFOs */ 233 writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR | 234 I2C_TXFIFO_CLEAR), &i2c_base->buf); 235 /* no stop bit needed here */ 236 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | 237 I2C_CON_STT, &i2c_base->con); 238 239 /* wait for Transmit ready condition */ 240 status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK); 241 242 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) 243 i2c_error = 1; 244 245 if (!i2c_error) { 246 if (status & I2C_STAT_XRDY) { 247 switch (alen) { 248 case 2: 249 /* Send address MSByte */ 250 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 251 defined(CONFIG_AM33XX) 252 writew(((addr >> 8) & 0xFF), &i2c_base->data); 253 254 /* Clearing XRDY event */ 255 writew((status & I2C_STAT_XRDY), 256 &i2c_base->stat); 257 /* wait for Transmit ready condition */ 258 status = wait_for_status_mask(I2C_STAT_XRDY | 259 I2C_STAT_NACK); 260 261 if (status & (I2C_STAT_NACK | 262 I2C_STAT_TIMEO)) { 263 i2c_error = 1; 264 break; 265 } 266 #endif 267 case 1: 268 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 269 defined(CONFIG_AM33XX) 270 /* Send address LSByte */ 271 writew((addr & 0xFF), &i2c_base->data); 272 #else 273 /* Send address Short word */ 274 writew((addr & 0xFFFF), &i2c_base->data); 275 #endif 276 /* Clearing XRDY event */ 277 writew((status & I2C_STAT_XRDY), 278 &i2c_base->stat); 279 /*wait for Transmit ready condition */ 280 status = wait_for_status_mask(I2C_STAT_ARDY | 281 I2C_STAT_NACK); 282 283 if (status & (I2C_STAT_NACK | 284 I2C_STAT_TIMEO)) { 285 i2c_error = 1; 286 break; 287 } 288 } 289 } else 290 i2c_error = 1; 291 } 292 293 /* Wait for ARDY to set */ 294 status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK 295 | I2C_STAT_AL); 296 297 if (!i2c_error) { 298 /* set slave address */ 299 writew(chip, &i2c_base->sa); 300 writew((len & 0xFF), &i2c_base->cnt); 301 /* Clear the Tx & Rx FIFOs */ 302 writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR | 303 I2C_TXFIFO_CLEAR), &i2c_base->buf); 304 /* need stop bit here */ 305 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, 306 &i2c_base->con); 307 308 for (i = 0; i < len; i++) { 309 /* wait for Receive condition */ 310 status = wait_for_status_mask(I2C_STAT_RRDY | 311 I2C_STAT_NACK); 312 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) { 313 i2c_error = 1; 314 break; 315 } 316 317 if (status & I2C_STAT_RRDY) { 318 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 319 defined(CONFIG_AM33XX) 320 buffer[i] = readb(&i2c_base->data); 321 #else 322 *((u16 *)&buffer[i]) = 323 readw(&i2c_base->data) & 0xFFFF; 324 i++; 325 #endif 326 writew((status & I2C_STAT_RRDY), 327 &i2c_base->stat); 328 udelay(1000); 329 } else { 330 i2c_error = 1; 331 } 332 } 333 } 334 335 /* Wait for ARDY to set */ 336 status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK 337 | I2C_STAT_AL); 338 339 if (i2c_error) { 340 writew(0, &i2c_base->con); 341 return 1; 342 } 343 344 writew(I2C_CON_EN, &i2c_base->con); 345 346 while (readw(&i2c_base->stat) 347 || (readw(&i2c_base->con) & I2C_CON_MST)) { 348 udelay(10000); 349 writew(0xFFFF, &i2c_base->stat); 350 } 351 352 writew(I2C_CON_EN, &i2c_base->con); 353 flush_fifo(); 354 writew(0xFFFF, &i2c_base->stat); 355 writew(0, &i2c_base->cnt); 356 357 return 0; 358 } 359 360 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 361 { 362 363 int i, i2c_error = 0; 364 u32 status; 365 u16 writelen; 366 367 if (alen > 2) 368 return 1; 369 370 if (alen < 2) { 371 if (addr + len > 256) 372 return 1; 373 } else if (addr + len > 0xFFFF) { 374 return 1; 375 } 376 377 /* wait until bus not busy */ 378 status = wait_for_bb(); 379 380 /* exiting on BUS busy */ 381 if (status & I2C_STAT_TIMEO) 382 return 1; 383 384 writelen = (len & 0xFFFF) + alen; 385 386 /* two bytes */ 387 writew((writelen & 0xFFFF), &i2c_base->cnt); 388 /* Clear the Tx & Rx FIFOs */ 389 writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR | 390 I2C_TXFIFO_CLEAR), &i2c_base->buf); 391 /* set slave address */ 392 writew(chip, &i2c_base->sa); 393 /* stop bit needed here */ 394 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 395 I2C_CON_STP, &i2c_base->con); 396 397 /* wait for Transmit ready condition */ 398 status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK); 399 400 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) 401 i2c_error = 1; 402 403 if (!i2c_error) { 404 if (status & I2C_STAT_XRDY) { 405 switch (alen) { 406 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 407 defined(CONFIG_AM33XX) 408 case 2: 409 /* send out MSB byte */ 410 writeb(((addr >> 8) & 0xFF), &i2c_base->data); 411 #else 412 writeb((addr & 0xFFFF), &i2c_base->data); 413 break; 414 #endif 415 /* Clearing XRDY event */ 416 writew((status & I2C_STAT_XRDY), 417 &i2c_base->stat); 418 /*waiting for Transmit ready * condition */ 419 status = wait_for_status_mask(I2C_STAT_XRDY | 420 I2C_STAT_NACK); 421 422 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) { 423 i2c_error = 1; 424 break; 425 } 426 case 1: 427 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 428 defined(CONFIG_AM33XX) 429 /* send out MSB byte */ 430 writeb((addr & 0xFF), &i2c_base->data); 431 #else 432 writew(((buffer[0] << 8) | (addr & 0xFF)), 433 &i2c_base->data); 434 #endif 435 } 436 437 /* Clearing XRDY event */ 438 writew((status & I2C_STAT_XRDY), &i2c_base->stat); 439 } 440 441 /* waiting for Transmit ready condition */ 442 status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK); 443 444 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) 445 i2c_error = 1; 446 447 if (!i2c_error) { 448 for (i = ((alen > 1) ? 0 : 1); i < len; i++) { 449 if (status & I2C_STAT_XRDY) { 450 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 451 defined(CONFIG_AM33XX) 452 writeb((buffer[i] & 0xFF), 453 &i2c_base->data); 454 #else 455 writew((((buffer[i] << 8) | 456 buffer[i + 1]) & 0xFFFF), 457 &i2c_base->data); 458 i++; 459 #endif 460 } else 461 i2c_error = 1; 462 /* Clearing XRDY event */ 463 writew((status & I2C_STAT_XRDY), 464 &i2c_base->stat); 465 /* waiting for XRDY condition */ 466 status = wait_for_status_mask( 467 I2C_STAT_XRDY | 468 I2C_STAT_ARDY | 469 I2C_STAT_NACK); 470 if (status & (I2C_STAT_NACK | 471 I2C_STAT_TIMEO)) { 472 i2c_error = 1; 473 break; 474 } 475 if (status & I2C_STAT_ARDY) 476 break; 477 } 478 } 479 } 480 481 status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK | 482 I2C_STAT_AL); 483 484 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) 485 i2c_error = 1; 486 487 if (i2c_error) { 488 writew(0, &i2c_base->con); 489 return 1; 490 } 491 492 if (!i2c_error) { 493 int eout = 200; 494 495 writew(I2C_CON_EN, &i2c_base->con); 496 while ((status = readw(&i2c_base->stat)) || 497 (readw(&i2c_base->con) & I2C_CON_MST)) { 498 udelay(1000); 499 /* have to read to clear intrrupt */ 500 writew(0xFFFF, &i2c_base->stat); 501 if (--eout == 0) 502 /* better leave with error than hang */ 503 break; 504 } 505 } 506 507 flush_fifo(); 508 writew(0xFFFF, &i2c_base->stat); 509 writew(0, &i2c_base->cnt); 510 return 0; 511 } 512 513 static u32 wait_for_bb(void) 514 { 515 int timeout = I2C_TIMEOUT; 516 u32 stat; 517 518 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { 519 writew(stat, &i2c_base->stat); 520 udelay(1000); 521 } 522 523 if (timeout <= 0) { 524 printf("timed out in wait_for_bb: I2C_STAT=%x\n", 525 readw(&i2c_base->stat)); 526 stat |= I2C_STAT_TIMEO; 527 } 528 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ 529 return stat; 530 } 531 532 static u32 wait_for_status_mask(u16 mask) 533 { 534 u32 status; 535 int timeout = I2C_TIMEOUT; 536 537 do { 538 udelay(1000); 539 status = readw(&i2c_base->stat); 540 } while (!(status & mask) && timeout--); 541 542 if (timeout <= 0) { 543 printf("timed out in wait_for_status_mask: I2C_STAT=%x\n", 544 readw(&i2c_base->stat)); 545 writew(0xFFFF, &i2c_base->stat); 546 status |= I2C_STAT_TIMEO; 547 } 548 return status; 549 } 550 551 int i2c_set_bus_num(unsigned int bus) 552 { 553 if ((bus < 0) || (bus >= I2C_BUS_MAX)) { 554 printf("Bad bus: %d\n", bus); 555 return -1; 556 } 557 558 #if I2C_BUS_MAX == 3 559 if (bus == 2) 560 i2c_base = (struct i2c *)I2C_BASE3; 561 else 562 #endif 563 if (bus == 1) 564 i2c_base = (struct i2c *)I2C_BASE2; 565 else 566 i2c_base = (struct i2c *)I2C_BASE1; 567 568 current_bus = bus; 569 570 if (!bus_initialized[current_bus]) 571 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 572 573 return 0; 574 } 575 576 int i2c_get_bus_num(void) 577 { 578 return (int) current_bus; 579 } 580