1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #include <common.h> 7f1df9364SStefan Roese #include <spl.h> 8f1df9364SStefan Roese #include <asm/io.h> 9f1df9364SStefan Roese #include <asm/arch/cpu.h> 10f1df9364SStefan Roese #include <asm/arch/soc.h> 11f1df9364SStefan Roese 12f1df9364SStefan Roese #include "ddr3_init.h" 13f1df9364SStefan Roese 14f1df9364SStefan Roese /* List of allowed frequency listed in order of enum hws_ddr_freq */ 15f1df9364SStefan Roese u32 freq_val[DDR_FREQ_LIMIT] = { 16f1df9364SStefan Roese 0, /*DDR_FREQ_LOW_FREQ */ 17f1df9364SStefan Roese 400, /*DDR_FREQ_400, */ 18f1df9364SStefan Roese 533, /*DDR_FREQ_533, */ 19f1df9364SStefan Roese 666, /*DDR_FREQ_667, */ 20f1df9364SStefan Roese 800, /*DDR_FREQ_800, */ 21f1df9364SStefan Roese 933, /*DDR_FREQ_933, */ 22f1df9364SStefan Roese 1066, /*DDR_FREQ_1066, */ 23f1df9364SStefan Roese 311, /*DDR_FREQ_311, */ 24f1df9364SStefan Roese 333, /*DDR_FREQ_333, */ 25f1df9364SStefan Roese 467, /*DDR_FREQ_467, */ 26f1df9364SStefan Roese 850, /*DDR_FREQ_850, */ 27f1df9364SStefan Roese 600, /*DDR_FREQ_600 */ 28f1df9364SStefan Roese 300, /*DDR_FREQ_300 */ 29f1df9364SStefan Roese 900, /*DDR_FREQ_900 */ 30f1df9364SStefan Roese 360, /*DDR_FREQ_360 */ 31f1df9364SStefan Roese 1000 /*DDR_FREQ_1000 */ 32f1df9364SStefan Roese }; 33f1df9364SStefan Roese 34f1df9364SStefan Roese /* Table for CL values per frequency for each speed bin index */ 35f1df9364SStefan Roese struct cl_val_per_freq cas_latency_table[] = { 36f1df9364SStefan Roese /* 37f1df9364SStefan Roese * 400M 667M 933M 311M 467M 600M 360 38f1df9364SStefan Roese * 100M 533M 800M 1066M 333M 850M 900 39f1df9364SStefan Roese * 1000 (the order is 100, 400, 533 etc.) 40f1df9364SStefan Roese */ 41f1df9364SStefan Roese /* DDR3-800D */ 42f1df9364SStefan Roese { {6, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} }, 43f1df9364SStefan Roese /* DDR3-800E */ 44f1df9364SStefan Roese { {6, 6, 0, 0, 0, 0, 0, 6, 6, 0, 0, 0, 6, 0, 6, 0} }, 45f1df9364SStefan Roese /* DDR3-1066E */ 46f1df9364SStefan Roese { {6, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 0, 5, 0, 5, 0} }, 47f1df9364SStefan Roese /* DDR3-1066F */ 48f1df9364SStefan Roese { {6, 6, 7, 0, 0, 0, 0, 6, 6, 7, 0, 0, 6, 0, 6, 0} }, 49f1df9364SStefan Roese /* DDR3-1066G */ 50f1df9364SStefan Roese { {6, 6, 8, 0, 0, 0, 0, 6, 6, 8, 0, 0, 6, 0, 6, 0} }, 51f1df9364SStefan Roese /* DDR3-1333F* */ 52f1df9364SStefan Roese { {6, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 53f1df9364SStefan Roese /* DDR3-1333G */ 54f1df9364SStefan Roese { {6, 5, 7, 8, 0, 0, 0, 5, 5, 7, 0, 8, 5, 0, 5, 0} }, 55f1df9364SStefan Roese /* DDR3-1333H */ 56f1df9364SStefan Roese { {6, 6, 8, 9, 0, 0, 0, 6, 6, 8, 0, 9, 6, 0, 6, 0} }, 57f1df9364SStefan Roese /* DDR3-1333J* */ 58f1df9364SStefan Roese { {6, 6, 8, 10, 0, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0} 59f1df9364SStefan Roese /* DDR3-1600G* */}, 60f1df9364SStefan Roese { {6, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 61f1df9364SStefan Roese /* DDR3-1600H */ 62f1df9364SStefan Roese { {6, 5, 6, 8, 9, 0, 0, 5, 5, 6, 0, 8, 5, 0, 5, 0} }, 63f1df9364SStefan Roese /* DDR3-1600J */ 64f1df9364SStefan Roese { {6, 5, 7, 9, 10, 0, 0, 5, 5, 7, 0, 9, 5, 0, 5, 0} }, 65f1df9364SStefan Roese /* DDR3-1600K */ 66f1df9364SStefan Roese { {6, 6, 8, 10, 11, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0 } }, 67f1df9364SStefan Roese /* DDR3-1866J* */ 68f1df9364SStefan Roese { {6, 5, 6, 8, 9, 11, 0, 5, 5, 6, 11, 8, 5, 0, 5, 0} }, 69f1df9364SStefan Roese /* DDR3-1866K */ 70f1df9364SStefan Roese { {6, 5, 7, 8, 10, 11, 0, 5, 5, 7, 11, 8, 5, 11, 5, 11} }, 71f1df9364SStefan Roese /* DDR3-1866L */ 72f1df9364SStefan Roese { {6, 6, 7, 9, 11, 12, 0, 6, 6, 7, 12, 9, 6, 12, 6, 12} }, 73f1df9364SStefan Roese /* DDR3-1866M* */ 74f1df9364SStefan Roese { {6, 6, 8, 10, 11, 13, 0, 6, 6, 8, 13, 10, 6, 13, 6, 13} }, 75f1df9364SStefan Roese /* DDR3-2133K* */ 76f1df9364SStefan Roese { {6, 5, 6, 7, 9, 10, 11, 5, 5, 6, 10, 7, 5, 11, 5, 11} }, 77f1df9364SStefan Roese /* DDR3-2133L */ 78f1df9364SStefan Roese { {6, 5, 6, 8, 9, 11, 12, 5, 5, 6, 11, 8, 5, 12, 5, 12} }, 79f1df9364SStefan Roese /* DDR3-2133M */ 80f1df9364SStefan Roese { {6, 5, 7, 9, 10, 12, 13, 5, 5, 7, 12, 9, 5, 13, 5, 13} }, 81f1df9364SStefan Roese /* DDR3-2133N* */ 82f1df9364SStefan Roese { {6, 6, 7, 9, 11, 13, 14, 6, 6, 7, 13, 9, 6, 14, 6, 14} }, 83f1df9364SStefan Roese /* DDR3-1333H-ext */ 84f1df9364SStefan Roese { {6, 6, 7, 9, 0, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} }, 85f1df9364SStefan Roese /* DDR3-1600K-ext */ 86f1df9364SStefan Roese { {6, 6, 7, 9, 11, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} }, 87f1df9364SStefan Roese /* DDR3-1866M-ext */ 88f1df9364SStefan Roese { {6, 6, 7, 9, 11, 13, 0, 6, 6, 7, 13, 9, 6, 13, 6, 13} }, 89f1df9364SStefan Roese }; 90f1df9364SStefan Roese 91f1df9364SStefan Roese /* Table for CWL values per speedbin index */ 92f1df9364SStefan Roese struct cl_val_per_freq cas_write_latency_table[] = { 93f1df9364SStefan Roese /* 94f1df9364SStefan Roese * 400M 667M 933M 311M 467M 600M 360 95f1df9364SStefan Roese * 100M 533M 800M 1066M 333M 850M 900 96f1df9364SStefan Roese * (the order is 100, 400, 533 etc.) 97f1df9364SStefan Roese */ 98f1df9364SStefan Roese /* DDR3-800D */ 99f1df9364SStefan Roese { {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} }, 100f1df9364SStefan Roese /* DDR3-800E */ 101f1df9364SStefan Roese { {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} }, 102f1df9364SStefan Roese /* DDR3-1066E */ 103f1df9364SStefan Roese { {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 104f1df9364SStefan Roese /* DDR3-1066F */ 105f1df9364SStefan Roese { {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 106f1df9364SStefan Roese /* DDR3-1066G */ 107f1df9364SStefan Roese { {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 108f1df9364SStefan Roese /* DDR3-1333F* */ 109f1df9364SStefan Roese { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 110f1df9364SStefan Roese /* DDR3-1333G */ 111f1df9364SStefan Roese { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 112f1df9364SStefan Roese /* DDR3-1333H */ 113f1df9364SStefan Roese { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 114f1df9364SStefan Roese /* DDR3-1333J* */ 115f1df9364SStefan Roese { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 116f1df9364SStefan Roese /* DDR3-1600G* */ 117f1df9364SStefan Roese { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 118f1df9364SStefan Roese /* DDR3-1600H */ 119f1df9364SStefan Roese { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 120f1df9364SStefan Roese /* DDR3-1600J */ 121f1df9364SStefan Roese { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 122f1df9364SStefan Roese /* DDR3-1600K */ 123f1df9364SStefan Roese { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 124f1df9364SStefan Roese /* DDR3-1866J* */ 125f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} }, 126f1df9364SStefan Roese /* DDR3-1866K */ 127f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} }, 128f1df9364SStefan Roese /* DDR3-1866L */ 129f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} }, 130f1df9364SStefan Roese /* DDR3-1866M* */ 131f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} }, 132f1df9364SStefan Roese /* DDR3-2133K* */ 133f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} }, 134f1df9364SStefan Roese /* DDR3-2133L */ 135f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} }, 136f1df9364SStefan Roese /* DDR3-2133M */ 137f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} }, 138f1df9364SStefan Roese /* DDR3-2133N* */ 139f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} }, 140f1df9364SStefan Roese /* DDR3-1333H-ext */ 141f1df9364SStefan Roese { {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 142f1df9364SStefan Roese /* DDR3-1600K-ext */ 143f1df9364SStefan Roese { {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} }, 144f1df9364SStefan Roese /* DDR3-1866M-ext */ 145f1df9364SStefan Roese { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} }, 146f1df9364SStefan Roese }; 147f1df9364SStefan Roese 148f1df9364SStefan Roese u8 twr_mask_table[] = { 149f1df9364SStefan Roese 10, 150f1df9364SStefan Roese 10, 151f1df9364SStefan Roese 10, 152f1df9364SStefan Roese 10, 153f1df9364SStefan Roese 10, 154f1df9364SStefan Roese 1, /*5*/ 155f1df9364SStefan Roese 2, /*6*/ 156f1df9364SStefan Roese 3, /*7*/ 157672e5598SChris Packham 4, /*8*/ 158f1df9364SStefan Roese 10, 159f1df9364SStefan Roese 5, /*10*/ 160f1df9364SStefan Roese 10, 161f1df9364SStefan Roese 6, /*12*/ 162f1df9364SStefan Roese 10, 163f1df9364SStefan Roese 7, /*14*/ 164f1df9364SStefan Roese 10, 165f1df9364SStefan Roese 0 /*16*/ 166f1df9364SStefan Roese }; 167f1df9364SStefan Roese 168f1df9364SStefan Roese u8 cl_mask_table[] = { 169f1df9364SStefan Roese 0, 170f1df9364SStefan Roese 0, 171f1df9364SStefan Roese 0, 172f1df9364SStefan Roese 0, 173f1df9364SStefan Roese 0, 174f1df9364SStefan Roese 0x2, 175f1df9364SStefan Roese 0x4, 176f1df9364SStefan Roese 0x6, 177f1df9364SStefan Roese 0x8, 178f1df9364SStefan Roese 0xa, 179f1df9364SStefan Roese 0xc, 180f1df9364SStefan Roese 0xe, 181f1df9364SStefan Roese 0x1, 182f1df9364SStefan Roese 0x3, 183f1df9364SStefan Roese 0x5, 184f1df9364SStefan Roese 0x5 185f1df9364SStefan Roese }; 186f1df9364SStefan Roese 187f1df9364SStefan Roese u8 cwl_mask_table[] = { 188f1df9364SStefan Roese 0, 189f1df9364SStefan Roese 0, 190f1df9364SStefan Roese 0, 191f1df9364SStefan Roese 0, 192f1df9364SStefan Roese 0, 193f1df9364SStefan Roese 0, 194f1df9364SStefan Roese 0x1, 195f1df9364SStefan Roese 0x2, 196f1df9364SStefan Roese 0x3, 197f1df9364SStefan Roese 0x4, 198f1df9364SStefan Roese 0x5, 199f1df9364SStefan Roese 0x6, 200f1df9364SStefan Roese 0x7, 201f1df9364SStefan Roese 0x8, 202f1df9364SStefan Roese 0x9, 203f1df9364SStefan Roese 0x9 204f1df9364SStefan Roese }; 205f1df9364SStefan Roese 206f1df9364SStefan Roese /* RFC values (in ns) */ 207f1df9364SStefan Roese u16 rfc_table[] = { 208f1df9364SStefan Roese 90, /* 512M */ 209f1df9364SStefan Roese 110, /* 1G */ 210f1df9364SStefan Roese 160, /* 2G */ 211f1df9364SStefan Roese 260, /* 4G */ 212f1df9364SStefan Roese 350 /* 8G */ 213f1df9364SStefan Roese }; 214f1df9364SStefan Roese 215f1df9364SStefan Roese u32 speed_bin_table_t_rc[] = { 216f1df9364SStefan Roese 50000, 217f1df9364SStefan Roese 52500, 218f1df9364SStefan Roese 48750, 219f1df9364SStefan Roese 50625, 220f1df9364SStefan Roese 52500, 221f1df9364SStefan Roese 46500, 222f1df9364SStefan Roese 48000, 223f1df9364SStefan Roese 49500, 224f1df9364SStefan Roese 51000, 225f1df9364SStefan Roese 45000, 226f1df9364SStefan Roese 46250, 227f1df9364SStefan Roese 47500, 228f1df9364SStefan Roese 48750, 229f1df9364SStefan Roese 44700, 230f1df9364SStefan Roese 45770, 231f1df9364SStefan Roese 46840, 232f1df9364SStefan Roese 47910, 233f1df9364SStefan Roese 43285, 234f1df9364SStefan Roese 44220, 235f1df9364SStefan Roese 45155, 236f1df9364SStefan Roese 46900 237f1df9364SStefan Roese }; 238f1df9364SStefan Roese 239f1df9364SStefan Roese u32 speed_bin_table_t_rcd_t_rp[] = { 240f1df9364SStefan Roese 12500, 241f1df9364SStefan Roese 15000, 242f1df9364SStefan Roese 11250, 243f1df9364SStefan Roese 13125, 244f1df9364SStefan Roese 15000, 245f1df9364SStefan Roese 10500, 246f1df9364SStefan Roese 12000, 247f1df9364SStefan Roese 13500, 248f1df9364SStefan Roese 15000, 249f1df9364SStefan Roese 10000, 250f1df9364SStefan Roese 11250, 251f1df9364SStefan Roese 12500, 252f1df9364SStefan Roese 13750, 253f1df9364SStefan Roese 10700, 254f1df9364SStefan Roese 11770, 255f1df9364SStefan Roese 12840, 256f1df9364SStefan Roese 13910, 257f1df9364SStefan Roese 10285, 258f1df9364SStefan Roese 11022, 259f1df9364SStefan Roese 12155, 260f1df9364SStefan Roese 13090, 261f1df9364SStefan Roese }; 262f1df9364SStefan Roese 263f1df9364SStefan Roese enum { 264f1df9364SStefan Roese PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR = 0, 265f1df9364SStefan Roese PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM 266f1df9364SStefan Roese }; 267f1df9364SStefan Roese 268f1df9364SStefan Roese static u8 pattern_killer_pattern_table_map[KILLER_PATTERN_LENGTH * 2][2] = { 269f1df9364SStefan Roese /*Aggressor / Victim */ 270f1df9364SStefan Roese {1, 0}, 271f1df9364SStefan Roese {0, 0}, 272f1df9364SStefan Roese {1, 0}, 273f1df9364SStefan Roese {1, 1}, 274f1df9364SStefan Roese {0, 1}, 275f1df9364SStefan Roese {0, 1}, 276f1df9364SStefan Roese {1, 0}, 277f1df9364SStefan Roese {0, 1}, 278f1df9364SStefan Roese {1, 0}, 279f1df9364SStefan Roese {0, 1}, 280f1df9364SStefan Roese {1, 0}, 281f1df9364SStefan Roese {1, 0}, 282f1df9364SStefan Roese {0, 1}, 283f1df9364SStefan Roese {1, 0}, 284f1df9364SStefan Roese {0, 1}, 285f1df9364SStefan Roese {0, 0}, 286f1df9364SStefan Roese {1, 1}, 287f1df9364SStefan Roese {0, 0}, 288f1df9364SStefan Roese {1, 1}, 289f1df9364SStefan Roese {0, 0}, 290f1df9364SStefan Roese {1, 1}, 291f1df9364SStefan Roese {0, 0}, 292f1df9364SStefan Roese {1, 1}, 293f1df9364SStefan Roese {1, 0}, 294f1df9364SStefan Roese {0, 0}, 295f1df9364SStefan Roese {1, 1}, 296f1df9364SStefan Roese {0, 0}, 297f1df9364SStefan Roese {1, 1}, 298f1df9364SStefan Roese {0, 0}, 299f1df9364SStefan Roese {0, 0}, 300f1df9364SStefan Roese {0, 0}, 301f1df9364SStefan Roese {0, 1}, 302f1df9364SStefan Roese {0, 1}, 303f1df9364SStefan Roese {1, 1}, 304f1df9364SStefan Roese {0, 0}, 305f1df9364SStefan Roese {0, 0}, 306f1df9364SStefan Roese {1, 1}, 307f1df9364SStefan Roese {1, 1}, 308f1df9364SStefan Roese {0, 0}, 309f1df9364SStefan Roese {1, 1}, 310f1df9364SStefan Roese {0, 0}, 311f1df9364SStefan Roese {1, 1}, 312f1df9364SStefan Roese {1, 1}, 313f1df9364SStefan Roese {0, 0}, 314f1df9364SStefan Roese {0, 0}, 315f1df9364SStefan Roese {1, 1}, 316f1df9364SStefan Roese {0, 0}, 317f1df9364SStefan Roese {1, 1}, 318f1df9364SStefan Roese {0, 1}, 319f1df9364SStefan Roese {0, 0}, 320f1df9364SStefan Roese {0, 1}, 321f1df9364SStefan Roese {0, 1}, 322f1df9364SStefan Roese {0, 0}, 323f1df9364SStefan Roese {1, 1}, 324f1df9364SStefan Roese {1, 1}, 325f1df9364SStefan Roese {1, 0}, 326f1df9364SStefan Roese {1, 0}, 327f1df9364SStefan Roese {1, 1}, 328f1df9364SStefan Roese {1, 1}, 329f1df9364SStefan Roese {1, 1}, 330f1df9364SStefan Roese {1, 1}, 331f1df9364SStefan Roese {1, 1}, 332f1df9364SStefan Roese {1, 1}, 333f1df9364SStefan Roese {1, 1} 334f1df9364SStefan Roese }; 335f1df9364SStefan Roese 336f1df9364SStefan Roese static u8 pattern_vref_pattern_table_map[] = { 337f1df9364SStefan Roese /* 1 means 0xffffffff, 0 is 0x0 */ 338f1df9364SStefan Roese 0xb8, 339f1df9364SStefan Roese 0x52, 340f1df9364SStefan Roese 0x55, 341f1df9364SStefan Roese 0x8a, 342f1df9364SStefan Roese 0x33, 343f1df9364SStefan Roese 0xa6, 344f1df9364SStefan Roese 0x6d, 345f1df9364SStefan Roese 0xfe 346f1df9364SStefan Roese }; 347f1df9364SStefan Roese 348f1df9364SStefan Roese /* Return speed Bin value for selected index and t* element */ 349f1df9364SStefan Roese u32 speed_bin_table(u8 index, enum speed_bin_table_elements element) 350f1df9364SStefan Roese { 351f1df9364SStefan Roese u32 result = 0; 352f1df9364SStefan Roese 353f1df9364SStefan Roese switch (element) { 354f1df9364SStefan Roese case SPEED_BIN_TRCD: 355f1df9364SStefan Roese case SPEED_BIN_TRP: 356f1df9364SStefan Roese result = speed_bin_table_t_rcd_t_rp[index]; 357f1df9364SStefan Roese break; 358f1df9364SStefan Roese case SPEED_BIN_TRAS: 359f1df9364SStefan Roese if (index < 6) 360f1df9364SStefan Roese result = 37500; 361f1df9364SStefan Roese else if (index < 10) 362f1df9364SStefan Roese result = 36000; 363f1df9364SStefan Roese else if (index < 14) 364f1df9364SStefan Roese result = 35000; 365f1df9364SStefan Roese else if (index < 18) 366f1df9364SStefan Roese result = 34000; 367f1df9364SStefan Roese else 368f1df9364SStefan Roese result = 33000; 369f1df9364SStefan Roese break; 370f1df9364SStefan Roese case SPEED_BIN_TRC: 371f1df9364SStefan Roese result = speed_bin_table_t_rc[index]; 372f1df9364SStefan Roese break; 373f1df9364SStefan Roese case SPEED_BIN_TRRD1K: 374f1df9364SStefan Roese if (index < 3) 375f1df9364SStefan Roese result = 10000; 376f1df9364SStefan Roese else if (index < 6) 377f1df9364SStefan Roese result = 7005; 378f1df9364SStefan Roese else if (index < 14) 379f1df9364SStefan Roese result = 6000; 380f1df9364SStefan Roese else 381f1df9364SStefan Roese result = 5000; 382f1df9364SStefan Roese break; 383f1df9364SStefan Roese case SPEED_BIN_TRRD2K: 384f1df9364SStefan Roese if (index < 6) 385f1df9364SStefan Roese result = 10000; 386f1df9364SStefan Roese else if (index < 14) 387f1df9364SStefan Roese result = 7005; 388f1df9364SStefan Roese else 389f1df9364SStefan Roese result = 6000; 390f1df9364SStefan Roese break; 391f1df9364SStefan Roese case SPEED_BIN_TPD: 392f1df9364SStefan Roese if (index < 3) 393f1df9364SStefan Roese result = 7500; 394f1df9364SStefan Roese else if (index < 10) 395f1df9364SStefan Roese result = 5625; 396f1df9364SStefan Roese else 397f1df9364SStefan Roese result = 5000; 398f1df9364SStefan Roese break; 399f1df9364SStefan Roese case SPEED_BIN_TFAW1K: 400f1df9364SStefan Roese if (index < 3) 401f1df9364SStefan Roese result = 40000; 402f1df9364SStefan Roese else if (index < 6) 403f1df9364SStefan Roese result = 37500; 404f1df9364SStefan Roese else if (index < 14) 405f1df9364SStefan Roese result = 30000; 406f1df9364SStefan Roese else if (index < 18) 407f1df9364SStefan Roese result = 27000; 408f1df9364SStefan Roese else 409f1df9364SStefan Roese result = 25000; 410f1df9364SStefan Roese break; 411f1df9364SStefan Roese case SPEED_BIN_TFAW2K: 412f1df9364SStefan Roese if (index < 6) 413f1df9364SStefan Roese result = 50000; 414f1df9364SStefan Roese else if (index < 10) 415f1df9364SStefan Roese result = 45000; 416f1df9364SStefan Roese else if (index < 14) 417f1df9364SStefan Roese result = 40000; 418f1df9364SStefan Roese else 419f1df9364SStefan Roese result = 35000; 420f1df9364SStefan Roese break; 421f1df9364SStefan Roese case SPEED_BIN_TWTR: 422f1df9364SStefan Roese result = 7500; 423f1df9364SStefan Roese break; 424f1df9364SStefan Roese case SPEED_BIN_TRTP: 425f1df9364SStefan Roese result = 7500; 426f1df9364SStefan Roese break; 427f1df9364SStefan Roese case SPEED_BIN_TWR: 428f1df9364SStefan Roese result = 15000; 429f1df9364SStefan Roese break; 430f1df9364SStefan Roese case SPEED_BIN_TMOD: 431f1df9364SStefan Roese result = 15000; 432f1df9364SStefan Roese break; 433672e5598SChris Packham case SPEED_BIN_TXPDLL: 434672e5598SChris Packham result = 24000; 435672e5598SChris Packham break; 436f1df9364SStefan Roese default: 437f1df9364SStefan Roese break; 438f1df9364SStefan Roese } 439f1df9364SStefan Roese 440f1df9364SStefan Roese return result; 441f1df9364SStefan Roese } 442f1df9364SStefan Roese 443f1df9364SStefan Roese static inline u32 pattern_table_get_killer_word(u8 dqs, u8 index) 444f1df9364SStefan Roese { 445f1df9364SStefan Roese u8 i, byte = 0; 446f1df9364SStefan Roese u8 role; 447f1df9364SStefan Roese 448f1df9364SStefan Roese for (i = 0; i < 8; i++) { 449f1df9364SStefan Roese role = (i == dqs) ? 450f1df9364SStefan Roese (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) : 451f1df9364SStefan Roese (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM); 452f1df9364SStefan Roese byte |= pattern_killer_pattern_table_map[index][role] << i; 453f1df9364SStefan Roese } 454f1df9364SStefan Roese 455f1df9364SStefan Roese return byte | (byte << 8) | (byte << 16) | (byte << 24); 456f1df9364SStefan Roese } 457f1df9364SStefan Roese 458f1df9364SStefan Roese static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index) 459f1df9364SStefan Roese { 460f1df9364SStefan Roese u8 i, byte0 = 0, byte1 = 0; 461f1df9364SStefan Roese u8 role; 462f1df9364SStefan Roese 463f1df9364SStefan Roese for (i = 0; i < 8; i++) { 464f1df9364SStefan Roese role = (i == dqs) ? 465f1df9364SStefan Roese (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) : 466f1df9364SStefan Roese (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM); 467f1df9364SStefan Roese byte0 |= pattern_killer_pattern_table_map[index * 2][role] << i; 468f1df9364SStefan Roese } 469f1df9364SStefan Roese 470f1df9364SStefan Roese for (i = 0; i < 8; i++) { 471f1df9364SStefan Roese role = (i == dqs) ? 472f1df9364SStefan Roese (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) : 473f1df9364SStefan Roese (PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM); 474f1df9364SStefan Roese byte1 |= pattern_killer_pattern_table_map 475f1df9364SStefan Roese [index * 2 + 1][role] << i; 476f1df9364SStefan Roese } 477f1df9364SStefan Roese 478f1df9364SStefan Roese return byte0 | (byte0 << 8) | (byte1 << 16) | (byte1 << 24); 479f1df9364SStefan Roese } 480f1df9364SStefan Roese 481f1df9364SStefan Roese static inline u32 pattern_table_get_sso_word(u8 sso, u8 index) 482f1df9364SStefan Roese { 483f1df9364SStefan Roese u8 step = sso + 1; 484f1df9364SStefan Roese 485f1df9364SStefan Roese if (0 == ((index / step) & 1)) 486f1df9364SStefan Roese return 0x0; 487f1df9364SStefan Roese else 488f1df9364SStefan Roese return 0xffffffff; 489f1df9364SStefan Roese } 490f1df9364SStefan Roese 491f1df9364SStefan Roese static inline u32 pattern_table_get_vref_word(u8 index) 492f1df9364SStefan Roese { 493f1df9364SStefan Roese if (0 == ((pattern_vref_pattern_table_map[index / 8] >> 494f1df9364SStefan Roese (index % 8)) & 1)) 495f1df9364SStefan Roese return 0x0; 496f1df9364SStefan Roese else 497f1df9364SStefan Roese return 0xffffffff; 498f1df9364SStefan Roese } 499f1df9364SStefan Roese 500f1df9364SStefan Roese static inline u32 pattern_table_get_vref_word16(u8 index) 501f1df9364SStefan Roese { 502f1df9364SStefan Roese if (0 == pattern_killer_pattern_table_map 503f1df9364SStefan Roese [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] && 504f1df9364SStefan Roese 0 == pattern_killer_pattern_table_map 505f1df9364SStefan Roese [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1]) 506f1df9364SStefan Roese return 0x00000000; 507f1df9364SStefan Roese else if (1 == pattern_killer_pattern_table_map 508f1df9364SStefan Roese [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] && 509f1df9364SStefan Roese 0 == pattern_killer_pattern_table_map 510f1df9364SStefan Roese [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1]) 511f1df9364SStefan Roese return 0xffff0000; 512f1df9364SStefan Roese else if (0 == pattern_killer_pattern_table_map 513f1df9364SStefan Roese [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] && 514f1df9364SStefan Roese 1 == pattern_killer_pattern_table_map 515f1df9364SStefan Roese [PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1]) 516f1df9364SStefan Roese return 0x0000ffff; 517f1df9364SStefan Roese else 518f1df9364SStefan Roese return 0xffffffff; 519f1df9364SStefan Roese } 520f1df9364SStefan Roese 521f1df9364SStefan Roese static inline u32 pattern_table_get_static_pbs_word(u8 index) 522f1df9364SStefan Roese { 523f1df9364SStefan Roese u16 temp; 524f1df9364SStefan Roese 525f1df9364SStefan Roese temp = ((0x00ff << (index / 3)) & 0xff00) >> 8; 526f1df9364SStefan Roese 527f1df9364SStefan Roese return temp | (temp << 8) | (temp << 16) | (temp << 24); 528f1df9364SStefan Roese } 529f1df9364SStefan Roese 530f1df9364SStefan Roese inline u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index) 531f1df9364SStefan Roese { 532f1df9364SStefan Roese u32 pattern; 533f1df9364SStefan Roese struct hws_topology_map *tm = ddr3_get_topology_map(); 534f1df9364SStefan Roese 535f1df9364SStefan Roese if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) { 536f1df9364SStefan Roese /* 32bit patterns */ 537f1df9364SStefan Roese switch (type) { 538f1df9364SStefan Roese case PATTERN_PBS1: 539f1df9364SStefan Roese case PATTERN_PBS2: 540f1df9364SStefan Roese if (index == 0 || index == 2 || index == 5 || 541f1df9364SStefan Roese index == 7) 542f1df9364SStefan Roese pattern = PATTERN_55; 543f1df9364SStefan Roese else 544f1df9364SStefan Roese pattern = PATTERN_AA; 545f1df9364SStefan Roese break; 546f1df9364SStefan Roese case PATTERN_PBS3: 547f1df9364SStefan Roese if (0 == (index & 1)) 548f1df9364SStefan Roese pattern = PATTERN_55; 549f1df9364SStefan Roese else 550f1df9364SStefan Roese pattern = PATTERN_AA; 551f1df9364SStefan Roese break; 552f1df9364SStefan Roese case PATTERN_RL: 553f1df9364SStefan Roese if (index < 6) 554f1df9364SStefan Roese pattern = PATTERN_00; 555f1df9364SStefan Roese else 556f1df9364SStefan Roese pattern = PATTERN_80; 557f1df9364SStefan Roese break; 558f1df9364SStefan Roese case PATTERN_STATIC_PBS: 559f1df9364SStefan Roese pattern = pattern_table_get_static_pbs_word(index); 560f1df9364SStefan Roese break; 561f1df9364SStefan Roese case PATTERN_KILLER_DQ0: 562f1df9364SStefan Roese case PATTERN_KILLER_DQ1: 563f1df9364SStefan Roese case PATTERN_KILLER_DQ2: 564f1df9364SStefan Roese case PATTERN_KILLER_DQ3: 565f1df9364SStefan Roese case PATTERN_KILLER_DQ4: 566f1df9364SStefan Roese case PATTERN_KILLER_DQ5: 567f1df9364SStefan Roese case PATTERN_KILLER_DQ6: 568f1df9364SStefan Roese case PATTERN_KILLER_DQ7: 569f1df9364SStefan Roese pattern = pattern_table_get_killer_word( 570f1df9364SStefan Roese (u8)(type - PATTERN_KILLER_DQ0), index); 571f1df9364SStefan Roese break; 572f1df9364SStefan Roese case PATTERN_RL2: 573f1df9364SStefan Roese if (index < 6) 574f1df9364SStefan Roese pattern = PATTERN_00; 575f1df9364SStefan Roese else 576f1df9364SStefan Roese pattern = PATTERN_01; 577f1df9364SStefan Roese break; 578f1df9364SStefan Roese case PATTERN_TEST: 579f1df9364SStefan Roese if (index > 1 && index < 6) 580f1df9364SStefan Roese pattern = PATTERN_20; 581f1df9364SStefan Roese else 582f1df9364SStefan Roese pattern = PATTERN_00; 583f1df9364SStefan Roese break; 584f1df9364SStefan Roese case PATTERN_FULL_SSO0: 585f1df9364SStefan Roese case PATTERN_FULL_SSO1: 586f1df9364SStefan Roese case PATTERN_FULL_SSO2: 587f1df9364SStefan Roese case PATTERN_FULL_SSO3: 588f1df9364SStefan Roese pattern = pattern_table_get_sso_word( 589f1df9364SStefan Roese (u8)(type - PATTERN_FULL_SSO0), index); 590f1df9364SStefan Roese break; 591f1df9364SStefan Roese case PATTERN_VREF: 592f1df9364SStefan Roese pattern = pattern_table_get_vref_word(index); 593f1df9364SStefan Roese break; 594f1df9364SStefan Roese default: 595f1df9364SStefan Roese pattern = 0; 596f1df9364SStefan Roese break; 597f1df9364SStefan Roese } 598f1df9364SStefan Roese } else { 599f1df9364SStefan Roese /* 16bit patterns */ 600f1df9364SStefan Roese switch (type) { 601f1df9364SStefan Roese case PATTERN_PBS1: 602f1df9364SStefan Roese case PATTERN_PBS2: 603f1df9364SStefan Roese case PATTERN_PBS3: 604f1df9364SStefan Roese pattern = PATTERN_55AA; 605f1df9364SStefan Roese break; 606f1df9364SStefan Roese case PATTERN_RL: 607f1df9364SStefan Roese if (index < 3) 608f1df9364SStefan Roese pattern = PATTERN_00; 609f1df9364SStefan Roese else 610f1df9364SStefan Roese pattern = PATTERN_80; 611f1df9364SStefan Roese break; 612f1df9364SStefan Roese case PATTERN_STATIC_PBS: 613f1df9364SStefan Roese pattern = PATTERN_00FF; 614f1df9364SStefan Roese break; 615f1df9364SStefan Roese case PATTERN_KILLER_DQ0: 616f1df9364SStefan Roese case PATTERN_KILLER_DQ1: 617f1df9364SStefan Roese case PATTERN_KILLER_DQ2: 618f1df9364SStefan Roese case PATTERN_KILLER_DQ3: 619f1df9364SStefan Roese case PATTERN_KILLER_DQ4: 620f1df9364SStefan Roese case PATTERN_KILLER_DQ5: 621f1df9364SStefan Roese case PATTERN_KILLER_DQ6: 622f1df9364SStefan Roese case PATTERN_KILLER_DQ7: 623f1df9364SStefan Roese pattern = pattern_table_get_killer_word16( 624f1df9364SStefan Roese (u8)(type - PATTERN_KILLER_DQ0), index); 625f1df9364SStefan Roese break; 626f1df9364SStefan Roese case PATTERN_RL2: 627f1df9364SStefan Roese if (index < 3) 628f1df9364SStefan Roese pattern = PATTERN_00; 629f1df9364SStefan Roese else 630f1df9364SStefan Roese pattern = PATTERN_01; 631f1df9364SStefan Roese break; 632f1df9364SStefan Roese case PATTERN_TEST: 633f1df9364SStefan Roese pattern = PATTERN_0080; 634f1df9364SStefan Roese break; 635f1df9364SStefan Roese case PATTERN_FULL_SSO0: 636f1df9364SStefan Roese pattern = 0x0000ffff; 637f1df9364SStefan Roese break; 638f1df9364SStefan Roese case PATTERN_FULL_SSO1: 639f1df9364SStefan Roese case PATTERN_FULL_SSO2: 640f1df9364SStefan Roese case PATTERN_FULL_SSO3: 641f1df9364SStefan Roese pattern = pattern_table_get_sso_word( 642f1df9364SStefan Roese (u8)(type - PATTERN_FULL_SSO1), index); 643f1df9364SStefan Roese break; 644f1df9364SStefan Roese case PATTERN_VREF: 645f1df9364SStefan Roese pattern = pattern_table_get_vref_word16(index); 646f1df9364SStefan Roese break; 647f1df9364SStefan Roese default: 648f1df9364SStefan Roese pattern = 0; 649f1df9364SStefan Roese break; 650f1df9364SStefan Roese } 651f1df9364SStefan Roese } 652f1df9364SStefan Roese 653f1df9364SStefan Roese return pattern; 654f1df9364SStefan Roese } 655