1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _DDR3_INIT_H
7 #define _DDR3_INIT_H
8 
9 #include "ddr_ml_wrapper.h"
10 #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
11 #include "mv_ddr_plat.h"
12 #endif
13 
14 #include "seq_exec.h"
15 #include "ddr3_logging_def.h"
16 #include "ddr3_training_hw_algo.h"
17 #include "ddr3_training_ip.h"
18 #include "ddr3_training_ip_centralization.h"
19 #include "ddr3_training_ip_engine.h"
20 #include "ddr3_training_ip_flow.h"
21 #include "ddr3_training_ip_pbs.h"
22 #include "ddr3_training_ip_prv_if.h"
23 #include "ddr3_training_leveling.h"
24 #include "xor.h"
25 
26 /* For checking function return values */
27 #define CHECK_STATUS(orig_func)		\
28 	{				\
29 		int status;		\
30 		status = orig_func;	\
31 		if (MV_OK != status)	\
32 			return status;	\
33 	}
34 
35 #define GET_MAX_VALUE(x, y)			\
36 	((x) > (y)) ? (x) : (y)
37 
38 #define SUB_VERSION	0
39 
40 /* max number of devices supported by driver */
41 #define MAX_DEVICE_NUM	1
42 
43 enum log_level  {
44 	MV_LOG_LEVEL_0,
45 	MV_LOG_LEVEL_1,
46 	MV_LOG_LEVEL_2,
47 	MV_LOG_LEVEL_3
48 };
49 
50 /* Globals */
51 extern u8 debug_training, debug_calibration, debug_ddr4_centralization,
52 	debug_tap_tuning, debug_dm_tuning;
53 extern u8 is_reg_dump;
54 extern u8 generic_init_controller;
55 /* list of allowed frequency listed in order of enum hws_ddr_freq */
56 extern u32 freq_val[DDR_FREQ_LAST];
57 extern u32 is_pll_old;
58 extern struct cl_val_per_freq cas_latency_table[];
59 extern struct pattern_info pattern_table[];
60 extern struct cl_val_per_freq cas_write_latency_table[];
61 extern u8 debug_centralization, debug_training_ip, debug_training_bist,
62 	debug_pbs, debug_training_static, debug_leveling;
63 extern struct hws_tip_config_func_db config_func_info[];
64 extern u8 twr_mask_table[];
65 extern u8 cl_mask_table[];
66 extern u8 cwl_mask_table[];
67 extern u16 rfc_table[];
68 extern u32 speed_bin_table_t_rc[];
69 extern u32 speed_bin_table_t_rcd_t_rp[];
70 
71 extern u32 vref_init_val;
72 extern u32 g_zpri_data;
73 extern u32 g_znri_data;
74 extern u32 g_zpri_ctrl;
75 extern u32 g_znri_ctrl;
76 extern u32 g_zpodt_data;
77 extern u32 g_znodt_data;
78 extern u32 g_zpodt_ctrl;
79 extern u32 g_znodt_ctrl;
80 extern u32 g_dic;
81 extern u32 g_odt_config;
82 extern u32 g_rtt_nom;
83 extern u32 g_rtt_wr;
84 extern u32 g_rtt_park;
85 
86 extern u8 debug_training_access;
87 extern u32 first_active_if;
88 extern u32 delay_enable, ck_delay, ca_delay;
89 extern u32 mask_tune_func;
90 extern u32 rl_version;
91 extern int rl_mid_freq_wa;
92 extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
93 extern enum hws_ddr_freq medium_freq;
94 
95 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
96 extern enum hws_ddr_freq low_freq;
97 extern enum auto_tune_stage training_stage;
98 extern u32 is_pll_before_init;
99 extern u32 is_adll_calib_before_init;
100 extern u32 is_dfs_in_init;
101 extern int wl_debug_delay;
102 extern u32 silicon_delay[MAX_DEVICE_NUM];
103 extern u32 start_pattern, end_pattern;
104 extern u32 phy_reg0_val;
105 extern u32 phy_reg1_val;
106 extern u32 phy_reg2_val;
107 extern u32 phy_reg3_val;
108 extern enum hws_pattern sweep_pattern;
109 extern enum hws_pattern pbs_pattern;
110 extern u32 g_znri_data;
111 extern u32 g_zpri_data;
112 extern u32 g_znri_ctrl;
113 extern u32 g_zpri_ctrl;
114 extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
115 	n_finger_end, p_finger_step, n_finger_step;
116 extern u32 mode_2t;
117 extern u32 xsb_validate_type;
118 extern u32 xsb_validation_base_address;
119 extern u32 odt_additional;
120 extern u32 debug_mode;
121 extern u32 debug_dunit;
122 extern u32 clamp_tbl[];
123 extern u32 freq_mask[MAX_DEVICE_NUM][DDR_FREQ_LAST];
124 
125 extern u32 maxt_poll_tries;
126 extern u32 is_bist_reset_bit;
127 
128 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
129 extern u32 effective_cs;
130 extern int ddr3_tip_centr_skip_min_win_check;
131 extern u32 *dq_map_table;
132 
133 extern u8 debug_training_hw_alg;
134 
135 extern u32 start_xsb_offset;
136 extern u32 odt_config;
137 
138 extern u16 mask_results_dq_reg_map[];
139 
140 extern u32 target_freq;
141 extern u32 dfs_low_freq;
142 extern u32 mem_size[];
143 
144 extern u32 nominal_avs;
145 extern u32 extension_avs;
146 
147 
148 /* Prototypes */
149 int ddr3_init(void);
150 int ddr3_tip_enable_init_sequence(u32 dev_num);
151 
152 int ddr3_hws_hw_training(enum hws_algo_type algo_mode);
153 int mv_ddr_early_init(void);
154 int mv_ddr_early_init2(void);
155 int ddr3_silicon_post_init(void);
156 int ddr3_post_run_alg(void);
157 int ddr3_if_ecc_enabled(void);
158 void ddr3_new_tip_ecc_scrub(void);
159 
160 void mv_ddr_ver_print(void);
161 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void);
162 
163 int ddr3_if_ecc_enabled(void);
164 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
165 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
166 int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
167 
168 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
169 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
170 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
171 		     int reg_addr, u32 mask);
172 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
173 			 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
174 int ddr3_tip_restore_dunit_regs(u32 dev_num);
175 void print_topology(struct mv_ddr_topology_map *tm);
176 
177 u32 mv_board_id_get(void);
178 
179 int ddr3_load_topology_map(void);
180 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
181 void mv_ddr_user_log_level_set(enum ddr_lib_debug_block block);
182 int ddr3_tip_tune_training_params(u32 dev_num,
183 				  struct tune_train_params *params);
184 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
185 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
186 u32 mv_board_id_index_get(u32 board_id);
187 void ddr3_set_log_level(u32 n_log_level);
188 int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num);
189 
190 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
191 
192 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
193 int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
194 
195 u32 mv_ddr_init_freq_get(void);
196 void mv_ddr_mc_config(void);
197 int mv_ddr_mc_init(void);
198 void mv_ddr_set_calib_controller(void);
199 #endif /* _DDR3_INIT_H */
200