1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017 Intel Corporation <www.intel.com> 4 */ 5 6 #include <common.h> 7 #include <errno.h> 8 #include <fdtdec.h> 9 #include <malloc.h> 10 #include <wait_bit.h> 11 #include <watchdog.h> 12 #include <asm/io.h> 13 #include <asm/arch/fpga_manager.h> 14 #include <asm/arch/misc.h> 15 #include <asm/arch/reset_manager.h> 16 #include <asm/arch/sdram.h> 17 #include <linux/kernel.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 static void sdram_mmr_init(void); 22 static u64 sdram_size_calc(void); 23 24 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */ 25 #define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) 26 27 #define ARRIA_DDR_CONFIG(A, B, C, R) \ 28 (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) 29 #define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config) 30 #define DDR_REG_SEQ2CORE 0xFFD0507C 31 #define DDR_REG_CORE2SEQ 0xFFD05078 32 #define DDR_READ_LATENCY_DELAY 40 33 #define DDR_SIZE_2GB_HEX 0x80000000 34 #define DDR_MAX_TRIES 0x00100000 35 36 #define IO48_MMR_DRAMSTS 0xFFCFA0EC 37 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110 38 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114 39 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118 40 41 #define SEQ2CORE_MASK 0xF 42 #define CORE2SEQ_INT_REQ 0xF 43 #define SEQ2CORE_INT_RESP_BIT 3 44 45 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = 46 (void *)SOCFPGA_SDR_ADDRESS; 47 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = 48 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; 49 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram 50 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base = 51 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS; 52 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base = 53 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; 54 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = 55 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; 56 57 /* The following are the supported configurations */ 58 static u32 ddr_config[] = { 59 /* Chip - Row - Bank - Column Style */ 60 /* All Types */ 61 ARRIA_DDR_CONFIG(0, 3, 10, 12), 62 ARRIA_DDR_CONFIG(0, 3, 10, 13), 63 ARRIA_DDR_CONFIG(0, 3, 10, 14), 64 ARRIA_DDR_CONFIG(0, 3, 10, 15), 65 ARRIA_DDR_CONFIG(0, 3, 10, 16), 66 ARRIA_DDR_CONFIG(0, 3, 10, 17), 67 /* LPDDR x16 */ 68 ARRIA_DDR_CONFIG(0, 3, 11, 14), 69 ARRIA_DDR_CONFIG(0, 3, 11, 15), 70 ARRIA_DDR_CONFIG(0, 3, 11, 16), 71 ARRIA_DDR_CONFIG(0, 3, 12, 15), 72 /* DDR4 Only */ 73 ARRIA_DDR_CONFIG(0, 4, 10, 14), 74 ARRIA_DDR_CONFIG(0, 4, 10, 15), 75 ARRIA_DDR_CONFIG(0, 4, 10, 16), 76 ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */ 77 /* Chip - Bank - Row - Column Style */ 78 ARRIA_DDR_CONFIG(1, 3, 10, 12), 79 ARRIA_DDR_CONFIG(1, 3, 10, 13), 80 ARRIA_DDR_CONFIG(1, 3, 10, 14), 81 ARRIA_DDR_CONFIG(1, 3, 10, 15), 82 ARRIA_DDR_CONFIG(1, 3, 10, 16), 83 ARRIA_DDR_CONFIG(1, 3, 10, 17), 84 ARRIA_DDR_CONFIG(1, 3, 11, 14), 85 ARRIA_DDR_CONFIG(1, 3, 11, 15), 86 ARRIA_DDR_CONFIG(1, 3, 11, 16), 87 ARRIA_DDR_CONFIG(1, 3, 12, 15), 88 /* DDR4 Only */ 89 ARRIA_DDR_CONFIG(1, 4, 10, 14), 90 ARRIA_DDR_CONFIG(1, 4, 10, 15), 91 ARRIA_DDR_CONFIG(1, 4, 10, 16), 92 ARRIA_DDR_CONFIG(1, 4, 10, 17), 93 }; 94 95 static int match_ddr_conf(u32 ddr_conf) 96 { 97 int i; 98 99 for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { 100 if (ddr_conf == ddr_config[i]) 101 return i; 102 } 103 return 0; 104 } 105 106 /* Check whether SDRAM is successfully Calibrated */ 107 static int is_sdram_cal_success(void) 108 { 109 return readl(&socfpga_ecc_hmc_base->ddrcalstat); 110 } 111 112 static unsigned char ddr_get_bit(u32 ereg, unsigned char bit) 113 { 114 u32 reg = readl(ereg); 115 116 return (reg & BIT(bit)) ? 1 : 0; 117 } 118 119 static unsigned char ddr_wait_bit(u32 ereg, u32 bit, 120 u32 expected, u32 timeout_usec) 121 { 122 u32 tmr; 123 124 for (tmr = 0; tmr < timeout_usec; tmr += 100) { 125 udelay(100); 126 WATCHDOG_RESET(); 127 if (ddr_get_bit(ereg, bit) == expected) 128 return 0; 129 } 130 131 return 1; 132 } 133 134 static int emif_clear(void) 135 { 136 u32 i = DDR_MAX_TRIES; 137 u8 ret = 0; 138 139 writel(0, DDR_REG_CORE2SEQ); 140 141 do { 142 ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, 143 SEQ2CORE_MASK, 1, 50, 0); 144 } while (ret && (--i > 0)); 145 146 return !i; 147 } 148 149 static int emif_reset(void) 150 { 151 u32 c2s, s2c; 152 153 c2s = readl(DDR_REG_CORE2SEQ); 154 s2c = readl(DDR_REG_SEQ2CORE); 155 156 debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", 157 c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0), 158 readl(IO48_MMR_NIOS2_RESERVE1), 159 readl(IO48_MMR_NIOS2_RESERVE2), 160 readl(IO48_MMR_DRAMSTS)); 161 162 if ((s2c & SEQ2CORE_MASK) && emif_clear()) { 163 debug("failed emif_clear()\n"); 164 return -EPERM; 165 } 166 167 writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); 168 169 if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) { 170 debug("emif_reset failed to see interrupt acknowledge\n"); 171 return -EPERM; 172 } else { 173 debug("emif_reset interrupt acknowledged\n"); 174 } 175 176 if (emif_clear()) { 177 debug("emif_clear() failed\n"); 178 return -EPERM; 179 } 180 debug("emif_reset interrupt cleared\n"); 181 182 debug("nr0=%08x nr1=%08x nr2=%08x\n", 183 readl(IO48_MMR_NIOS2_RESERVE0), 184 readl(IO48_MMR_NIOS2_RESERVE1), 185 readl(IO48_MMR_NIOS2_RESERVE2)); 186 187 return 0; 188 } 189 190 static int ddr_setup(void) 191 { 192 int i, j, ddr_setup_complete = 0; 193 194 /* Try 3 times to do a calibration */ 195 for (i = 0; (i < 3) && !ddr_setup_complete; i++) { 196 WATCHDOG_RESET(); 197 198 /* A delay to wait for calibration bit to set */ 199 for (j = 0; (j < 10) && !ddr_setup_complete; j++) { 200 mdelay(500); 201 ddr_setup_complete = is_sdram_cal_success(); 202 } 203 204 if (!ddr_setup_complete) 205 if (emif_reset()) 206 puts("Error: Failed to reset EMIF\n"); 207 } 208 209 /* After 3 times trying calibration */ 210 if (!ddr_setup_complete) { 211 puts("Error: Could Not Calibrate SDRAM\n"); 212 return -EPERM; 213 } 214 215 return 0; 216 } 217 218 static int sdram_is_ecc_enabled(void) 219 { 220 return !!(readl(&socfpga_ecc_hmc_base->eccctrl) & 221 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK); 222 } 223 224 /* Initialize SDRAM ECC bits to avoid false DBE */ 225 static void sdram_init_ecc_bits(u32 size) 226 { 227 icache_enable(); 228 229 memset(0, 0, 0x8000); 230 gd->arch.tlb_addr = 0x4000; 231 gd->arch.tlb_size = PGTABLE_SIZE; 232 233 dcache_enable(); 234 235 printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20); 236 memset((void *)0x8000, 0, size - 0x8000); 237 flush_dcache_all(); 238 printf("DDRCAL: Scrubbing ECC RAM done.\n"); 239 dcache_disable(); 240 } 241 242 /* Function to startup the SDRAM*/ 243 static int sdram_startup(void) 244 { 245 /* Release NOC ddr scheduler from reset */ 246 socfpga_reset_deassert_noc_ddr_scheduler(); 247 248 /* Bringup the DDR (calibration and configuration) */ 249 return ddr_setup(); 250 } 251 252 static u64 sdram_size_calc(void) 253 { 254 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); 255 256 u64 size = BIT(((dramaddrw & 257 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >> 258 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) + 259 ((dramaddrw & 260 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> 261 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) + 262 ((dramaddrw & 263 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> 264 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + 265 ((dramaddrw & 266 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> 267 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) + 268 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK)); 269 270 size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & 271 ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK)); 272 273 debug("SDRAM size=%llu", size); 274 275 return size; 276 } 277 278 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/ 279 static void sdram_mmr_init(void) 280 { 281 u32 update_value, io48_value; 282 u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0); 283 u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1); 284 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); 285 u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0); 286 u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1); 287 u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2); 288 u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3); 289 u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4); 290 u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9); 291 u32 ddrioctl; 292 293 /* 294 * Configure the DDR IO size [0xFFCFB008] 295 * niosreserve0: Used to indicate DDR width & 296 * bit[7:0] = Number of data bits (0x20 for 32bit) 297 * bit[8] = 1 if user-mode OCT is present 298 * bit[9] = 1 if warm reset compiled into EMIF Cal Code 299 * bit[10] = 1 if warm reset is on during generation in EMIF Cal 300 * niosreserve1: IP ADCDS version encoded as 16 bit value 301 * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, 302 * 3=EAP, 4-6 are reserved) 303 * bit[5:3] = Service Pack # (e.g. 1) 304 * bit[9:6] = Minor Release # 305 * bit[14:10] = Major Release # 306 */ 307 if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) { 308 update_value = readl(&socfpga_io48_mmr_base->niosreserve0); 309 writel(((update_value & 0xFF) >> 5), 310 &socfpga_ecc_hmc_base->ddrioctrl); 311 } 312 313 ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl); 314 315 /* Set the DDR Configuration [0xFFD12400] */ 316 io48_value = ARRIA_DDR_CONFIG( 317 ((ctrlcfg1 & 318 IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >> 319 IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT), 320 ((dramaddrw & 321 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> 322 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + 323 ((dramaddrw & 324 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> 325 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT), 326 (dramaddrw & 327 IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK), 328 ((dramaddrw & 329 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> 330 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT)); 331 332 update_value = match_ddr_conf(io48_value); 333 if (update_value) 334 writel(update_value, 335 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf); 336 337 /* 338 * Configure DDR timing [0xFFD1240C] 339 * RDTOMISS = tRTP + tRP + tRCD - BL/2 340 * WRTOMISS = WL + tWR + tRP + tRCD and 341 * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... 342 * First part of equation is in memory clock units so divide by 2 343 * for HMC clock units. 1066MHz is close to 1ns so use 15 directly. 344 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD 345 */ 346 u32 ctrlcfg0_cfg_ctrl_burst_len = 347 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >> 348 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT; 349 350 u32 caltim0_cfg_act_to_rdwr = caltim0 & 351 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK; 352 353 u32 caltim0_cfg_act_to_act = 354 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >> 355 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT; 356 357 u32 caltim0_cfg_act_to_act_db = 358 (caltim0 & 359 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >> 360 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT; 361 362 u32 caltim1_cfg_rd_to_wr = 363 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >> 364 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT; 365 366 u32 caltim1_cfg_rd_to_rd_dc = 367 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >> 368 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT; 369 370 u32 caltim1_cfg_rd_to_wr_dc = 371 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >> 372 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT; 373 374 u32 caltim2_cfg_rd_to_pch = 375 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >> 376 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT; 377 378 u32 caltim3_cfg_wr_to_rd = 379 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >> 380 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT; 381 382 u32 caltim3_cfg_wr_to_rd_dc = 383 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >> 384 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT; 385 386 u32 caltim4_cfg_pch_to_valid = 387 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >> 388 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT; 389 390 u32 caltim9_cfg_4_act_to_act = caltim9 & 391 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK; 392 393 update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid + 394 caltim0_cfg_act_to_rdwr - 395 (ctrlcfg0_cfg_ctrl_burst_len >> 2)); 396 397 io48_value = ((((socfpga_io48_mmr_base->dramtiming0 & 398 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 + 399 (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) - 400 /* Up to here was in memory cycles so divide by 2 */ 401 caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr + 402 caltim4_cfg_pch_to_valid); 403 404 writel(((caltim0_cfg_act_to_act << 405 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) | 406 (update_value << 407 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) | 408 (io48_value << 409 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) | 410 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) << 411 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) | 412 (caltim1_cfg_rd_to_wr << 413 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) | 414 (caltim3_cfg_wr_to_rd << 415 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) | 416 (((ddrioctl == 1) ? 1 : 0) << 417 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)), 418 &socfpga_noc_ddr_scheduler_base-> 419 ddr_t_main_scheduler_ddrtiming); 420 421 /* Configure DDR mode [0xFFD12410] [precharge = 0] */ 422 writel(((ddrioctl ? 0 : 1) << 423 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB), 424 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode); 425 426 /* Configure the read latency [0xFFD12414] */ 427 writel(((socfpga_io48_mmr_base->dramtiming0 & 428 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) + 429 DDR_READ_LATENCY_DELAY, 430 &socfpga_noc_ddr_scheduler_base-> 431 ddr_t_main_scheduler_readlatency); 432 433 /* 434 * Configuring timing values concerning activate commands 435 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR] 436 */ 437 writel(((caltim0_cfg_act_to_act_db << 438 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) | 439 (caltim9_cfg_4_act_to_act << 440 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) | 441 (ARRIA10_SDR_ACTIVATE_FAWBANK << 442 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)), 443 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate); 444 445 /* 446 * Configuring timing values concerning device to device data bus 447 * ownership change [0xFFD1243C] 448 */ 449 writel(((caltim1_cfg_rd_to_rd_dc << 450 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) | 451 (caltim1_cfg_rd_to_wr_dc << 452 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) | 453 (caltim3_cfg_wr_to_rd_dc << 454 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)), 455 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev); 456 457 /* Enable or disable the SDRAM ECC */ 458 if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) { 459 setbits_le32(&socfpga_ecc_hmc_base->eccctrl, 460 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | 461 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | 462 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); 463 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, 464 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | 465 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK)); 466 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2, 467 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | 468 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); 469 } else { 470 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, 471 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | 472 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | 473 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); 474 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2, 475 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | 476 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); 477 } 478 } 479 480 struct firewall_entry { 481 const char *prop_name; 482 const u32 cfg_addr; 483 const u32 en_addr; 484 const u32 en_bit; 485 }; 486 #define FW_MPU_FPGA_ADDRESS \ 487 ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\ 488 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS) 489 490 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \ 491 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \ 492 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR)) 493 494 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \ 495 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \ 496 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR)) 497 498 const struct firewall_entry firewall_table[] = { 499 { 500 "mpu0", 501 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr), 502 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 503 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK 504 }, 505 { 506 "mpu1", 507 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + 508 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr), 509 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 510 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK 511 }, 512 { 513 "mpu2", 514 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr), 515 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 516 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK 517 }, 518 { 519 "mpu3", 520 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr), 521 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 522 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK 523 }, 524 { 525 "l3-0", 526 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr), 527 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), 528 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK 529 }, 530 { 531 "l3-1", 532 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr), 533 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), 534 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK 535 }, 536 { 537 "l3-2", 538 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr), 539 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), 540 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK 541 }, 542 { 543 "l3-3", 544 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr), 545 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), 546 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK 547 }, 548 { 549 "l3-4", 550 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr), 551 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), 552 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK 553 }, 554 { 555 "l3-5", 556 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr), 557 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), 558 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK 559 }, 560 { 561 "l3-6", 562 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr), 563 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), 564 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK 565 }, 566 { 567 "l3-7", 568 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr), 569 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), 570 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK 571 }, 572 { 573 "fpga2sdram0-0", 574 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 575 (fpga2sdram0region0addr), 576 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 577 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK 578 }, 579 { 580 "fpga2sdram0-1", 581 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 582 (fpga2sdram0region1addr), 583 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 584 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK 585 }, 586 { 587 "fpga2sdram0-2", 588 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 589 (fpga2sdram0region2addr), 590 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 591 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK 592 }, 593 { 594 "fpga2sdram0-3", 595 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 596 (fpga2sdram0region3addr), 597 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 598 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK 599 }, 600 { 601 "fpga2sdram1-0", 602 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 603 (fpga2sdram1region0addr), 604 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 605 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK 606 }, 607 { 608 "fpga2sdram1-1", 609 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 610 (fpga2sdram1region1addr), 611 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 612 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK 613 }, 614 { 615 "fpga2sdram1-2", 616 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 617 (fpga2sdram1region2addr), 618 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 619 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK 620 }, 621 { 622 "fpga2sdram1-3", 623 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 624 (fpga2sdram1region3addr), 625 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 626 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK 627 }, 628 { 629 "fpga2sdram2-0", 630 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 631 (fpga2sdram2region0addr), 632 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 633 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK 634 }, 635 { 636 "fpga2sdram2-1", 637 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 638 (fpga2sdram2region1addr), 639 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 640 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK 641 }, 642 { 643 "fpga2sdram2-2", 644 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 645 (fpga2sdram2region2addr), 646 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 647 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK 648 }, 649 { 650 "fpga2sdram2-3", 651 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET 652 (fpga2sdram2region3addr), 653 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), 654 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK 655 }, 656 657 }; 658 659 static int of_sdram_firewall_setup(const void *blob) 660 { 661 int child, i, node, ret; 662 u32 start_end[2]; 663 char name[32]; 664 665 node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC); 666 if (node < 0) 667 return -ENXIO; 668 669 child = fdt_first_subnode(blob, node); 670 if (child < 0) 671 return -ENXIO; 672 673 /* set to default state */ 674 writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable); 675 writel(0, &socfpga_noc_fw_ddr_l3_base->enable); 676 677 678 for (i = 0; i < ARRAY_SIZE(firewall_table); i++) { 679 sprintf(name, "%s", firewall_table[i].prop_name); 680 ret = fdtdec_get_int_array(blob, child, name, 681 start_end, 2); 682 if (ret) { 683 sprintf(name, "altr,%s", firewall_table[i].prop_name); 684 ret = fdtdec_get_int_array(blob, child, name, 685 start_end, 2); 686 if (ret) 687 continue; 688 } 689 690 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) | 691 (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB), 692 firewall_table[i].cfg_addr); 693 setbits_le32(firewall_table[i].en_addr, 694 firewall_table[i].en_bit); 695 } 696 697 return 0; 698 } 699 700 int ddr_calibration_sequence(void) 701 { 702 WATCHDOG_RESET(); 703 704 /* Check to see if SDRAM cal was success */ 705 if (sdram_startup()) { 706 puts("DDRCAL: Failed\n"); 707 return -EPERM; 708 } 709 710 puts("DDRCAL: Success\n"); 711 712 WATCHDOG_RESET(); 713 714 /* initialize the MMR register */ 715 sdram_mmr_init(); 716 717 /* assigning the SDRAM size */ 718 u64 size = sdram_size_calc(); 719 720 /* 721 * If size is less than zero, this is invalid/weird value from 722 * calculation, use default Config size. 723 * Up to 2GB is supported, 2GB would be used if more than that. 724 */ 725 if (size <= 0) 726 gd->ram_size = PHYS_SDRAM_1_SIZE; 727 else if (DDR_SIZE_2GB_HEX <= size) 728 gd->ram_size = DDR_SIZE_2GB_HEX; 729 else 730 gd->ram_size = (u32)size; 731 732 /* setup the dram info within bd */ 733 dram_init_banksize(); 734 735 if (of_sdram_firewall_setup(gd->fdt_blob)) 736 puts("FW: Error Configuring Firewall\n"); 737 738 if (sdram_is_ecc_enabled()) 739 sdram_init_ecc_bits(gd->ram_size); 740 741 return 0; 742 } 743