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821aa191 |
| 15-Mar-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'efi-2019-04-rc4-3' of https://github.com/xypron2/u-boot Pull request for UEFI system for v2019.04-rc4 Fix an error with the serial communication on boards with a very sma
Merge tag 'efi-2019-04-rc4-3' of https://github.com/xypron2/u-boot Pull request for UEFI system for v2019.04-rc4 Fix an error with the serial communication on boards with a very small UART buffer which leads to a stalled system. Provide an X86 reset driver for the UEFI runtime. Fix a problem with parallel builds.
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9659eb46 |
| 14-Mar-2019 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-samsung
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116a3a1a |
| 12-Mar-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'efi-2019-04-rc4-2' of https://github.com/xypron2/u-boot Pull request for UEFI system for v2019.04-rc4 Fix an error with the serial communication on boards with a very sma
Merge tag 'efi-2019-04-rc4-2' of https://github.com/xypron2/u-boot Pull request for UEFI system for v2019.04-rc4 Fix an error with the serial communication on boards with a very small UART buffer which leads to a stalled system. Provide an X86 reset driver for the UEFI runtime.
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2e8092d9 |
| 11-Mar-2019 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-sunxi - axp818 fix - fix warnings for ethernet clock code
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6a08213d |
| 11-Mar-2019 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86 - ACPI changes and fixes to Intel Tangier/Edison - i8254 beeper fixes
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19c8c9c1 |
| 10-Mar-2019 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga - Arria10 DRAM fixes and Gen5 cache fixes
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88c3bb49 |
| 09-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Clean up ddr_setup() Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDR
ddr: socfpga: Clean up ddr_setup() Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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8297dd1d |
| 09-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Clean up EMIF reset The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, s
ddr: socfpga: Clean up EMIF reset The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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ffd1e1a3 |
| 08-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Fix EMIF clear timeout The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Repl
ddr: socfpga: Fix EMIF clear timeout The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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dc3249b9 |
| 06-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Fix newline in debug print on A10 The debug print is missing a newline, add it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel
ddr: socfpga: Fix newline in debug print on A10 The debug print is missing a newline, add it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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71fc4825 |
| 05-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Fix IO in Arria10 DDR driver The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this.
ddr: socfpga: Fix IO in Arria10 DDR driver The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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914bb7ea |
| 13-Jul-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga - Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c Signed-off-by: Tom Rini <trini@konsulko.com>
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07252f6f |
| 28-May-2018 |
Marek Vasut <marex@denx.de> |
ddr: altera: Add ECC DRAM scrubbing support for Arria10 The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with ze
ddr: altera: Add ECC DRAM scrubbing support for Arria10 The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
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93a8ed86 |
| 29-May-2018 |
Marek Vasut <marex@denx.de> |
ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only differ
ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only difference is the part which configures OCRAM as cachable, which doesn't really work as it covers more than the OCRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
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3eceff64 |
| 06-Jun-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-samsung
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8ada17dd |
| 30-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi - Fix a conflict in drivers/spi/atcspi200_spi.c related to the riscv tree fixing a warning. Signed-off-by: Tom Rini <trin
Merge branch 'master' of git://git.denx.de/u-boot-spi - Fix a conflict in drivers/spi/atcspi200_spi.c related to the riscv tree fixing a warning. Signed-off-by: Tom Rini <trini@konsulko.com>
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624d2cae |
| 20-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Fixup SPDX tags in a few new files Signed-off-by: Tom Rini <trini@konsulko.com>
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bea1649c |
| 20-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-sh
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56932e84 |
| 20-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-usb
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904e5469 |
| 20-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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5658a299 |
| 05-Dec-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
ARM: socfpga: Add DDR driver for Arria 10 Add DDR driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
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