1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Based on CAAM driver in drivers/crypto/caam in Linux 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include "fsl_sec.h" 12 #include "jr.h" 13 #include "jobdesc.h" 14 #include "desc_constr.h" 15 #ifdef CONFIG_FSL_CORENET 16 #include <asm/fsl_pamu.h> 17 #endif 18 19 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) 20 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) 21 22 uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { 23 0, 24 #if defined(CONFIG_PPC_C29X) 25 CONFIG_SYS_FSL_SEC_IDX_OFFSET, 26 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET 27 #endif 28 }; 29 30 #define SEC_ADDR(idx) \ 31 ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) 32 33 #define SEC_JR0_ADDR(idx) \ 34 (SEC_ADDR(idx) + \ 35 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) 36 37 struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; 38 39 static inline void start_jr0(uint8_t sec_idx) 40 { 41 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); 42 u32 ctpr_ms = sec_in32(&sec->ctpr_ms); 43 u32 scfgr = sec_in32(&sec->scfgr); 44 45 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) { 46 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or 47 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1 48 */ 49 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) || 50 (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) && 51 (scfgr & SEC_SCFGR_VIRT_EN))) 52 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); 53 } else { 54 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ 55 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) 56 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); 57 } 58 } 59 60 static inline void jr_reset_liodn(uint8_t sec_idx) 61 { 62 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); 63 sec_out32(&sec->jrliodnr[0].ls, 0); 64 } 65 66 static inline void jr_disable_irq(uint8_t sec_idx) 67 { 68 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); 69 uint32_t jrcfg = sec_in32(®s->jrcfg1); 70 71 jrcfg = jrcfg | JR_INTMASK; 72 73 sec_out32(®s->jrcfg1, jrcfg); 74 } 75 76 static void jr_initregs(uint8_t sec_idx) 77 { 78 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); 79 struct jobring *jr = &jr0[sec_idx]; 80 phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); 81 phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); 82 83 #ifdef CONFIG_PHYS_64BIT 84 sec_out32(®s->irba_h, ip_base >> 32); 85 #else 86 sec_out32(®s->irba_h, 0x0); 87 #endif 88 sec_out32(®s->irba_l, (uint32_t)ip_base); 89 #ifdef CONFIG_PHYS_64BIT 90 sec_out32(®s->orba_h, op_base >> 32); 91 #else 92 sec_out32(®s->orba_h, 0x0); 93 #endif 94 sec_out32(®s->orba_l, (uint32_t)op_base); 95 sec_out32(®s->ors, JR_SIZE); 96 sec_out32(®s->irs, JR_SIZE); 97 98 if (!jr->irq) 99 jr_disable_irq(sec_idx); 100 } 101 102 static int jr_init(uint8_t sec_idx) 103 { 104 struct jobring *jr = &jr0[sec_idx]; 105 106 memset(jr, 0, sizeof(struct jobring)); 107 108 jr->jq_id = DEFAULT_JR_ID; 109 jr->irq = DEFAULT_IRQ; 110 111 #ifdef CONFIG_FSL_CORENET 112 jr->liodn = DEFAULT_JR_LIODN; 113 #endif 114 jr->size = JR_SIZE; 115 jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, 116 JR_SIZE * sizeof(dma_addr_t)); 117 if (!jr->input_ring) 118 return -1; 119 120 jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring), 121 ARCH_DMA_MINALIGN); 122 jr->output_ring = 123 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size); 124 if (!jr->output_ring) 125 return -1; 126 127 memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); 128 memset(jr->output_ring, 0, jr->op_size); 129 130 start_jr0(sec_idx); 131 132 jr_initregs(sec_idx); 133 134 return 0; 135 } 136 137 static int jr_sw_cleanup(uint8_t sec_idx) 138 { 139 struct jobring *jr = &jr0[sec_idx]; 140 141 jr->head = 0; 142 jr->tail = 0; 143 jr->read_idx = 0; 144 jr->write_idx = 0; 145 memset(jr->info, 0, sizeof(jr->info)); 146 memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t)); 147 memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); 148 149 return 0; 150 } 151 152 static int jr_hw_reset(uint8_t sec_idx) 153 { 154 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); 155 uint32_t timeout = 100000; 156 uint32_t jrint, jrcr; 157 158 sec_out32(®s->jrcr, JRCR_RESET); 159 do { 160 jrint = sec_in32(®s->jrint); 161 } while (((jrint & JRINT_ERR_HALT_MASK) == 162 JRINT_ERR_HALT_INPROGRESS) && --timeout); 163 164 jrint = sec_in32(®s->jrint); 165 if (((jrint & JRINT_ERR_HALT_MASK) != 166 JRINT_ERR_HALT_INPROGRESS) && timeout == 0) 167 return -1; 168 169 timeout = 100000; 170 sec_out32(®s->jrcr, JRCR_RESET); 171 do { 172 jrcr = sec_in32(®s->jrcr); 173 } while ((jrcr & JRCR_RESET) && --timeout); 174 175 if (timeout == 0) 176 return -1; 177 178 return 0; 179 } 180 181 /* -1 --- error, can't enqueue -- no space available */ 182 static int jr_enqueue(uint32_t *desc_addr, 183 void (*callback)(uint32_t status, void *arg), 184 void *arg, uint8_t sec_idx) 185 { 186 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); 187 struct jobring *jr = &jr0[sec_idx]; 188 int head = jr->head; 189 uint32_t desc_word; 190 int length = desc_len(desc_addr); 191 int i; 192 #ifdef CONFIG_PHYS_64BIT 193 uint32_t *addr_hi, *addr_lo; 194 #endif 195 196 /* The descriptor must be submitted to SEC block as per endianness 197 * of the SEC Block. 198 * So, if the endianness of Core and SEC block is different, each word 199 * of the descriptor will be byte-swapped. 200 */ 201 for (i = 0; i < length; i++) { 202 desc_word = desc_addr[i]; 203 sec_out32((uint32_t *)&desc_addr[i], desc_word); 204 } 205 206 phys_addr_t desc_phys_addr = virt_to_phys(desc_addr); 207 208 jr->info[head].desc_phys_addr = desc_phys_addr; 209 jr->info[head].callback = (void *)callback; 210 jr->info[head].arg = arg; 211 jr->info[head].op_done = 0; 212 213 unsigned long start = (unsigned long)&jr->info[head] & 214 ~(ARCH_DMA_MINALIGN - 1); 215 unsigned long end = ALIGN((unsigned long)&jr->info[head] + 216 sizeof(struct jr_info), ARCH_DMA_MINALIGN); 217 flush_dcache_range(start, end); 218 219 #ifdef CONFIG_PHYS_64BIT 220 /* Write the 64 bit Descriptor address on Input Ring. 221 * The 32 bit hign and low part of the address will 222 * depend on endianness of SEC block. 223 */ 224 #ifdef CONFIG_SYS_FSL_SEC_LE 225 addr_lo = (uint32_t *)(&jr->input_ring[head]); 226 addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1; 227 #elif defined(CONFIG_SYS_FSL_SEC_BE) 228 addr_hi = (uint32_t *)(&jr->input_ring[head]); 229 addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1; 230 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ 231 232 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32)); 233 sec_out32(addr_lo, (uint32_t)(desc_phys_addr)); 234 235 #else 236 /* Write the 32 bit Descriptor address on Input Ring. */ 237 sec_out32(&jr->input_ring[head], desc_phys_addr); 238 #endif /* ifdef CONFIG_PHYS_64BIT */ 239 240 start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); 241 end = ALIGN((unsigned long)&jr->input_ring[head] + 242 sizeof(dma_addr_t), ARCH_DMA_MINALIGN); 243 flush_dcache_range(start, end); 244 245 jr->head = (head + 1) & (jr->size - 1); 246 247 /* Invalidate output ring */ 248 start = (unsigned long)jr->output_ring & 249 ~(ARCH_DMA_MINALIGN - 1); 250 end = ALIGN((unsigned long)jr->output_ring + jr->op_size, 251 ARCH_DMA_MINALIGN); 252 invalidate_dcache_range(start, end); 253 254 sec_out32(®s->irja, 1); 255 256 return 0; 257 } 258 259 static int jr_dequeue(int sec_idx) 260 { 261 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); 262 struct jobring *jr = &jr0[sec_idx]; 263 int head = jr->head; 264 int tail = jr->tail; 265 int idx, i, found; 266 void (*callback)(uint32_t status, void *arg); 267 void *arg = NULL; 268 #ifdef CONFIG_PHYS_64BIT 269 uint32_t *addr_hi, *addr_lo; 270 #else 271 uint32_t *addr; 272 #endif 273 274 while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail, 275 jr->size)) { 276 277 found = 0; 278 279 phys_addr_t op_desc; 280 #ifdef CONFIG_PHYS_64BIT 281 /* Read the 64 bit Descriptor address from Output Ring. 282 * The 32 bit hign and low part of the address will 283 * depend on endianness of SEC block. 284 */ 285 #ifdef CONFIG_SYS_FSL_SEC_LE 286 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc); 287 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1; 288 #elif defined(CONFIG_SYS_FSL_SEC_BE) 289 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc); 290 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1; 291 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ 292 293 op_desc = ((u64)sec_in32(addr_hi) << 32) | 294 ((u64)sec_in32(addr_lo)); 295 296 #else 297 /* Read the 32 bit Descriptor address from Output Ring. */ 298 addr = (uint32_t *)&jr->output_ring[jr->tail].desc; 299 op_desc = sec_in32(addr); 300 #endif /* ifdef CONFIG_PHYS_64BIT */ 301 302 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status); 303 304 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) { 305 idx = (tail + i) & (jr->size - 1); 306 if (op_desc == jr->info[idx].desc_phys_addr) { 307 found = 1; 308 break; 309 } 310 } 311 312 /* Error condition if match not found */ 313 if (!found) 314 return -1; 315 316 jr->info[idx].op_done = 1; 317 callback = (void *)jr->info[idx].callback; 318 arg = jr->info[idx].arg; 319 320 /* When the job on tail idx gets done, increment 321 * tail till the point where job completed out of oredr has 322 * been taken into account 323 */ 324 if (idx == tail) 325 do { 326 tail = (tail + 1) & (jr->size - 1); 327 } while (jr->info[tail].op_done); 328 329 jr->tail = tail; 330 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1); 331 332 sec_out32(®s->orjr, 1); 333 jr->info[idx].op_done = 0; 334 335 callback(status, arg); 336 } 337 338 return 0; 339 } 340 341 static void desc_done(uint32_t status, void *arg) 342 { 343 struct result *x = arg; 344 x->status = status; 345 caam_jr_strstatus(status); 346 x->done = 1; 347 } 348 349 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) 350 { 351 unsigned long long timeval = get_ticks(); 352 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); 353 struct result op; 354 int ret = 0; 355 356 memset(&op, 0, sizeof(op)); 357 358 ret = jr_enqueue(desc, desc_done, &op, sec_idx); 359 if (ret) { 360 debug("Error in SEC enq\n"); 361 ret = JQ_ENQ_ERR; 362 goto out; 363 } 364 365 timeval = get_ticks(); 366 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); 367 while (op.done != 1) { 368 ret = jr_dequeue(sec_idx); 369 if (ret) { 370 debug("Error in SEC deq\n"); 371 ret = JQ_DEQ_ERR; 372 goto out; 373 } 374 375 if ((get_ticks() - timeval) > timeout) { 376 debug("SEC Dequeue timed out\n"); 377 ret = JQ_DEQ_TO_ERR; 378 goto out; 379 } 380 } 381 382 if (op.status) { 383 debug("Error %x\n", op.status); 384 ret = op.status; 385 } 386 out: 387 return ret; 388 } 389 390 int run_descriptor_jr(uint32_t *desc) 391 { 392 return run_descriptor_jr_idx(desc, 0); 393 } 394 395 static inline int jr_reset_sec(uint8_t sec_idx) 396 { 397 if (jr_hw_reset(sec_idx) < 0) 398 return -1; 399 400 /* Clean up the jobring structure maintained by software */ 401 jr_sw_cleanup(sec_idx); 402 403 return 0; 404 } 405 406 int jr_reset(void) 407 { 408 return jr_reset_sec(0); 409 } 410 411 static inline int sec_reset_idx(uint8_t sec_idx) 412 { 413 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); 414 uint32_t mcfgr = sec_in32(&sec->mcfgr); 415 uint32_t timeout = 100000; 416 417 mcfgr |= MCFGR_SWRST; 418 sec_out32(&sec->mcfgr, mcfgr); 419 420 mcfgr |= MCFGR_DMA_RST; 421 sec_out32(&sec->mcfgr, mcfgr); 422 do { 423 mcfgr = sec_in32(&sec->mcfgr); 424 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout); 425 426 if (timeout == 0) 427 return -1; 428 429 timeout = 100000; 430 do { 431 mcfgr = sec_in32(&sec->mcfgr); 432 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout); 433 434 if (timeout == 0) 435 return -1; 436 437 return 0; 438 } 439 440 static int instantiate_rng(uint8_t sec_idx) 441 { 442 struct result op; 443 u32 *desc; 444 u32 rdsta_val; 445 int ret = 0; 446 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); 447 struct rng4tst __iomem *rng = 448 (struct rng4tst __iomem *)&sec->rng; 449 450 memset(&op, 0, sizeof(struct result)); 451 452 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6); 453 if (!desc) { 454 printf("cannot allocate RNG init descriptor memory\n"); 455 return -1; 456 } 457 458 inline_cnstr_jobdesc_rng_instantiation(desc); 459 int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN); 460 flush_dcache_range((unsigned long)desc, 461 (unsigned long)desc + size); 462 463 ret = run_descriptor_jr_idx(desc, sec_idx); 464 465 if (ret) 466 printf("RNG: Instantiation failed with error %x\n", ret); 467 468 rdsta_val = sec_in32(&rng->rdsta); 469 if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED)) 470 return -1; 471 472 return ret; 473 } 474 475 int sec_reset(void) 476 { 477 return sec_reset_idx(0); 478 } 479 480 static u8 get_rng_vid(uint8_t sec_idx) 481 { 482 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); 483 u32 cha_vid = sec_in32(&sec->chavid_ls); 484 485 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT; 486 } 487 488 /* 489 * By default, the TRNG runs for 200 clocks per sample; 490 * 1200 clocks per sample generates better entropy. 491 */ 492 static void kick_trng(int ent_delay, uint8_t sec_idx) 493 { 494 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); 495 struct rng4tst __iomem *rng = 496 (struct rng4tst __iomem *)&sec->rng; 497 u32 val; 498 499 /* put RNG4 into program mode */ 500 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM); 501 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the 502 * length (in system clocks) of each Entropy sample taken 503 * */ 504 val = sec_in32(&rng->rtsdctl); 505 val = (val & ~RTSDCTL_ENT_DLY_MASK) | 506 (ent_delay << RTSDCTL_ENT_DLY_SHIFT); 507 sec_out32(&rng->rtsdctl, val); 508 /* min. freq. count, equal to 1/4 of the entropy sample length */ 509 sec_out32(&rng->rtfreqmin, ent_delay >> 2); 510 /* disable maximum frequency count */ 511 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE); 512 /* 513 * select raw sampling in both entropy shifter 514 * and statistical checker 515 */ 516 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC); 517 /* put RNG4 into run mode */ 518 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); 519 } 520 521 static int rng_init(uint8_t sec_idx) 522 { 523 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN; 524 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); 525 struct rng4tst __iomem *rng = 526 (struct rng4tst __iomem *)&sec->rng; 527 528 u32 rdsta = sec_in32(&rng->rdsta); 529 530 /* Check if RNG state 0 handler is already instantiated */ 531 if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) 532 return 0; 533 534 do { 535 /* 536 * If either of the SH's were instantiated by somebody else 537 * then it is assumed that the entropy 538 * parameters are properly set and thus the function 539 * setting these (kick_trng(...)) is skipped. 540 * Also, if a handle was instantiated, do not change 541 * the TRNG parameters. 542 */ 543 kick_trng(ent_delay, sec_idx); 544 ent_delay += 400; 545 /* 546 * if instantiate_rng(...) fails, the loop will rerun 547 * and the kick_trng(...) function will modfiy the 548 * upper and lower limits of the entropy sampling 549 * interval, leading to a sucessful initialization of 550 * the RNG. 551 */ 552 ret = instantiate_rng(sec_idx); 553 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); 554 if (ret) { 555 printf("RNG: Failed to instantiate RNG\n"); 556 return ret; 557 } 558 559 /* Enable RDB bit so that RNG works faster */ 560 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE); 561 562 return ret; 563 } 564 565 int sec_init_idx(uint8_t sec_idx) 566 { 567 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); 568 uint32_t mcr = sec_in32(&sec->mcfgr); 569 int ret = 0; 570 571 #ifdef CONFIG_FSL_CORENET 572 uint32_t liodnr; 573 uint32_t liodn_ns; 574 uint32_t liodn_s; 575 #endif 576 577 if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) { 578 printf("SEC initialization failed\n"); 579 return -1; 580 } 581 582 /* 583 * Modifying CAAM Read/Write Attributes 584 * For LS2080A 585 * For AXI Write - Cacheable, Write Back, Write allocate 586 * For AXI Read - Cacheable, Read allocate 587 * Only For LS2080a, to solve CAAM coherency issues 588 */ 589 #ifdef CONFIG_LS2080A 590 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); 591 mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); 592 #else 593 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); 594 #endif 595 596 #ifdef CONFIG_PHYS_64BIT 597 mcr |= (1 << MCFGR_PS_SHIFT); 598 #endif 599 sec_out32(&sec->mcfgr, mcr); 600 601 #ifdef CONFIG_FSL_CORENET 602 liodnr = sec_in32(&sec->jrliodnr[0].ls); 603 liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; 604 liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; 605 #endif 606 607 ret = jr_init(sec_idx); 608 if (ret < 0) { 609 printf("SEC initialization failed\n"); 610 return -1; 611 } 612 613 #ifdef CONFIG_FSL_CORENET 614 ret = sec_config_pamu_table(liodn_ns, liodn_s); 615 if (ret < 0) 616 return -1; 617 618 pamu_enable(); 619 #endif 620 621 if (get_rng_vid(sec_idx) >= 4) { 622 if (rng_init(sec_idx) < 0) { 623 printf("SEC%u: RNG instantiation failed\n", sec_idx); 624 return -1; 625 } 626 printf("SEC%u: RNG instantiated\n", sec_idx); 627 } 628 629 return ret; 630 } 631 632 int sec_init(void) 633 { 634 return sec_init_idx(0); 635 } 636