1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 *
5 * Based on CAAM driver in drivers/crypto/caam in Linux
6 */
7
8 #include <common.h>
9 #include <malloc.h>
10 #include "fsl_sec.h"
11 #include "jr.h"
12 #include "jobdesc.h"
13 #include "desc_constr.h"
14 #ifdef CONFIG_FSL_CORENET
15 #include <asm/fsl_pamu.h>
16 #endif
17
18 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
19 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
20
21 uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
22 0,
23 #if defined(CONFIG_ARCH_C29X)
24 CONFIG_SYS_FSL_SEC_IDX_OFFSET,
25 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
26 #endif
27 };
28
29 #define SEC_ADDR(idx) \
30 ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
31
32 #define SEC_JR0_ADDR(idx) \
33 (SEC_ADDR(idx) + \
34 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
35
36 struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
37
start_jr0(uint8_t sec_idx)38 static inline void start_jr0(uint8_t sec_idx)
39 {
40 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
41 u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
42 u32 scfgr = sec_in32(&sec->scfgr);
43
44 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
45 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
46 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
47 */
48 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
49 (scfgr & SEC_SCFGR_VIRT_EN))
50 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
51 } else {
52 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
53 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
54 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
55 }
56 }
57
jr_reset_liodn(uint8_t sec_idx)58 static inline void jr_reset_liodn(uint8_t sec_idx)
59 {
60 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
61 sec_out32(&sec->jrliodnr[0].ls, 0);
62 }
63
jr_disable_irq(uint8_t sec_idx)64 static inline void jr_disable_irq(uint8_t sec_idx)
65 {
66 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
67 uint32_t jrcfg = sec_in32(®s->jrcfg1);
68
69 jrcfg = jrcfg | JR_INTMASK;
70
71 sec_out32(®s->jrcfg1, jrcfg);
72 }
73
jr_initregs(uint8_t sec_idx)74 static void jr_initregs(uint8_t sec_idx)
75 {
76 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
77 struct jobring *jr = &jr0[sec_idx];
78 phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
79 phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
80
81 #ifdef CONFIG_PHYS_64BIT
82 sec_out32(®s->irba_h, ip_base >> 32);
83 #else
84 sec_out32(®s->irba_h, 0x0);
85 #endif
86 sec_out32(®s->irba_l, (uint32_t)ip_base);
87 #ifdef CONFIG_PHYS_64BIT
88 sec_out32(®s->orba_h, op_base >> 32);
89 #else
90 sec_out32(®s->orba_h, 0x0);
91 #endif
92 sec_out32(®s->orba_l, (uint32_t)op_base);
93 sec_out32(®s->ors, JR_SIZE);
94 sec_out32(®s->irs, JR_SIZE);
95
96 if (!jr->irq)
97 jr_disable_irq(sec_idx);
98 }
99
jr_init(uint8_t sec_idx)100 static int jr_init(uint8_t sec_idx)
101 {
102 struct jobring *jr = &jr0[sec_idx];
103
104 memset(jr, 0, sizeof(struct jobring));
105
106 jr->jq_id = DEFAULT_JR_ID;
107 jr->irq = DEFAULT_IRQ;
108
109 #ifdef CONFIG_FSL_CORENET
110 jr->liodn = DEFAULT_JR_LIODN;
111 #endif
112 jr->size = JR_SIZE;
113 jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
114 JR_SIZE * sizeof(dma_addr_t));
115 if (!jr->input_ring)
116 return -1;
117
118 jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
119 ARCH_DMA_MINALIGN);
120 jr->output_ring =
121 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
122 if (!jr->output_ring)
123 return -1;
124
125 memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
126 memset(jr->output_ring, 0, jr->op_size);
127
128 start_jr0(sec_idx);
129
130 jr_initregs(sec_idx);
131
132 return 0;
133 }
134
jr_sw_cleanup(uint8_t sec_idx)135 static int jr_sw_cleanup(uint8_t sec_idx)
136 {
137 struct jobring *jr = &jr0[sec_idx];
138
139 jr->head = 0;
140 jr->tail = 0;
141 jr->read_idx = 0;
142 jr->write_idx = 0;
143 memset(jr->info, 0, sizeof(jr->info));
144 memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
145 memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
146
147 return 0;
148 }
149
jr_hw_reset(uint8_t sec_idx)150 static int jr_hw_reset(uint8_t sec_idx)
151 {
152 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
153 uint32_t timeout = 100000;
154 uint32_t jrint, jrcr;
155
156 sec_out32(®s->jrcr, JRCR_RESET);
157 do {
158 jrint = sec_in32(®s->jrint);
159 } while (((jrint & JRINT_ERR_HALT_MASK) ==
160 JRINT_ERR_HALT_INPROGRESS) && --timeout);
161
162 jrint = sec_in32(®s->jrint);
163 if (((jrint & JRINT_ERR_HALT_MASK) !=
164 JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
165 return -1;
166
167 timeout = 100000;
168 sec_out32(®s->jrcr, JRCR_RESET);
169 do {
170 jrcr = sec_in32(®s->jrcr);
171 } while ((jrcr & JRCR_RESET) && --timeout);
172
173 if (timeout == 0)
174 return -1;
175
176 return 0;
177 }
178
179 /* -1 --- error, can't enqueue -- no space available */
jr_enqueue(uint32_t * desc_addr,void (* callback)(uint32_t status,void * arg),void * arg,uint8_t sec_idx)180 static int jr_enqueue(uint32_t *desc_addr,
181 void (*callback)(uint32_t status, void *arg),
182 void *arg, uint8_t sec_idx)
183 {
184 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
185 struct jobring *jr = &jr0[sec_idx];
186 int head = jr->head;
187 uint32_t desc_word;
188 int length = desc_len(desc_addr);
189 int i;
190 #ifdef CONFIG_PHYS_64BIT
191 uint32_t *addr_hi, *addr_lo;
192 #endif
193
194 /* The descriptor must be submitted to SEC block as per endianness
195 * of the SEC Block.
196 * So, if the endianness of Core and SEC block is different, each word
197 * of the descriptor will be byte-swapped.
198 */
199 for (i = 0; i < length; i++) {
200 desc_word = desc_addr[i];
201 sec_out32((uint32_t *)&desc_addr[i], desc_word);
202 }
203
204 phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
205
206 jr->info[head].desc_phys_addr = desc_phys_addr;
207 jr->info[head].callback = (void *)callback;
208 jr->info[head].arg = arg;
209 jr->info[head].op_done = 0;
210
211 unsigned long start = (unsigned long)&jr->info[head] &
212 ~(ARCH_DMA_MINALIGN - 1);
213 unsigned long end = ALIGN((unsigned long)&jr->info[head] +
214 sizeof(struct jr_info), ARCH_DMA_MINALIGN);
215 flush_dcache_range(start, end);
216
217 #ifdef CONFIG_PHYS_64BIT
218 /* Write the 64 bit Descriptor address on Input Ring.
219 * The 32 bit hign and low part of the address will
220 * depend on endianness of SEC block.
221 */
222 #ifdef CONFIG_SYS_FSL_SEC_LE
223 addr_lo = (uint32_t *)(&jr->input_ring[head]);
224 addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
225 #elif defined(CONFIG_SYS_FSL_SEC_BE)
226 addr_hi = (uint32_t *)(&jr->input_ring[head]);
227 addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
228 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
229
230 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
231 sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
232
233 #else
234 /* Write the 32 bit Descriptor address on Input Ring. */
235 sec_out32(&jr->input_ring[head], desc_phys_addr);
236 #endif /* ifdef CONFIG_PHYS_64BIT */
237
238 start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
239 end = ALIGN((unsigned long)&jr->input_ring[head] +
240 sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
241 flush_dcache_range(start, end);
242
243 jr->head = (head + 1) & (jr->size - 1);
244
245 /* Invalidate output ring */
246 start = (unsigned long)jr->output_ring &
247 ~(ARCH_DMA_MINALIGN - 1);
248 end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
249 ARCH_DMA_MINALIGN);
250 invalidate_dcache_range(start, end);
251
252 sec_out32(®s->irja, 1);
253
254 return 0;
255 }
256
jr_dequeue(int sec_idx)257 static int jr_dequeue(int sec_idx)
258 {
259 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
260 struct jobring *jr = &jr0[sec_idx];
261 int head = jr->head;
262 int tail = jr->tail;
263 int idx, i, found;
264 void (*callback)(uint32_t status, void *arg);
265 void *arg = NULL;
266 #ifdef CONFIG_PHYS_64BIT
267 uint32_t *addr_hi, *addr_lo;
268 #else
269 uint32_t *addr;
270 #endif
271
272 while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail,
273 jr->size)) {
274
275 found = 0;
276
277 phys_addr_t op_desc;
278 #ifdef CONFIG_PHYS_64BIT
279 /* Read the 64 bit Descriptor address from Output Ring.
280 * The 32 bit hign and low part of the address will
281 * depend on endianness of SEC block.
282 */
283 #ifdef CONFIG_SYS_FSL_SEC_LE
284 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
285 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
286 #elif defined(CONFIG_SYS_FSL_SEC_BE)
287 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
288 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
289 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
290
291 op_desc = ((u64)sec_in32(addr_hi) << 32) |
292 ((u64)sec_in32(addr_lo));
293
294 #else
295 /* Read the 32 bit Descriptor address from Output Ring. */
296 addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
297 op_desc = sec_in32(addr);
298 #endif /* ifdef CONFIG_PHYS_64BIT */
299
300 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
301
302 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
303 idx = (tail + i) & (jr->size - 1);
304 if (op_desc == jr->info[idx].desc_phys_addr) {
305 found = 1;
306 break;
307 }
308 }
309
310 /* Error condition if match not found */
311 if (!found)
312 return -1;
313
314 jr->info[idx].op_done = 1;
315 callback = (void *)jr->info[idx].callback;
316 arg = jr->info[idx].arg;
317
318 /* When the job on tail idx gets done, increment
319 * tail till the point where job completed out of oredr has
320 * been taken into account
321 */
322 if (idx == tail)
323 do {
324 tail = (tail + 1) & (jr->size - 1);
325 } while (jr->info[tail].op_done);
326
327 jr->tail = tail;
328 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
329
330 sec_out32(®s->orjr, 1);
331 jr->info[idx].op_done = 0;
332
333 callback(status, arg);
334 }
335
336 return 0;
337 }
338
desc_done(uint32_t status,void * arg)339 static void desc_done(uint32_t status, void *arg)
340 {
341 struct result *x = arg;
342 x->status = status;
343 #ifndef CONFIG_SPL_BUILD
344 caam_jr_strstatus(status);
345 #endif
346 x->done = 1;
347 }
348
run_descriptor_jr_idx(uint32_t * desc,uint8_t sec_idx)349 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
350 {
351 unsigned long long timeval = get_ticks();
352 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
353 struct result op;
354 int ret = 0;
355
356 memset(&op, 0, sizeof(op));
357
358 ret = jr_enqueue(desc, desc_done, &op, sec_idx);
359 if (ret) {
360 debug("Error in SEC enq\n");
361 ret = JQ_ENQ_ERR;
362 goto out;
363 }
364
365 timeval = get_ticks();
366 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
367 while (op.done != 1) {
368 ret = jr_dequeue(sec_idx);
369 if (ret) {
370 debug("Error in SEC deq\n");
371 ret = JQ_DEQ_ERR;
372 goto out;
373 }
374
375 if ((get_ticks() - timeval) > timeout) {
376 debug("SEC Dequeue timed out\n");
377 ret = JQ_DEQ_TO_ERR;
378 goto out;
379 }
380 }
381
382 if (op.status) {
383 debug("Error %x\n", op.status);
384 ret = op.status;
385 }
386 out:
387 return ret;
388 }
389
run_descriptor_jr(uint32_t * desc)390 int run_descriptor_jr(uint32_t *desc)
391 {
392 return run_descriptor_jr_idx(desc, 0);
393 }
394
jr_reset_sec(uint8_t sec_idx)395 static inline int jr_reset_sec(uint8_t sec_idx)
396 {
397 if (jr_hw_reset(sec_idx) < 0)
398 return -1;
399
400 /* Clean up the jobring structure maintained by software */
401 jr_sw_cleanup(sec_idx);
402
403 return 0;
404 }
405
jr_reset(void)406 int jr_reset(void)
407 {
408 return jr_reset_sec(0);
409 }
410
sec_reset_idx(uint8_t sec_idx)411 static inline int sec_reset_idx(uint8_t sec_idx)
412 {
413 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
414 uint32_t mcfgr = sec_in32(&sec->mcfgr);
415 uint32_t timeout = 100000;
416
417 mcfgr |= MCFGR_SWRST;
418 sec_out32(&sec->mcfgr, mcfgr);
419
420 mcfgr |= MCFGR_DMA_RST;
421 sec_out32(&sec->mcfgr, mcfgr);
422 do {
423 mcfgr = sec_in32(&sec->mcfgr);
424 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
425
426 if (timeout == 0)
427 return -1;
428
429 timeout = 100000;
430 do {
431 mcfgr = sec_in32(&sec->mcfgr);
432 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
433
434 if (timeout == 0)
435 return -1;
436
437 return 0;
438 }
sec_reset(void)439 int sec_reset(void)
440 {
441 return sec_reset_idx(0);
442 }
443 #ifndef CONFIG_SPL_BUILD
instantiate_rng(uint8_t sec_idx)444 static int instantiate_rng(uint8_t sec_idx)
445 {
446 u32 *desc;
447 u32 rdsta_val;
448 int ret = 0, sh_idx, size;
449 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
450 struct rng4tst __iomem *rng =
451 (struct rng4tst __iomem *)&sec->rng;
452
453 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
454 if (!desc) {
455 printf("cannot allocate RNG init descriptor memory\n");
456 return -1;
457 }
458
459 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
460 /*
461 * If the corresponding bit is set, this state handle
462 * was initialized by somebody else, so it's left alone.
463 */
464 rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
465 if (rdsta_val & (1 << sh_idx))
466 continue;
467
468 inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx);
469 size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
470 flush_dcache_range((unsigned long)desc,
471 (unsigned long)desc + size);
472
473 ret = run_descriptor_jr_idx(desc, sec_idx);
474
475 if (ret)
476 printf("RNG: Instantiation failed with error 0x%x\n",
477 ret);
478
479 rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
480 if (!(rdsta_val & (1 << sh_idx))) {
481 free(desc);
482 return -1;
483 }
484
485 memset(desc, 0, sizeof(uint32_t) * 6);
486 }
487
488 free(desc);
489
490 return ret;
491 }
492
get_rng_vid(uint8_t sec_idx)493 static u8 get_rng_vid(uint8_t sec_idx)
494 {
495 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
496 u32 cha_vid = sec_in32(&sec->chavid_ls);
497
498 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
499 }
500
501 /*
502 * By default, the TRNG runs for 200 clocks per sample;
503 * 1200 clocks per sample generates better entropy.
504 */
kick_trng(int ent_delay,uint8_t sec_idx)505 static void kick_trng(int ent_delay, uint8_t sec_idx)
506 {
507 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
508 struct rng4tst __iomem *rng =
509 (struct rng4tst __iomem *)&sec->rng;
510 u32 val;
511
512 /* put RNG4 into program mode */
513 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
514 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
515 * length (in system clocks) of each Entropy sample taken
516 * */
517 val = sec_in32(&rng->rtsdctl);
518 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
519 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
520 sec_out32(&rng->rtsdctl, val);
521 /* min. freq. count, equal to 1/4 of the entropy sample length */
522 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
523 /* disable maximum frequency count */
524 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
525 /*
526 * select raw sampling in both entropy shifter
527 * and statistical checker
528 */
529 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
530 /* put RNG4 into run mode */
531 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
532 }
533
rng_init(uint8_t sec_idx)534 static int rng_init(uint8_t sec_idx)
535 {
536 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
537 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
538 struct rng4tst __iomem *rng =
539 (struct rng4tst __iomem *)&sec->rng;
540 u32 inst_handles;
541
542 do {
543 inst_handles = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
544
545 /*
546 * If either of the SH's were instantiated by somebody else
547 * then it is assumed that the entropy
548 * parameters are properly set and thus the function
549 * setting these (kick_trng(...)) is skipped.
550 * Also, if a handle was instantiated, do not change
551 * the TRNG parameters.
552 */
553 if (!inst_handles) {
554 kick_trng(ent_delay, sec_idx);
555 ent_delay += 400;
556 }
557 /*
558 * if instantiate_rng(...) fails, the loop will rerun
559 * and the kick_trng(...) function will modfiy the
560 * upper and lower limits of the entropy sampling
561 * interval, leading to a sucessful initialization of
562 * the RNG.
563 */
564 ret = instantiate_rng(sec_idx);
565 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
566 if (ret) {
567 printf("RNG: Failed to instantiate RNG\n");
568 return ret;
569 }
570
571 /* Enable RDB bit so that RNG works faster */
572 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
573
574 return ret;
575 }
576 #endif
sec_init_idx(uint8_t sec_idx)577 int sec_init_idx(uint8_t sec_idx)
578 {
579 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
580 uint32_t mcr = sec_in32(&sec->mcfgr);
581 uint32_t jrown_ns;
582 int i;
583 int ret = 0;
584
585 #ifdef CONFIG_FSL_CORENET
586 uint32_t liodnr;
587 uint32_t liodn_ns;
588 uint32_t liodn_s;
589 #endif
590
591 if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
592 printf("SEC initialization failed\n");
593 return -1;
594 }
595
596 /*
597 * Modifying CAAM Read/Write Attributes
598 * For LS2080A
599 * For AXI Write - Cacheable, Write Back, Write allocate
600 * For AXI Read - Cacheable, Read allocate
601 * Only For LS2080a, to solve CAAM coherency issues
602 */
603 #ifdef CONFIG_ARCH_LS2080A
604 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
605 mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
606 #else
607 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
608 #endif
609
610 #ifdef CONFIG_PHYS_64BIT
611 mcr |= (1 << MCFGR_PS_SHIFT);
612 #endif
613 sec_out32(&sec->mcfgr, mcr);
614
615 #ifdef CONFIG_FSL_CORENET
616 #ifdef CONFIG_SPL_BUILD
617 /*
618 * For SPL Build, Set the Liodns in SEC JR0 for
619 * creating PAMU entries corresponding to these.
620 * For normal build, these are set in set_liodns().
621 */
622 liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
623 liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
624
625 liodnr = sec_in32(&sec->jrliodnr[0].ls) &
626 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
627 liodnr = liodnr |
628 (liodn_ns << JRNSLIODN_SHIFT) |
629 (liodn_s << JRSLIODN_SHIFT);
630 sec_out32(&sec->jrliodnr[0].ls, liodnr);
631 #else
632 liodnr = sec_in32(&sec->jrliodnr[0].ls);
633 liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
634 liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
635 #endif
636 #endif
637
638 /* Set ownership of job rings to non-TrustZone mode by default */
639 for (i = 0; i < ARRAY_SIZE(sec->jrliodnr); i++) {
640 jrown_ns = sec_in32(&sec->jrliodnr[i].ms);
641 jrown_ns |= JROWN_NS | JRMID_NS;
642 sec_out32(&sec->jrliodnr[i].ms, jrown_ns);
643 }
644
645 ret = jr_init(sec_idx);
646 if (ret < 0) {
647 printf("SEC initialization failed\n");
648 return -1;
649 }
650
651 #ifdef CONFIG_FSL_CORENET
652 ret = sec_config_pamu_table(liodn_ns, liodn_s);
653 if (ret < 0)
654 return -1;
655
656 pamu_enable();
657 #endif
658 #ifndef CONFIG_SPL_BUILD
659 if (get_rng_vid(sec_idx) >= 4) {
660 if (rng_init(sec_idx) < 0) {
661 printf("SEC%u: RNG instantiation failed\n", sec_idx);
662 return -1;
663 }
664 printf("SEC%u: RNG instantiated\n", sec_idx);
665 }
666 #endif
667 return ret;
668 }
669
sec_init(void)670 int sec_init(void)
671 {
672 return sec_init_idx(0);
673 }
674