xref: /openbmc/u-boot/drivers/crypto/fsl/jr.c (revision ad5b5801) 
1 /*
2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  *
6  * Based on CAAM driver in drivers/crypto/caam in Linux
7  */
8 
9 #include <common.h>
10 #include <malloc.h>
11 #include "fsl_sec.h"
12 #include "jr.h"
13 #include "jobdesc.h"
14 #include "desc_constr.h"
15 #ifdef CONFIG_FSL_CORENET
16 #include <asm/fsl_pamu.h>
17 #endif
18 
19 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
20 #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
21 
22 struct jobring jr;
23 
24 static inline void start_jr0(void)
25 {
26 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
27 	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
28 	u32 scfgr = sec_in32(&sec->scfgr);
29 
30 	if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
31 		/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
32 		 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
33 		 */
34 		if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
35 		    (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
36 					(scfgr & SEC_SCFGR_VIRT_EN)))
37 			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
38 	} else {
39 		/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
40 		if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
41 			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
42 	}
43 }
44 
45 static inline void jr_reset_liodn(void)
46 {
47 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
48 	sec_out32(&sec->jrliodnr[0].ls, 0);
49 }
50 
51 static inline void jr_disable_irq(void)
52 {
53 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
54 	uint32_t jrcfg = sec_in32(&regs->jrcfg1);
55 
56 	jrcfg = jrcfg | JR_INTMASK;
57 
58 	sec_out32(&regs->jrcfg1, jrcfg);
59 }
60 
61 static void jr_initregs(void)
62 {
63 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
64 	phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
65 	phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
66 
67 #ifdef CONFIG_PHYS_64BIT
68 	sec_out32(&regs->irba_h, ip_base >> 32);
69 #else
70 	sec_out32(&regs->irba_h, 0x0);
71 #endif
72 	sec_out32(&regs->irba_l, (uint32_t)ip_base);
73 #ifdef CONFIG_PHYS_64BIT
74 	sec_out32(&regs->orba_h, op_base >> 32);
75 #else
76 	sec_out32(&regs->orba_h, 0x0);
77 #endif
78 	sec_out32(&regs->orba_l, (uint32_t)op_base);
79 	sec_out32(&regs->ors, JR_SIZE);
80 	sec_out32(&regs->irs, JR_SIZE);
81 
82 	if (!jr.irq)
83 		jr_disable_irq();
84 }
85 
86 static int jr_init(void)
87 {
88 	memset(&jr, 0, sizeof(struct jobring));
89 
90 	jr.jq_id = DEFAULT_JR_ID;
91 	jr.irq = DEFAULT_IRQ;
92 
93 #ifdef CONFIG_FSL_CORENET
94 	jr.liodn = DEFAULT_JR_LIODN;
95 #endif
96 	jr.size = JR_SIZE;
97 	jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
98 				JR_SIZE * sizeof(dma_addr_t));
99 	if (!jr.input_ring)
100 		return -1;
101 
102 	jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
103 			     ARCH_DMA_MINALIGN);
104 	jr.output_ring =
105 	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
106 	if (!jr.output_ring)
107 		return -1;
108 
109 	memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
110 	memset(jr.output_ring, 0, jr.op_size);
111 
112 	start_jr0();
113 
114 	jr_initregs();
115 
116 	return 0;
117 }
118 
119 static int jr_sw_cleanup(void)
120 {
121 	jr.head = 0;
122 	jr.tail = 0;
123 	jr.read_idx = 0;
124 	jr.write_idx = 0;
125 	memset(jr.info, 0, sizeof(jr.info));
126 	memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
127 	memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
128 
129 	return 0;
130 }
131 
132 static int jr_hw_reset(void)
133 {
134 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
135 	uint32_t timeout = 100000;
136 	uint32_t jrint, jrcr;
137 
138 	sec_out32(&regs->jrcr, JRCR_RESET);
139 	do {
140 		jrint = sec_in32(&regs->jrint);
141 	} while (((jrint & JRINT_ERR_HALT_MASK) ==
142 		  JRINT_ERR_HALT_INPROGRESS) && --timeout);
143 
144 	jrint = sec_in32(&regs->jrint);
145 	if (((jrint & JRINT_ERR_HALT_MASK) !=
146 	     JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
147 		return -1;
148 
149 	timeout = 100000;
150 	sec_out32(&regs->jrcr, JRCR_RESET);
151 	do {
152 		jrcr = sec_in32(&regs->jrcr);
153 	} while ((jrcr & JRCR_RESET) && --timeout);
154 
155 	if (timeout == 0)
156 		return -1;
157 
158 	return 0;
159 }
160 
161 /* -1 --- error, can't enqueue -- no space available */
162 static int jr_enqueue(uint32_t *desc_addr,
163 	       void (*callback)(uint32_t status, void *arg),
164 	       void *arg)
165 {
166 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
167 	int head = jr.head;
168 	uint32_t desc_word;
169 	int length = desc_len(desc_addr);
170 	int i;
171 #ifdef CONFIG_PHYS_64BIT
172 	uint32_t *addr_hi, *addr_lo;
173 #endif
174 
175 	/* The descriptor must be submitted to SEC block as per endianness
176 	 * of the SEC Block.
177 	 * So, if the endianness of Core and SEC block is different, each word
178 	 * of the descriptor will be byte-swapped.
179 	 */
180 	for (i = 0; i < length; i++) {
181 		desc_word = desc_addr[i];
182 		sec_out32((uint32_t *)&desc_addr[i], desc_word);
183 	}
184 
185 	phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
186 
187 	if (sec_in32(&regs->irsa) == 0 ||
188 	    CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
189 		return -1;
190 
191 	jr.info[head].desc_phys_addr = desc_phys_addr;
192 	jr.info[head].callback = (void *)callback;
193 	jr.info[head].arg = arg;
194 	jr.info[head].op_done = 0;
195 
196 	unsigned long start = (unsigned long)&jr.info[head] &
197 					~(ARCH_DMA_MINALIGN - 1);
198 	unsigned long end = ALIGN((unsigned long)&jr.info[head] +
199 				  sizeof(struct jr_info), ARCH_DMA_MINALIGN);
200 	flush_dcache_range(start, end);
201 
202 #ifdef CONFIG_PHYS_64BIT
203 	/* Write the 64 bit Descriptor address on Input Ring.
204 	 * The 32 bit hign and low part of the address will
205 	 * depend on endianness of SEC block.
206 	 */
207 #ifdef CONFIG_SYS_FSL_SEC_LE
208 	addr_lo = (uint32_t *)(&jr.input_ring[head]);
209 	addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
210 #elif defined(CONFIG_SYS_FSL_SEC_BE)
211 	addr_hi = (uint32_t *)(&jr.input_ring[head]);
212 	addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
213 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
214 
215 	sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
216 	sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
217 
218 #else
219 	/* Write the 32 bit Descriptor address on Input Ring. */
220 	sec_out32(&jr.input_ring[head], desc_phys_addr);
221 #endif /* ifdef CONFIG_PHYS_64BIT */
222 
223 	start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
224 	end = ALIGN((unsigned long)&jr.input_ring[head] +
225 		     sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
226 	flush_dcache_range(start, end);
227 
228 	jr.head = (head + 1) & (jr.size - 1);
229 
230 	/* Invalidate output ring */
231 	start = (unsigned long)jr.output_ring &
232 					~(ARCH_DMA_MINALIGN - 1);
233 	end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
234 		     ARCH_DMA_MINALIGN);
235 	invalidate_dcache_range(start, end);
236 
237 	sec_out32(&regs->irja, 1);
238 
239 	return 0;
240 }
241 
242 static int jr_dequeue(void)
243 {
244 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
245 	int head = jr.head;
246 	int tail = jr.tail;
247 	int idx, i, found;
248 	void (*callback)(uint32_t status, void *arg);
249 	void *arg = NULL;
250 #ifdef CONFIG_PHYS_64BIT
251 	uint32_t *addr_hi, *addr_lo;
252 #else
253 	uint32_t *addr;
254 #endif
255 
256 	while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
257 
258 		found = 0;
259 
260 		phys_addr_t op_desc;
261 	#ifdef CONFIG_PHYS_64BIT
262 		/* Read the 64 bit Descriptor address from Output Ring.
263 		 * The 32 bit hign and low part of the address will
264 		 * depend on endianness of SEC block.
265 		 */
266 	#ifdef CONFIG_SYS_FSL_SEC_LE
267 		addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
268 		addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
269 	#elif defined(CONFIG_SYS_FSL_SEC_BE)
270 		addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
271 		addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
272 	#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
273 
274 		op_desc = ((u64)sec_in32(addr_hi) << 32) |
275 			  ((u64)sec_in32(addr_lo));
276 
277 	#else
278 		/* Read the 32 bit Descriptor address from Output Ring. */
279 		addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
280 		op_desc = sec_in32(addr);
281 	#endif /* ifdef CONFIG_PHYS_64BIT */
282 
283 		uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
284 
285 		for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
286 			idx = (tail + i) & (jr.size - 1);
287 			if (op_desc == jr.info[idx].desc_phys_addr) {
288 				found = 1;
289 				break;
290 			}
291 		}
292 
293 		/* Error condition if match not found */
294 		if (!found)
295 			return -1;
296 
297 		jr.info[idx].op_done = 1;
298 		callback = (void *)jr.info[idx].callback;
299 		arg = jr.info[idx].arg;
300 
301 		/* When the job on tail idx gets done, increment
302 		 * tail till the point where job completed out of oredr has
303 		 * been taken into account
304 		 */
305 		if (idx == tail)
306 			do {
307 				tail = (tail + 1) & (jr.size - 1);
308 			} while (jr.info[tail].op_done);
309 
310 		jr.tail = tail;
311 		jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
312 
313 		sec_out32(&regs->orjr, 1);
314 		jr.info[idx].op_done = 0;
315 
316 		callback(status, arg);
317 	}
318 
319 	return 0;
320 }
321 
322 static void desc_done(uint32_t status, void *arg)
323 {
324 	struct result *x = arg;
325 	x->status = status;
326 	caam_jr_strstatus(status);
327 	x->done = 1;
328 }
329 
330 int run_descriptor_jr(uint32_t *desc)
331 {
332 	unsigned long long timeval = get_ticks();
333 	unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
334 	struct result op;
335 	int ret = 0;
336 
337 	memset(&op, 0, sizeof(op));
338 
339 	ret = jr_enqueue(desc, desc_done, &op);
340 	if (ret) {
341 		debug("Error in SEC enq\n");
342 		ret = JQ_ENQ_ERR;
343 		goto out;
344 	}
345 
346 	timeval = get_ticks();
347 	timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
348 	while (op.done != 1) {
349 		ret = jr_dequeue();
350 		if (ret) {
351 			debug("Error in SEC deq\n");
352 			ret = JQ_DEQ_ERR;
353 			goto out;
354 		}
355 
356 		if ((get_ticks() - timeval) > timeout) {
357 			debug("SEC Dequeue timed out\n");
358 			ret = JQ_DEQ_TO_ERR;
359 			goto out;
360 		}
361 	}
362 
363 	if (op.status) {
364 		debug("Error %x\n", op.status);
365 		ret = op.status;
366 	}
367 out:
368 	return ret;
369 }
370 
371 int jr_reset(void)
372 {
373 	if (jr_hw_reset() < 0)
374 		return -1;
375 
376 	/* Clean up the jobring structure maintained by software */
377 	jr_sw_cleanup();
378 
379 	return 0;
380 }
381 
382 int sec_reset(void)
383 {
384 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
385 	uint32_t mcfgr = sec_in32(&sec->mcfgr);
386 	uint32_t timeout = 100000;
387 
388 	mcfgr |= MCFGR_SWRST;
389 	sec_out32(&sec->mcfgr, mcfgr);
390 
391 	mcfgr |= MCFGR_DMA_RST;
392 	sec_out32(&sec->mcfgr, mcfgr);
393 	do {
394 		mcfgr = sec_in32(&sec->mcfgr);
395 	} while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
396 
397 	if (timeout == 0)
398 		return -1;
399 
400 	timeout = 100000;
401 	do {
402 		mcfgr = sec_in32(&sec->mcfgr);
403 	} while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
404 
405 	if (timeout == 0)
406 		return -1;
407 
408 	return 0;
409 }
410 
411 static int instantiate_rng(void)
412 {
413 	struct result op;
414 	u32 *desc;
415 	u32 rdsta_val;
416 	int ret = 0;
417 	ccsr_sec_t __iomem *sec =
418 			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
419 	struct rng4tst __iomem *rng =
420 			(struct rng4tst __iomem *)&sec->rng;
421 
422 	memset(&op, 0, sizeof(struct result));
423 
424 	desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
425 	if (!desc) {
426 		printf("cannot allocate RNG init descriptor memory\n");
427 		return -1;
428 	}
429 
430 	inline_cnstr_jobdesc_rng_instantiation(desc);
431 	int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
432 	flush_dcache_range((unsigned long)desc,
433 			   (unsigned long)desc + size);
434 
435 	ret = run_descriptor_jr(desc);
436 
437 	if (ret)
438 		printf("RNG: Instantiation failed with error %x\n", ret);
439 
440 	rdsta_val = sec_in32(&rng->rdsta);
441 	if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
442 		return -1;
443 
444 	return ret;
445 }
446 
447 static u8 get_rng_vid(void)
448 {
449 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
450 	u32 cha_vid = sec_in32(&sec->chavid_ls);
451 
452 	return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
453 }
454 
455 /*
456  * By default, the TRNG runs for 200 clocks per sample;
457  * 1200 clocks per sample generates better entropy.
458  */
459 static void kick_trng(int ent_delay)
460 {
461 	ccsr_sec_t __iomem *sec =
462 			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
463 	struct rng4tst __iomem *rng =
464 			(struct rng4tst __iomem *)&sec->rng;
465 	u32 val;
466 
467 	/* put RNG4 into program mode */
468 	sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
469 	/* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
470 	 * length (in system clocks) of each Entropy sample taken
471 	 * */
472 	val = sec_in32(&rng->rtsdctl);
473 	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
474 	      (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
475 	sec_out32(&rng->rtsdctl, val);
476 	/* min. freq. count, equal to 1/4 of the entropy sample length */
477 	sec_out32(&rng->rtfreqmin, ent_delay >> 2);
478 	/* disable maximum frequency count */
479 	sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
480 	/*
481 	 * select raw sampling in both entropy shifter
482 	 * and statistical checker
483 	 */
484 	sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
485 	/* put RNG4 into run mode */
486 	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
487 }
488 
489 static int rng_init(void)
490 {
491 	int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
492 	ccsr_sec_t __iomem *sec =
493 			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
494 	struct rng4tst __iomem *rng =
495 			(struct rng4tst __iomem *)&sec->rng;
496 
497 	u32 rdsta = sec_in32(&rng->rdsta);
498 
499 	/* Check if RNG state 0 handler is already instantiated */
500 	if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
501 		return 0;
502 
503 	do {
504 		/*
505 		 * If either of the SH's were instantiated by somebody else
506 		 * then it is assumed that the entropy
507 		 * parameters are properly set and thus the function
508 		 * setting these (kick_trng(...)) is skipped.
509 		 * Also, if a handle was instantiated, do not change
510 		 * the TRNG parameters.
511 		 */
512 		kick_trng(ent_delay);
513 		ent_delay += 400;
514 		/*
515 		 * if instantiate_rng(...) fails, the loop will rerun
516 		 * and the kick_trng(...) function will modfiy the
517 		 * upper and lower limits of the entropy sampling
518 		 * interval, leading to a sucessful initialization of
519 		 * the RNG.
520 		 */
521 		ret = instantiate_rng();
522 	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
523 	if (ret) {
524 		printf("RNG: Failed to instantiate RNG\n");
525 		return ret;
526 	}
527 
528 	 /* Enable RDB bit so that RNG works faster */
529 	sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
530 
531 	return ret;
532 }
533 
534 int sec_init(void)
535 {
536 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
537 	uint32_t mcr = sec_in32(&sec->mcfgr);
538 	int ret = 0;
539 
540 #ifdef CONFIG_FSL_CORENET
541 	uint32_t liodnr;
542 	uint32_t liodn_ns;
543 	uint32_t liodn_s;
544 #endif
545 
546 	/*
547 	 * Modifying CAAM Read/Write Attributes
548 	 * For LS2080A
549 	 * For AXI Write - Cacheable, Write Back, Write allocate
550 	 * For AXI Read - Cacheable, Read allocate
551 	 * Only For LS2080a, to solve CAAM coherency issues
552 	 */
553 #ifdef CONFIG_LS2080A
554 	mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
555 	mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
556 #else
557 	mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
558 #endif
559 
560 #ifdef CONFIG_PHYS_64BIT
561 	mcr |= (1 << MCFGR_PS_SHIFT);
562 #endif
563 	sec_out32(&sec->mcfgr, mcr);
564 
565 #ifdef CONFIG_FSL_CORENET
566 	liodnr = sec_in32(&sec->jrliodnr[0].ls);
567 	liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
568 	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
569 #endif
570 
571 	ret = jr_init();
572 	if (ret < 0) {
573 		printf("SEC initialization failed\n");
574 		return -1;
575 	}
576 
577 #ifdef CONFIG_FSL_CORENET
578 	ret = sec_config_pamu_table(liodn_ns, liodn_s);
579 	if (ret < 0)
580 		return -1;
581 
582 	pamu_enable();
583 #endif
584 
585 	if (get_rng_vid() >= 4) {
586 		if (rng_init() < 0) {
587 			printf("RNG instantiation failed\n");
588 			return -1;
589 		}
590 		printf("SEC: RNG instantiated\n");
591 	}
592 
593 	return ret;
594 }
595