xref: /openbmc/u-boot/drivers/crypto/fsl/jr.c (revision 9ee16897) 
1 /*
2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  *
6  * Based on CAAM driver in drivers/crypto/caam in Linux
7  */
8 
9 #include <common.h>
10 #include <malloc.h>
11 #include "fsl_sec.h"
12 #include "jr.h"
13 #include "jobdesc.h"
14 
15 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
16 #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
17 
18 struct jobring jr;
19 
20 static inline void start_jr0(void)
21 {
22 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
23 	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
24 	u32 scfgr = sec_in32(&sec->scfgr);
25 
26 	if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
27 		/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
28 		 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
29 		 */
30 		if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
31 		    (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
32 					(scfgr & SEC_SCFGR_VIRT_EN)))
33 			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
34 	} else {
35 		/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
36 		if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
37 			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
38 	}
39 }
40 
41 static inline void jr_reset_liodn(void)
42 {
43 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
44 	sec_out32(&sec->jrliodnr[0].ls, 0);
45 }
46 
47 static inline void jr_disable_irq(void)
48 {
49 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
50 	uint32_t jrcfg = sec_in32(&regs->jrcfg1);
51 
52 	jrcfg = jrcfg | JR_INTMASK;
53 
54 	sec_out32(&regs->jrcfg1, jrcfg);
55 }
56 
57 static void jr_initregs(void)
58 {
59 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
60 	phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
61 	phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
62 
63 #ifdef CONFIG_PHYS_64BIT
64 	sec_out32(&regs->irba_h, ip_base >> 32);
65 #else
66 	sec_out32(&regs->irba_h, 0x0);
67 #endif
68 	sec_out32(&regs->irba_l, (uint32_t)ip_base);
69 #ifdef CONFIG_PHYS_64BIT
70 	sec_out32(&regs->orba_h, op_base >> 32);
71 #else
72 	sec_out32(&regs->orba_h, 0x0);
73 #endif
74 	sec_out32(&regs->orba_l, (uint32_t)op_base);
75 	sec_out32(&regs->ors, JR_SIZE);
76 	sec_out32(&regs->irs, JR_SIZE);
77 
78 	if (!jr.irq)
79 		jr_disable_irq();
80 }
81 
82 static int jr_init(void)
83 {
84 	memset(&jr, 0, sizeof(struct jobring));
85 
86 	jr.jq_id = DEFAULT_JR_ID;
87 	jr.irq = DEFAULT_IRQ;
88 
89 #ifdef CONFIG_FSL_CORENET
90 	jr.liodn = DEFAULT_JR_LIODN;
91 #endif
92 	jr.size = JR_SIZE;
93 	jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
94 				JR_SIZE * sizeof(dma_addr_t));
95 	if (!jr.input_ring)
96 		return -1;
97 	jr.output_ring =
98 	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN,
99 				JR_SIZE * sizeof(struct op_ring));
100 	if (!jr.output_ring)
101 		return -1;
102 
103 	memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
104 	memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring));
105 
106 	start_jr0();
107 
108 	jr_initregs();
109 
110 	return 0;
111 }
112 
113 static int jr_sw_cleanup(void)
114 {
115 	jr.head = 0;
116 	jr.tail = 0;
117 	jr.read_idx = 0;
118 	jr.write_idx = 0;
119 	memset(jr.info, 0, sizeof(jr.info));
120 	memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
121 	memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
122 
123 	return 0;
124 }
125 
126 static int jr_hw_reset(void)
127 {
128 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
129 	uint32_t timeout = 100000;
130 	uint32_t jrint, jrcr;
131 
132 	sec_out32(&regs->jrcr, JRCR_RESET);
133 	do {
134 		jrint = sec_in32(&regs->jrint);
135 	} while (((jrint & JRINT_ERR_HALT_MASK) ==
136 		  JRINT_ERR_HALT_INPROGRESS) && --timeout);
137 
138 	jrint = sec_in32(&regs->jrint);
139 	if (((jrint & JRINT_ERR_HALT_MASK) !=
140 	     JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
141 		return -1;
142 
143 	timeout = 100000;
144 	sec_out32(&regs->jrcr, JRCR_RESET);
145 	do {
146 		jrcr = sec_in32(&regs->jrcr);
147 	} while ((jrcr & JRCR_RESET) && --timeout);
148 
149 	if (timeout == 0)
150 		return -1;
151 
152 	return 0;
153 }
154 
155 /* -1 --- error, can't enqueue -- no space available */
156 static int jr_enqueue(uint32_t *desc_addr,
157 	       void (*callback)(uint32_t desc, uint32_t status, void *arg),
158 	       void *arg)
159 {
160 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
161 	int head = jr.head;
162 	dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
163 
164 	if (sec_in32(&regs->irsa) == 0 ||
165 	    CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
166 		return -1;
167 
168 	jr.info[head].desc_phys_addr = desc_phys_addr;
169 	jr.info[head].desc_addr = (uint32_t)desc_addr;
170 	jr.info[head].callback = (void *)callback;
171 	jr.info[head].arg = arg;
172 	jr.info[head].op_done = 0;
173 
174 	unsigned long start = (unsigned long)&jr.info[head] &
175 					~(ARCH_DMA_MINALIGN - 1);
176 	unsigned long end = ALIGN(start + sizeof(struct jr_info),
177 					ARCH_DMA_MINALIGN);
178 	flush_dcache_range(start, end);
179 
180 	jr.input_ring[head] = desc_phys_addr;
181 	start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
182 	end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
183 	flush_dcache_range(start, end);
184 
185 	jr.head = (head + 1) & (jr.size - 1);
186 
187 	sec_out32(&regs->irja, 1);
188 
189 	return 0;
190 }
191 
192 static int jr_dequeue(void)
193 {
194 	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
195 	int head = jr.head;
196 	int tail = jr.tail;
197 	int idx, i, found;
198 	void (*callback)(uint32_t desc, uint32_t status, void *arg);
199 	void *arg = NULL;
200 
201 	while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
202 		unsigned long start = (unsigned long)jr.output_ring &
203 					~(ARCH_DMA_MINALIGN - 1);
204 		unsigned long end = ALIGN(start +
205 					  sizeof(struct op_ring)*JR_SIZE,
206 					  ARCH_DMA_MINALIGN);
207 		invalidate_dcache_range(start, end);
208 
209 		found = 0;
210 
211 		dma_addr_t op_desc = jr.output_ring[jr.tail].desc;
212 		uint32_t status = jr.output_ring[jr.tail].status;
213 		uint32_t desc_virt;
214 
215 		for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
216 			idx = (tail + i) & (jr.size - 1);
217 			if (op_desc == jr.info[idx].desc_phys_addr) {
218 				desc_virt = jr.info[idx].desc_addr;
219 				found = 1;
220 				break;
221 			}
222 		}
223 
224 		/* Error condition if match not found */
225 		if (!found)
226 			return -1;
227 
228 		jr.info[idx].op_done = 1;
229 		callback = (void *)jr.info[idx].callback;
230 		arg = jr.info[idx].arg;
231 
232 		/* When the job on tail idx gets done, increment
233 		 * tail till the point where job completed out of oredr has
234 		 * been taken into account
235 		 */
236 		if (idx == tail)
237 			do {
238 				tail = (tail + 1) & (jr.size - 1);
239 			} while (jr.info[tail].op_done);
240 
241 		jr.tail = tail;
242 		jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
243 
244 		sec_out32(&regs->orjr, 1);
245 		jr.info[idx].op_done = 0;
246 
247 		callback(desc_virt, status, arg);
248 	}
249 
250 	return 0;
251 }
252 
253 static void desc_done(uint32_t desc, uint32_t status, void *arg)
254 {
255 	struct result *x = arg;
256 	x->status = status;
257 	caam_jr_strstatus(status);
258 	x->done = 1;
259 }
260 
261 int run_descriptor_jr(uint32_t *desc)
262 {
263 	unsigned long long timeval = get_ticks();
264 	unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
265 	struct result op;
266 	int ret = 0;
267 
268 	memset(&op, 0, sizeof(op));
269 
270 	ret = jr_enqueue(desc, desc_done, &op);
271 	if (ret) {
272 		debug("Error in SEC enq\n");
273 		ret = JQ_ENQ_ERR;
274 		goto out;
275 	}
276 
277 	timeval = get_ticks();
278 	timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
279 	while (op.done != 1) {
280 		ret = jr_dequeue();
281 		if (ret) {
282 			debug("Error in SEC deq\n");
283 			ret = JQ_DEQ_ERR;
284 			goto out;
285 		}
286 
287 		if ((get_ticks() - timeval) > timeout) {
288 			debug("SEC Dequeue timed out\n");
289 			ret = JQ_DEQ_TO_ERR;
290 			goto out;
291 		}
292 	}
293 
294 	if (!op.status) {
295 		debug("Error %x\n", op.status);
296 		ret = op.status;
297 	}
298 out:
299 	return ret;
300 }
301 
302 int jr_reset(void)
303 {
304 	if (jr_hw_reset() < 0)
305 		return -1;
306 
307 	/* Clean up the jobring structure maintained by software */
308 	jr_sw_cleanup();
309 
310 	return 0;
311 }
312 
313 int sec_reset(void)
314 {
315 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
316 	uint32_t mcfgr = sec_in32(&sec->mcfgr);
317 	uint32_t timeout = 100000;
318 
319 	mcfgr |= MCFGR_SWRST;
320 	sec_out32(&sec->mcfgr, mcfgr);
321 
322 	mcfgr |= MCFGR_DMA_RST;
323 	sec_out32(&sec->mcfgr, mcfgr);
324 	do {
325 		mcfgr = sec_in32(&sec->mcfgr);
326 	} while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
327 
328 	if (timeout == 0)
329 		return -1;
330 
331 	timeout = 100000;
332 	do {
333 		mcfgr = sec_in32(&sec->mcfgr);
334 	} while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
335 
336 	if (timeout == 0)
337 		return -1;
338 
339 	return 0;
340 }
341 
342 static int instantiate_rng(void)
343 {
344 	struct result op;
345 	u32 *desc;
346 	u32 rdsta_val;
347 	int ret = 0;
348 	ccsr_sec_t __iomem *sec =
349 			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
350 	struct rng4tst __iomem *rng =
351 			(struct rng4tst __iomem *)&sec->rng;
352 
353 	memset(&op, 0, sizeof(struct result));
354 
355 	desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
356 	if (!desc) {
357 		printf("cannot allocate RNG init descriptor memory\n");
358 		return -1;
359 	}
360 
361 	inline_cnstr_jobdesc_rng_instantiation(desc);
362 	int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
363 	flush_dcache_range((unsigned long)desc,
364 			   (unsigned long)desc + size);
365 
366 	ret = run_descriptor_jr(desc);
367 
368 	if (ret)
369 		printf("RNG: Instantiation failed with error %x\n", ret);
370 
371 	rdsta_val = sec_in32(&rng->rdsta);
372 	if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
373 		return -1;
374 
375 	return ret;
376 }
377 
378 static u8 get_rng_vid(void)
379 {
380 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
381 	u32 cha_vid = sec_in32(&sec->chavid_ls);
382 
383 	return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
384 }
385 
386 /*
387  * By default, the TRNG runs for 200 clocks per sample;
388  * 1200 clocks per sample generates better entropy.
389  */
390 static void kick_trng(int ent_delay)
391 {
392 	ccsr_sec_t __iomem *sec =
393 			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
394 	struct rng4tst __iomem *rng =
395 			(struct rng4tst __iomem *)&sec->rng;
396 	u32 val;
397 
398 	/* put RNG4 into program mode */
399 	sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
400 	/* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
401 	 * length (in system clocks) of each Entropy sample taken
402 	 * */
403 	val = sec_in32(&rng->rtsdctl);
404 	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
405 	      (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
406 	sec_out32(&rng->rtsdctl, val);
407 	/* min. freq. count, equal to 1/4 of the entropy sample length */
408 	sec_out32(&rng->rtfreqmin, ent_delay >> 2);
409 	/* disable maximum frequency count */
410 	sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
411 	/* read the control register */
412 	val = sec_in32(&rng->rtmctl);
413 	/*
414 	 * select raw sampling in both entropy shifter
415 	 * and statistical checker
416 	 */
417 	sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
418 	/* put RNG4 into run mode */
419 	sec_clrbits32(&val, RTMCTL_PRGM);
420 	/* write back the control register */
421 	sec_out32(&rng->rtmctl, val);
422 }
423 
424 static int rng_init(void)
425 {
426 	int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
427 	ccsr_sec_t __iomem *sec =
428 			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
429 	struct rng4tst __iomem *rng =
430 			(struct rng4tst __iomem *)&sec->rng;
431 
432 	u32 rdsta = sec_in32(&rng->rdsta);
433 
434 	/* Check if RNG state 0 handler is already instantiated */
435 	if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
436 		return 0;
437 
438 	do {
439 		/*
440 		 * If either of the SH's were instantiated by somebody else
441 		 * then it is assumed that the entropy
442 		 * parameters are properly set and thus the function
443 		 * setting these (kick_trng(...)) is skipped.
444 		 * Also, if a handle was instantiated, do not change
445 		 * the TRNG parameters.
446 		 */
447 		kick_trng(ent_delay);
448 		ent_delay += 400;
449 		/*
450 		 * if instantiate_rng(...) fails, the loop will rerun
451 		 * and the kick_trng(...) function will modfiy the
452 		 * upper and lower limits of the entropy sampling
453 		 * interval, leading to a sucessful initialization of
454 		 * the RNG.
455 		 */
456 		ret = instantiate_rng();
457 	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
458 	if (ret) {
459 		printf("RNG: Failed to instantiate RNG\n");
460 		return ret;
461 	}
462 
463 	 /* Enable RDB bit so that RNG works faster */
464 	sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
465 
466 	return ret;
467 }
468 
469 int sec_init(void)
470 {
471 	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
472 	uint32_t mcr = sec_in32(&sec->mcfgr);
473 	int ret = 0;
474 
475 	mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
476 #ifdef CONFIG_PHYS_64BIT
477 	mcr |= (1 << MCFGR_PS_SHIFT);
478 #endif
479 	sec_out32(&sec->mcfgr, mcr);
480 
481 	ret = jr_init();
482 	if (ret < 0) {
483 		printf("SEC initialization failed\n");
484 		return -1;
485 	}
486 
487 	if (get_rng_vid() >= 4) {
488 		if (rng_init() < 0) {
489 			printf("RNG instantiation failed\n");
490 			return -1;
491 		}
492 		printf("SEC: RNG instantiated\n");
493 	}
494 
495 	return ret;
496 }
497