1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Based on CAAM driver in drivers/crypto/caam in Linux 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include "fsl_sec.h" 12 #include "jr.h" 13 #include "jobdesc.h" 14 #include "desc_constr.h" 15 16 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) 17 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) 18 19 struct jobring jr; 20 21 static inline void start_jr0(void) 22 { 23 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 24 u32 ctpr_ms = sec_in32(&sec->ctpr_ms); 25 u32 scfgr = sec_in32(&sec->scfgr); 26 27 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) { 28 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or 29 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1 30 */ 31 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) || 32 (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) && 33 (scfgr & SEC_SCFGR_VIRT_EN))) 34 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); 35 } else { 36 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ 37 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) 38 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); 39 } 40 } 41 42 static inline void jr_reset_liodn(void) 43 { 44 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 45 sec_out32(&sec->jrliodnr[0].ls, 0); 46 } 47 48 static inline void jr_disable_irq(void) 49 { 50 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; 51 uint32_t jrcfg = sec_in32(®s->jrcfg1); 52 53 jrcfg = jrcfg | JR_INTMASK; 54 55 sec_out32(®s->jrcfg1, jrcfg); 56 } 57 58 static void jr_initregs(void) 59 { 60 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; 61 phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring); 62 phys_addr_t op_base = virt_to_phys((void *)jr.output_ring); 63 64 #ifdef CONFIG_PHYS_64BIT 65 sec_out32(®s->irba_h, ip_base >> 32); 66 #else 67 sec_out32(®s->irba_h, 0x0); 68 #endif 69 sec_out32(®s->irba_l, (uint32_t)ip_base); 70 #ifdef CONFIG_PHYS_64BIT 71 sec_out32(®s->orba_h, op_base >> 32); 72 #else 73 sec_out32(®s->orba_h, 0x0); 74 #endif 75 sec_out32(®s->orba_l, (uint32_t)op_base); 76 sec_out32(®s->ors, JR_SIZE); 77 sec_out32(®s->irs, JR_SIZE); 78 79 if (!jr.irq) 80 jr_disable_irq(); 81 } 82 83 static int jr_init(void) 84 { 85 memset(&jr, 0, sizeof(struct jobring)); 86 87 jr.jq_id = DEFAULT_JR_ID; 88 jr.irq = DEFAULT_IRQ; 89 90 #ifdef CONFIG_FSL_CORENET 91 jr.liodn = DEFAULT_JR_LIODN; 92 #endif 93 jr.size = JR_SIZE; 94 jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, 95 JR_SIZE * sizeof(dma_addr_t)); 96 if (!jr.input_ring) 97 return -1; 98 jr.output_ring = 99 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, 100 JR_SIZE * sizeof(struct op_ring)); 101 if (!jr.output_ring) 102 return -1; 103 104 memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); 105 memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring)); 106 107 start_jr0(); 108 109 jr_initregs(); 110 111 return 0; 112 } 113 114 static int jr_sw_cleanup(void) 115 { 116 jr.head = 0; 117 jr.tail = 0; 118 jr.read_idx = 0; 119 jr.write_idx = 0; 120 memset(jr.info, 0, sizeof(jr.info)); 121 memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t)); 122 memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring)); 123 124 return 0; 125 } 126 127 static int jr_hw_reset(void) 128 { 129 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; 130 uint32_t timeout = 100000; 131 uint32_t jrint, jrcr; 132 133 sec_out32(®s->jrcr, JRCR_RESET); 134 do { 135 jrint = sec_in32(®s->jrint); 136 } while (((jrint & JRINT_ERR_HALT_MASK) == 137 JRINT_ERR_HALT_INPROGRESS) && --timeout); 138 139 jrint = sec_in32(®s->jrint); 140 if (((jrint & JRINT_ERR_HALT_MASK) != 141 JRINT_ERR_HALT_INPROGRESS) && timeout == 0) 142 return -1; 143 144 timeout = 100000; 145 sec_out32(®s->jrcr, JRCR_RESET); 146 do { 147 jrcr = sec_in32(®s->jrcr); 148 } while ((jrcr & JRCR_RESET) && --timeout); 149 150 if (timeout == 0) 151 return -1; 152 153 return 0; 154 } 155 156 /* -1 --- error, can't enqueue -- no space available */ 157 static int jr_enqueue(uint32_t *desc_addr, 158 void (*callback)(uint32_t status, void *arg), 159 void *arg) 160 { 161 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; 162 int head = jr.head; 163 uint32_t desc_word; 164 int length = desc_len(desc_addr); 165 int i; 166 #ifdef CONFIG_PHYS_64BIT 167 uint32_t *addr_hi, *addr_lo; 168 #endif 169 170 /* The descriptor must be submitted to SEC block as per endianness 171 * of the SEC Block. 172 * So, if the endianness of Core and SEC block is different, each word 173 * of the descriptor will be byte-swapped. 174 */ 175 for (i = 0; i < length; i++) { 176 desc_word = desc_addr[i]; 177 sec_out32((uint32_t *)&desc_addr[i], desc_word); 178 } 179 180 phys_addr_t desc_phys_addr = virt_to_phys(desc_addr); 181 182 if (sec_in32(®s->irsa) == 0 || 183 CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0) 184 return -1; 185 186 jr.info[head].desc_phys_addr = desc_phys_addr; 187 jr.info[head].callback = (void *)callback; 188 jr.info[head].arg = arg; 189 jr.info[head].op_done = 0; 190 191 unsigned long start = (unsigned long)&jr.info[head] & 192 ~(ARCH_DMA_MINALIGN - 1); 193 unsigned long end = ALIGN(start + sizeof(struct jr_info), 194 ARCH_DMA_MINALIGN); 195 flush_dcache_range(start, end); 196 197 #ifdef CONFIG_PHYS_64BIT 198 /* Write the 64 bit Descriptor address on Input Ring. 199 * The 32 bit hign and low part of the address will 200 * depend on endianness of SEC block. 201 */ 202 #ifdef CONFIG_SYS_FSL_SEC_LE 203 addr_lo = (uint32_t *)(&jr.input_ring[head]); 204 addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1; 205 #elif defined(CONFIG_SYS_FSL_SEC_BE) 206 addr_hi = (uint32_t *)(&jr.input_ring[head]); 207 addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1; 208 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ 209 210 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32)); 211 sec_out32(addr_lo, (uint32_t)(desc_phys_addr)); 212 213 #else 214 /* Write the 32 bit Descriptor address on Input Ring. */ 215 sec_out32(&jr.input_ring[head], desc_phys_addr); 216 #endif /* ifdef CONFIG_PHYS_64BIT */ 217 218 start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); 219 end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN); 220 flush_dcache_range(start, end); 221 222 jr.head = (head + 1) & (jr.size - 1); 223 224 sec_out32(®s->irja, 1); 225 226 return 0; 227 } 228 229 static int jr_dequeue(void) 230 { 231 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; 232 int head = jr.head; 233 int tail = jr.tail; 234 int idx, i, found; 235 void (*callback)(uint32_t status, void *arg); 236 void *arg = NULL; 237 #ifdef CONFIG_PHYS_64BIT 238 uint32_t *addr_hi, *addr_lo; 239 #else 240 uint32_t *addr; 241 #endif 242 243 while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { 244 unsigned long start = (unsigned long)jr.output_ring & 245 ~(ARCH_DMA_MINALIGN - 1); 246 unsigned long end = ALIGN(start + 247 sizeof(struct op_ring)*JR_SIZE, 248 ARCH_DMA_MINALIGN); 249 invalidate_dcache_range(start, end); 250 251 found = 0; 252 253 phys_addr_t op_desc; 254 #ifdef CONFIG_PHYS_64BIT 255 /* Read the 64 bit Descriptor address from Output Ring. 256 * The 32 bit hign and low part of the address will 257 * depend on endianness of SEC block. 258 */ 259 #ifdef CONFIG_SYS_FSL_SEC_LE 260 addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc); 261 addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1; 262 #elif defined(CONFIG_SYS_FSL_SEC_BE) 263 addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc); 264 addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1; 265 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */ 266 267 op_desc = ((u64)sec_in32(addr_hi) << 32) | 268 ((u64)sec_in32(addr_lo)); 269 270 #else 271 /* Read the 32 bit Descriptor address from Output Ring. */ 272 addr = (uint32_t *)&jr.output_ring[jr.tail].desc; 273 op_desc = sec_in32(addr); 274 #endif /* ifdef CONFIG_PHYS_64BIT */ 275 276 uint32_t status = sec_in32(&jr.output_ring[jr.tail].status); 277 278 for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) { 279 idx = (tail + i) & (jr.size - 1); 280 if (op_desc == jr.info[idx].desc_phys_addr) { 281 found = 1; 282 break; 283 } 284 } 285 286 /* Error condition if match not found */ 287 if (!found) 288 return -1; 289 290 jr.info[idx].op_done = 1; 291 callback = (void *)jr.info[idx].callback; 292 arg = jr.info[idx].arg; 293 294 /* When the job on tail idx gets done, increment 295 * tail till the point where job completed out of oredr has 296 * been taken into account 297 */ 298 if (idx == tail) 299 do { 300 tail = (tail + 1) & (jr.size - 1); 301 } while (jr.info[tail].op_done); 302 303 jr.tail = tail; 304 jr.read_idx = (jr.read_idx + 1) & (jr.size - 1); 305 306 sec_out32(®s->orjr, 1); 307 jr.info[idx].op_done = 0; 308 309 callback(status, arg); 310 } 311 312 return 0; 313 } 314 315 static void desc_done(uint32_t status, void *arg) 316 { 317 struct result *x = arg; 318 x->status = status; 319 caam_jr_strstatus(status); 320 x->done = 1; 321 } 322 323 int run_descriptor_jr(uint32_t *desc) 324 { 325 unsigned long long timeval = get_ticks(); 326 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); 327 struct result op; 328 int ret = 0; 329 330 memset(&op, 0, sizeof(op)); 331 332 ret = jr_enqueue(desc, desc_done, &op); 333 if (ret) { 334 debug("Error in SEC enq\n"); 335 ret = JQ_ENQ_ERR; 336 goto out; 337 } 338 339 timeval = get_ticks(); 340 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); 341 while (op.done != 1) { 342 ret = jr_dequeue(); 343 if (ret) { 344 debug("Error in SEC deq\n"); 345 ret = JQ_DEQ_ERR; 346 goto out; 347 } 348 349 if ((get_ticks() - timeval) > timeout) { 350 debug("SEC Dequeue timed out\n"); 351 ret = JQ_DEQ_TO_ERR; 352 goto out; 353 } 354 } 355 356 if (!op.status) { 357 debug("Error %x\n", op.status); 358 ret = op.status; 359 } 360 out: 361 return ret; 362 } 363 364 int jr_reset(void) 365 { 366 if (jr_hw_reset() < 0) 367 return -1; 368 369 /* Clean up the jobring structure maintained by software */ 370 jr_sw_cleanup(); 371 372 return 0; 373 } 374 375 int sec_reset(void) 376 { 377 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 378 uint32_t mcfgr = sec_in32(&sec->mcfgr); 379 uint32_t timeout = 100000; 380 381 mcfgr |= MCFGR_SWRST; 382 sec_out32(&sec->mcfgr, mcfgr); 383 384 mcfgr |= MCFGR_DMA_RST; 385 sec_out32(&sec->mcfgr, mcfgr); 386 do { 387 mcfgr = sec_in32(&sec->mcfgr); 388 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout); 389 390 if (timeout == 0) 391 return -1; 392 393 timeout = 100000; 394 do { 395 mcfgr = sec_in32(&sec->mcfgr); 396 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout); 397 398 if (timeout == 0) 399 return -1; 400 401 return 0; 402 } 403 404 static int instantiate_rng(void) 405 { 406 struct result op; 407 u32 *desc; 408 u32 rdsta_val; 409 int ret = 0; 410 ccsr_sec_t __iomem *sec = 411 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 412 struct rng4tst __iomem *rng = 413 (struct rng4tst __iomem *)&sec->rng; 414 415 memset(&op, 0, sizeof(struct result)); 416 417 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6); 418 if (!desc) { 419 printf("cannot allocate RNG init descriptor memory\n"); 420 return -1; 421 } 422 423 inline_cnstr_jobdesc_rng_instantiation(desc); 424 int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN); 425 flush_dcache_range((unsigned long)desc, 426 (unsigned long)desc + size); 427 428 ret = run_descriptor_jr(desc); 429 430 if (ret) 431 printf("RNG: Instantiation failed with error %x\n", ret); 432 433 rdsta_val = sec_in32(&rng->rdsta); 434 if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED)) 435 return -1; 436 437 return ret; 438 } 439 440 static u8 get_rng_vid(void) 441 { 442 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 443 u32 cha_vid = sec_in32(&sec->chavid_ls); 444 445 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT; 446 } 447 448 /* 449 * By default, the TRNG runs for 200 clocks per sample; 450 * 1200 clocks per sample generates better entropy. 451 */ 452 static void kick_trng(int ent_delay) 453 { 454 ccsr_sec_t __iomem *sec = 455 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 456 struct rng4tst __iomem *rng = 457 (struct rng4tst __iomem *)&sec->rng; 458 u32 val; 459 460 /* put RNG4 into program mode */ 461 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM); 462 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the 463 * length (in system clocks) of each Entropy sample taken 464 * */ 465 val = sec_in32(&rng->rtsdctl); 466 val = (val & ~RTSDCTL_ENT_DLY_MASK) | 467 (ent_delay << RTSDCTL_ENT_DLY_SHIFT); 468 sec_out32(&rng->rtsdctl, val); 469 /* min. freq. count, equal to 1/4 of the entropy sample length */ 470 sec_out32(&rng->rtfreqmin, ent_delay >> 2); 471 /* disable maximum frequency count */ 472 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE); 473 /* read the control register */ 474 val = sec_in32(&rng->rtmctl); 475 /* 476 * select raw sampling in both entropy shifter 477 * and statistical checker 478 */ 479 sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC); 480 /* put RNG4 into run mode */ 481 sec_clrbits32(&val, RTMCTL_PRGM); 482 /* write back the control register */ 483 sec_out32(&rng->rtmctl, val); 484 } 485 486 static int rng_init(void) 487 { 488 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN; 489 ccsr_sec_t __iomem *sec = 490 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 491 struct rng4tst __iomem *rng = 492 (struct rng4tst __iomem *)&sec->rng; 493 494 u32 rdsta = sec_in32(&rng->rdsta); 495 496 /* Check if RNG state 0 handler is already instantiated */ 497 if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) 498 return 0; 499 500 do { 501 /* 502 * If either of the SH's were instantiated by somebody else 503 * then it is assumed that the entropy 504 * parameters are properly set and thus the function 505 * setting these (kick_trng(...)) is skipped. 506 * Also, if a handle was instantiated, do not change 507 * the TRNG parameters. 508 */ 509 kick_trng(ent_delay); 510 ent_delay += 400; 511 /* 512 * if instantiate_rng(...) fails, the loop will rerun 513 * and the kick_trng(...) function will modfiy the 514 * upper and lower limits of the entropy sampling 515 * interval, leading to a sucessful initialization of 516 * the RNG. 517 */ 518 ret = instantiate_rng(); 519 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); 520 if (ret) { 521 printf("RNG: Failed to instantiate RNG\n"); 522 return ret; 523 } 524 525 /* Enable RDB bit so that RNG works faster */ 526 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE); 527 528 return ret; 529 } 530 531 int sec_init(void) 532 { 533 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 534 uint32_t mcr = sec_in32(&sec->mcfgr); 535 int ret = 0; 536 537 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); 538 #ifdef CONFIG_PHYS_64BIT 539 mcr |= (1 << MCFGR_PS_SHIFT); 540 #endif 541 sec_out32(&sec->mcfgr, mcr); 542 543 ret = jr_init(); 544 if (ret < 0) { 545 printf("SEC initialization failed\n"); 546 return -1; 547 } 548 549 if (get_rng_vid() >= 4) { 550 if (rng_init() < 0) { 551 printf("RNG instantiation failed\n"); 552 return -1; 553 } 554 printf("SEC: RNG instantiated\n"); 555 } 556 557 return ret; 558 } 559