1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <stm32_rcc.h> 12 13 #include <asm/io.h> 14 #include <asm/arch/stm32.h> 15 #include <asm/arch/stm32_pwr.h> 16 17 #include <dt-bindings/mfd/stm32f7-rcc.h> 18 19 #define RCC_CR_HSION BIT(0) 20 #define RCC_CR_HSEON BIT(16) 21 #define RCC_CR_HSERDY BIT(17) 22 #define RCC_CR_HSEBYP BIT(18) 23 #define RCC_CR_CSSON BIT(19) 24 #define RCC_CR_PLLON BIT(24) 25 #define RCC_CR_PLLRDY BIT(25) 26 #define RCC_CR_PLLSAION BIT(28) 27 #define RCC_CR_PLLSAIRDY BIT(29) 28 29 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) 30 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) 31 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) 32 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) 33 #define RCC_PLLCFGR_PLLSRC BIT(22) 34 #define RCC_PLLCFGR_PLLM_SHIFT 0 35 #define RCC_PLLCFGR_PLLN_SHIFT 6 36 #define RCC_PLLCFGR_PLLP_SHIFT 16 37 #define RCC_PLLCFGR_PLLQ_SHIFT 24 38 39 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) 40 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) 41 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) 42 #define RCC_CFGR_SW0 BIT(0) 43 #define RCC_CFGR_SW1 BIT(1) 44 #define RCC_CFGR_SW_MASK GENMASK(1, 0) 45 #define RCC_CFGR_SW_HSI 0 46 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 47 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 48 #define RCC_CFGR_SWS0 BIT(2) 49 #define RCC_CFGR_SWS1 BIT(3) 50 #define RCC_CFGR_SWS_MASK GENMASK(3, 2) 51 #define RCC_CFGR_SWS_HSI 0 52 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 53 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 54 #define RCC_CFGR_HPRE_SHIFT 4 55 #define RCC_CFGR_PPRE1_SHIFT 10 56 #define RCC_CFGR_PPRE2_SHIFT 13 57 58 #define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6) 59 #define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) 60 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 61 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 62 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17) 63 #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) 64 #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) 65 66 #define RCC_DCKCFGRX_CK48MSEL BIT(27) 67 #define RCC_DCKCFGRX_SDMMC1SEL BIT(28) 68 #define RCC_DCKCFGR2_SDMMC2SEL BIT(29) 69 70 #define RCC_APB2ENR_SAI1EN BIT(22) 71 72 /* 73 * RCC AHB1ENR specific definitions 74 */ 75 #define RCC_AHB1ENR_ETHMAC_EN BIT(25) 76 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) 77 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) 78 79 /* 80 * RCC APB1ENR specific definitions 81 */ 82 #define RCC_APB1ENR_TIM2EN BIT(0) 83 #define RCC_APB1ENR_PWREN BIT(28) 84 85 /* 86 * RCC APB2ENR specific definitions 87 */ 88 #define RCC_APB2ENR_SYSCFGEN BIT(14) 89 90 enum periph_clock { 91 SYSCFG_CLOCK_CFG, 92 TIMER2_CLOCK_CFG, 93 STMMAC_CLOCK_CFG, 94 }; 95 96 static const struct stm32_clk_info stm32f4_clk_info = { 97 /* 180 MHz */ 98 .sys_pll_psc = { 99 .pll_n = 360, 100 .pll_p = 2, 101 .pll_q = 8, 102 .ahb_psc = AHB_PSC_1, 103 .apb1_psc = APB_PSC_4, 104 .apb2_psc = APB_PSC_2, 105 }, 106 .has_overdrive = false, 107 .v2 = false, 108 }; 109 110 static const struct stm32_clk_info stm32f7_clk_info = { 111 /* 200 MHz */ 112 .sys_pll_psc = { 113 .pll_n = 400, 114 .pll_p = 2, 115 .pll_q = 8, 116 .ahb_psc = AHB_PSC_1, 117 .apb1_psc = APB_PSC_4, 118 .apb2_psc = APB_PSC_2, 119 }, 120 .has_overdrive = true, 121 .v2 = true, 122 }; 123 124 struct stm32_clk { 125 struct stm32_rcc_regs *base; 126 struct stm32_pwr_regs *pwr_regs; 127 struct stm32_clk_info info; 128 unsigned long hse_rate; 129 }; 130 131 static int configure_clocks(struct udevice *dev) 132 { 133 struct stm32_clk *priv = dev_get_priv(dev); 134 struct stm32_rcc_regs *regs = priv->base; 135 struct stm32_pwr_regs *pwr = priv->pwr_regs; 136 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; 137 u32 pllsaicfgr = 0; 138 139 /* Reset RCC configuration */ 140 setbits_le32(®s->cr, RCC_CR_HSION); 141 writel(0, ®s->cfgr); /* Reset CFGR */ 142 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON 143 | RCC_CR_PLLON | RCC_CR_PLLSAION)); 144 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ 145 clrbits_le32(®s->cr, RCC_CR_HSEBYP); 146 writel(0, ®s->cir); /* Disable all interrupts */ 147 148 /* Configure for HSE+PLL operation */ 149 setbits_le32(®s->cr, RCC_CR_HSEON); 150 while (!(readl(®s->cr) & RCC_CR_HSERDY)) 151 ; 152 153 setbits_le32(®s->cfgr, (( 154 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT) 155 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT) 156 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT))); 157 158 /* Configure the main PLL */ 159 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ 160 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK, 161 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT); 162 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK, 163 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT); 164 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK, 165 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); 166 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, 167 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT); 168 169 /* Configure the SAI PLL to get a 48 MHz source */ 170 pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 | 171 RCC_PLLSAICFGR_PLLSAIP_4; 172 pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT; 173 writel(pllsaicfgr, ®s->pllsaicfgr); 174 175 /* Enable the main PLL */ 176 setbits_le32(®s->cr, RCC_CR_PLLON); 177 while (!(readl(®s->cr) & RCC_CR_PLLRDY)) 178 ; 179 180 if (priv->info.v2) { /*stm32f7 case */ 181 /* select PLLSAI as 48MHz clock source */ 182 setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); 183 184 /* select 48MHz as SDMMC1 clock source */ 185 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL); 186 187 /* select 48MHz as SDMMC2 clock source */ 188 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL); 189 } else { /* stm32f4 case */ 190 /* select PLLSAI as 48MHz clock source */ 191 setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); 192 193 /* select 48MHz as SDMMC1 clock source */ 194 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); 195 } 196 197 /* Enable the SAI PLL */ 198 setbits_le32(®s->cr, RCC_CR_PLLSAION); 199 while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) 200 ; 201 202 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); 203 204 if (priv->info.has_overdrive) { 205 /* 206 * Enable high performance mode 207 * System frequency up to 200 MHz 208 */ 209 setbits_le32(&pwr->cr1, PWR_CR1_ODEN); 210 /* Infinite wait! */ 211 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) 212 ; 213 /* Enable the Over-drive switch */ 214 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN); 215 /* Infinite wait! */ 216 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) 217 ; 218 } 219 220 stm32_flash_latency_cfg(5); 221 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); 222 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); 223 224 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != 225 RCC_CFGR_SWS_PLL) 226 ; 227 /* gate the SAI clock, needed for MMC 1&2 clocks */ 228 setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN); 229 230 return 0; 231 } 232 233 static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, 234 u32 sysclk) 235 { 236 struct stm32_rcc_regs *regs = priv->base; 237 u16 pllq, pllm, pllsain, pllsaip; 238 bool pllsai; 239 240 pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) 241 >> RCC_PLLCFGR_PLLQ_SHIFT; 242 243 if (priv->info.v2) /*stm32f7 case */ 244 pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; 245 else 246 pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; 247 248 if (pllsai) { 249 /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ 250 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); 251 pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK) 252 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); 253 pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) 254 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); 255 return ((priv->hse_rate / pllm) * pllsain) / pllsaip; 256 } 257 /* PLL48CLK is selected from PLLQ */ 258 return sysclk / pllq; 259 } 260 261 static unsigned long stm32_clk_get_rate(struct clk *clk) 262 { 263 struct stm32_clk *priv = dev_get_priv(clk->dev); 264 struct stm32_rcc_regs *regs = priv->base; 265 u32 sysclk = 0; 266 u32 shift = 0; 267 u16 pllm, plln, pllp; 268 /* Prescaler table lookups for clock computation */ 269 u8 ahb_psc_table[16] = { 270 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 271 }; 272 u8 apb_psc_table[8] = { 273 0, 0, 0, 0, 1, 2, 3, 4 274 }; 275 276 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == 277 RCC_CFGR_SWS_PLL) { 278 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); 279 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) 280 >> RCC_PLLCFGR_PLLN_SHIFT); 281 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) 282 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); 283 sysclk = ((priv->hse_rate / pllm) * plln) / pllp; 284 } else { 285 return -EINVAL; 286 } 287 288 switch (clk->id) { 289 /* 290 * AHB CLOCK: 3 x 32 bits consecutive registers are used : 291 * AHB1, AHB2 and AHB3 292 */ 293 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI): 294 shift = ahb_psc_table[( 295 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) 296 >> RCC_CFGR_HPRE_SHIFT)]; 297 return sysclk >>= shift; 298 /* APB1 CLOCK */ 299 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): 300 shift = apb_psc_table[( 301 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) 302 >> RCC_CFGR_PPRE1_SHIFT)]; 303 return sysclk >>= shift; 304 /* APB2 CLOCK */ 305 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): 306 /* 307 * particular case for SDMMC1 and SDMMC2 : 308 * 48Mhz source clock can be from main PLL or from 309 * SAI PLL 310 */ 311 switch (clk->id) { 312 case STM32F7_APB2_CLOCK(SDMMC1): 313 if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL) 314 /* System clock is selected as SDMMC1 clock */ 315 return sysclk; 316 else 317 return stm32_clk_pll48clk_rate(priv, sysclk); 318 break; 319 case STM32F7_APB2_CLOCK(SDMMC2): 320 if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) 321 /* System clock is selected as SDMMC2 clock */ 322 return sysclk; 323 else 324 return stm32_clk_pll48clk_rate(priv, sysclk); 325 break; 326 } 327 328 shift = apb_psc_table[( 329 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) 330 >> RCC_CFGR_PPRE2_SHIFT)]; 331 return sysclk >>= shift; 332 default: 333 pr_err("clock index %ld out of range\n", clk->id); 334 return -EINVAL; 335 } 336 } 337 338 static int stm32_clk_enable(struct clk *clk) 339 { 340 struct stm32_clk *priv = dev_get_priv(clk->dev); 341 struct stm32_rcc_regs *regs = priv->base; 342 u32 offset = clk->id / 32; 343 u32 bit_index = clk->id % 32; 344 345 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", 346 __func__, clk->id, offset, bit_index); 347 setbits_le32(®s->ahb1enr + offset, BIT(bit_index)); 348 349 return 0; 350 } 351 352 void clock_setup(int peripheral) 353 { 354 switch (peripheral) { 355 case SYSCFG_CLOCK_CFG: 356 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); 357 break; 358 case TIMER2_CLOCK_CFG: 359 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); 360 break; 361 case STMMAC_CLOCK_CFG: 362 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN); 363 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); 364 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); 365 break; 366 default: 367 break; 368 } 369 } 370 371 static int stm32_clk_probe(struct udevice *dev) 372 { 373 struct ofnode_phandle_args args; 374 struct udevice *fixed_clock_dev = NULL; 375 struct clk clk; 376 int err; 377 378 debug("%s\n", __func__); 379 380 struct stm32_clk *priv = dev_get_priv(dev); 381 fdt_addr_t addr; 382 383 addr = dev_read_addr(dev); 384 if (addr == FDT_ADDR_T_NONE) 385 return -EINVAL; 386 387 priv->base = (struct stm32_rcc_regs *)addr; 388 389 switch (dev_get_driver_data(dev)) { 390 case STM32F4: 391 memcpy(&priv->info, &stm32f4_clk_info, 392 sizeof(struct stm32_clk_info)); 393 break; 394 case STM32F7: 395 memcpy(&priv->info, &stm32f7_clk_info, 396 sizeof(struct stm32_clk_info)); 397 break; 398 default: 399 return -EINVAL; 400 } 401 402 /* retrieve HSE frequency (external oscillator) */ 403 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse", 404 &fixed_clock_dev); 405 406 if (err) { 407 pr_err("Can't find fixed clock (%d)", err); 408 return err; 409 } 410 411 err = clk_request(fixed_clock_dev, &clk); 412 if (err) { 413 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name, 414 err); 415 return err; 416 } 417 418 /* 419 * set pllm factor accordingly to the external oscillator 420 * frequency (HSE). For STM32F4 and STM32F7, we want VCO 421 * freq at 1MHz 422 * if input PLL frequency is 25Mhz, divide it by 25 423 */ 424 clk.id = 0; 425 priv->hse_rate = clk_get_rate(&clk); 426 427 if (priv->hse_rate < 1000000) { 428 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__, 429 priv->hse_rate); 430 return -EINVAL; 431 } 432 433 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000; 434 435 if (priv->info.has_overdrive) { 436 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, 437 &args); 438 if (err) { 439 debug("%s: can't find syscon device (%d)\n", __func__, 440 err); 441 return err; 442 } 443 444 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node); 445 } 446 447 configure_clocks(dev); 448 449 return 0; 450 } 451 452 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) 453 { 454 debug("%s(clk=%p)\n", __func__, clk); 455 456 if (args->args_count != 2) { 457 debug("Invaild args_count: %d\n", args->args_count); 458 return -EINVAL; 459 } 460 461 if (args->args_count) 462 clk->id = args->args[1]; 463 else 464 clk->id = 0; 465 466 return 0; 467 } 468 469 static struct clk_ops stm32_clk_ops = { 470 .of_xlate = stm32_clk_of_xlate, 471 .enable = stm32_clk_enable, 472 .get_rate = stm32_clk_get_rate, 473 }; 474 475 U_BOOT_DRIVER(stm32fx_clk) = { 476 .name = "stm32fx_rcc_clock", 477 .id = UCLASS_CLK, 478 .ops = &stm32_clk_ops, 479 .probe = stm32_clk_probe, 480 .priv_auto_alloc_size = sizeof(struct stm32_clk), 481 .flags = DM_FLAG_PRE_RELOC, 482 }; 483